Introduce a register fence instruction to force all registers to be spilled (514374, r=edwsmith,rreitmai).

js/src/jsregexp.cpp

@@ -3001,11 +3001,13 @@ class RegExpNativeCompiler {
 
         /* Fall-through from compileNode means success. */
         lir->insStorei(pos, state, offsetof(REGlobalData, stateStack));
+        lir->ins0(LIR_regfence);
         lir->ins1(LIR_ret, lir->insImm(1));
 
         /* Stick return here so we don't have to jump over it every time. */
         if (anchorFail) {
             targetCurrentPoint(anchorFail);
+            lir->ins0(LIR_regfence);
             lir->ins1(LIR_ret, lir->insImm(0));
         }
 
@@ -3021,6 +3023,7 @@ class RegExpNativeCompiler {
             return false;
 
         /* Failed to match on first character, so fail whole match. */
+        lir->ins0(LIR_regfence);
         lir->ins1(LIR_ret, lir->insImm(0));
         return !JS_TRACE_MONITOR(cx).reAllocator->outOfMemory();
     }

js/src/nanojit/Assembler.cpp

@@ -884,6 +884,10 @@ namespace nanojit
                     NanoAssertMsgf(false, "unsupported LIR instruction: %d (~0x40: %d)\n", op, op&~LIR64);
                     break;
 
+                case LIR_regfence:
+                    evictRegs(~_allocator.free);
+                    break;
+
                 case LIR_flive:
                 case LIR_live: {
                     countlir_live();

js/src/nanojit/LIR.cpp

@@ -1701,6 +1701,7 @@ namespace nanojit
             }
 
             case LIR_start:
+            case LIR_regfence:
                 VMPI_sprintf(s, "%s", lirNames[op]);
                 break;
 

js/src/nanojit/LIR.h

@@ -786,7 +786,7 @@ namespace nanojit
             return isGuard() || isBranch() ||
                    (isCall() && !isCse()) ||
                    isStore() ||
-                   isop(LIR_label) || isop(LIR_live) ||
+                   isop(LIR_label) || isop(LIR_live) || isop(LIR_regfence) ||
                    isRet();
         }
 

js/src/nanojit/LIRopcode.tbl

@@ -72,7 +72,7 @@
 
 /* special operations (must be 0..N) */
 OPDEF(start,     0, 0, Op0)     // start of a fragment
-OPDEF(unused1,   1,-1, None)
+OPDEF(regfence,  1, 0, Op0)     // register fence, no register allocation is allowed across this meta instruction
 OPDEF(skip,      2, 1, Sk)      // holds blobs ("payloads") of data;  also links pages
 OPDEF(unused3,   3,-1, None)
 OPDEF(unused4,   4,-1, None)