Add support for LIR_stb on PPC (bug 558597 r=leon.sha pending)

Pushing this in advance of review; It appears to run fine in the tamarin-redux
acceptance suite, and i tested it also by stopping in asm_store32() with dbx,
and disassembling the generated STB instruction.  Looked fine to the naked eye.

--HG--
extra : convert_revision : 1e26f7116dc4435461b56900454b02fa821a9e54

js/src/nanojit/NativeSparc.cpp

@@ -278,9 +278,9 @@ namespace nanojit
     {
         switch (op) {
             case LIR_sti:
+            case LIR_stb:
                 // handled by mainline code below for now
                 break;
-            case LIR_stb:
             case LIR_sts:
                 NanoAssertMsg(0, "NJ_EXPANDED_LOADSTORE_SUPPORTED not yet supported for this architecture");
                 return;
@@ -294,7 +294,14 @@ namespace nanojit
             {
                 Register rb = getBaseReg(base, dr, GpRegs);
                 int c = value->imm32();
-                STW32(L2, dr, rb);
+                switch (op) {
+                case LIR_sti:
+                    STW32(L2, dr, rb);
+                    break;
+                case LIR_stb:
+                    STB32(L2, dr, rb);
+                    break;
+                }
                 SET32(c, L2);
             }
         else
@@ -309,7 +316,14 @@ namespace nanojit
                 } else {
                     getBaseReg2(GpRegs, value, ra, GpRegs, base, rb, dr);
                 }
-                STW32(ra, dr, rb);
+                switch (op) {
+                case LIR_sti:
+                    STW32(ra, dr, rb);
+                    break;
+                case LIR_stb:
+                    STB32(ra, dr, rb);
+                    break;
+                }
             }
     }
 

js/src/nanojit/NativeSparc.h

@@ -841,6 +841,19 @@ namespace nanojit
     asm_output("st %s, [%s + %d]", gpn(rd), gpn(rs1), simm13); \
     } while (0)
 
+#define STB(rd, rs2, rs1) \
+    do { \
+    Format_3_1(3, rd, 0x5, rs1, 0, rs2); \
+    asm_output("stb %s, [%s + %s]", gpn(rd), gpn(rs1), gpn(rs2)); \
+    } while (0)
+
+#define STBI(rd, simm13, rs1) \
+    do { \
+    Format_3_1I(3, rd, 0x5, rs1, simm13); \
+    asm_output("stb %s, [%s + %d]", gpn(rd), gpn(rs1), simm13); \
+    } while (0)
+
+
 #define SUBCC(rs1, rs2, rd) \
     do { \
     Format_3_1(2, rd, 0x14, rs1, 0, rs2); \
@@ -921,6 +934,14 @@ namespace nanojit
       SET32(imm32, L0); \
     }
 
+#define STB32(rd, imm32, rs1) \
+    if(isIMM13(imm32)) { \
+      STBI(rd, imm32, rs1); \
+    } else { \
+      STB(rd, L0, rs1); \
+      SET32(imm32, L0); \
+    }
+
 #define LDUB32(rs1, imm32, rd) \
     if(isIMM13(imm32)) { \
       LDUBI(rs1, imm32, rd); \