зеркало из https://github.com/mozilla/gecko-dev.git
Clean up asm_branch and correct the use of condition flags on VFP conditions. (489583, r=vladimir)
This commit is contained in:
Jacob Bramley
Родитель
fbc6d7224b
Коммит
074631d53c
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@ -284,6 +284,7 @@ Assembler::asm_arg(ArgSize sz, LInsp arg, Register& r, int& stkd)
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// handle qjoin first; won't ever show up if VFP is available
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if (arg->isop(LIR_qjoin)) {
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NanoAssert(!AvmCore::config.vfp);
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asm_arg(ARGSIZE_LO, arg->oprnd1(), r, stkd);
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asm_arg(ARGSIZE_LO, arg->oprnd2(), r, stkd);
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} else if (!argRes || argRes->reg == UnknownReg || !AvmCore::config.vfp) {
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@ -1427,93 +1428,67 @@ Assembler::asm_branch(bool branchOnFalse, LInsp cond, NIns* targ, bool isfar)
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// XXX noone actually uses the far param in nj anyway... (always false)
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(void)isfar;
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NIns* at = 0;
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LOpcode condop = cond->opcode();
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NanoAssert(cond->isCond());
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if (condop >= LIR_feq && condop <= LIR_fge)
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// The old "never" condition code has special meaning on newer ARM cores,
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// so use "always" as a sensible default code.
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ConditionCode cc = AL;
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// Detect whether or not this is a floating-point comparison.
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bool fp_cond;
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// Select the appropriate ARM condition code to match the LIR instruction.
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switch (condop)
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{
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ConditionCode cc = NV;
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// Floating-point conditions. Note that the VFP LT/LE conditions
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// require use of the unsigned condition codes, even though
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// float-point comparisons are always signed.
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case LIR_feq: cc = EQ; fp_cond = true; break;
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case LIR_flt: cc = LO; fp_cond = true; break;
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case LIR_fle: cc = LS; fp_cond = true; break;
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case LIR_fge: cc = GE; fp_cond = true; break;
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case LIR_fgt: cc = GT; fp_cond = true; break;
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if (branchOnFalse) {
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switch (condop) {
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case LIR_feq: cc = NE; break;
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case LIR_flt: cc = PL; break;
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case LIR_fgt: cc = LE; break;
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case LIR_fle: cc = HI; break;
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case LIR_fge: cc = LT; break;
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default: NanoAssert(0); break;
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}
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} else {
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switch (condop) {
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case LIR_feq: cc = EQ; break;
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case LIR_flt: cc = MI; break;
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case LIR_fgt: cc = GT; break;
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case LIR_fle: cc = LS; break;
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case LIR_fge: cc = GE; break;
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default: NanoAssert(0); break;
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}
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}
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// Standard signed and unsigned integer comparisons.
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case LIR_eq: cc = EQ; fp_cond = false; break;
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case LIR_ov: cc = VS; fp_cond = false; break;
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case LIR_cs: cc = CS; fp_cond = false; break;
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case LIR_lt: cc = LT; fp_cond = false; break;
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case LIR_le: cc = LE; fp_cond = false; break;
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case LIR_gt: cc = GT; fp_cond = false; break;
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case LIR_ge: cc = GE; fp_cond = false; break;
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case LIR_ult: cc = LO; fp_cond = false; break;
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case LIR_ule: cc = LS; fp_cond = false; break;
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case LIR_ugt: cc = HI; fp_cond = false; break;
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case LIR_uge: cc = HS; fp_cond = false; break;
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B_cond(cc, targ);
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asm_output("b(%d) 0x%08x", cc, (unsigned int) targ);
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// Default case for invalid or unexpected LIR instructions.
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default: cc = AL; fp_cond = false; break;
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}
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NIns *at = _nIns;
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// Invert the condition if required.
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if (branchOnFalse)
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cc = OppositeCond(cc);
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// Ensure that we got a sensible condition code.
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NanoAssert((cc != AL) && (cc != NV));
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// Ensure that we don't hit floating-point LIR codes if VFP is disabled.
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NanoAssert(AvmCore::config.vfp || !fp_cond);
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// Emit a suitable branch instruction.
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B_cond(cc, targ);
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// Store the address of the branch instruction so that we can return it.
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// asm_[f]cmp will move _nIns so we must do this now.
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NIns *at = _nIns;
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if (fp_cond)
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asm_fcmp(cond);
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return at;
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}
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else
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asm_cmp(cond);
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// produce the branch
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if (branchOnFalse) {
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if (condop == LIR_eq)
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JNE(targ);
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else if (condop == LIR_ov)
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JNO(targ);
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else if (condop == LIR_cs)
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JNC(targ);
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else if (condop == LIR_lt)
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JNL(targ);
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else if (condop == LIR_le)
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JNLE(targ);
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else if (condop == LIR_gt)
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JNG(targ);
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else if (condop == LIR_ge)
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JNGE(targ);
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else if (condop == LIR_ult)
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JNB(targ);
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else if (condop == LIR_ule)
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JNBE(targ);
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else if (condop == LIR_ugt)
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JNA(targ);
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else //if (condop == LIR_uge)
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JNAE(targ);
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} else // op == LIR_xt
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{
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if (condop == LIR_eq)
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JE(targ);
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else if (condop == LIR_ov)
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JO(targ);
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else if (condop == LIR_cs)
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JC(targ);
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else if (condop == LIR_lt)
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JL(targ);
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else if (condop == LIR_le)
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JLE(targ);
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else if (condop == LIR_gt)
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JG(targ);
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else if (condop == LIR_ge)
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JGE(targ);
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else if (condop == LIR_ult)
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JB(targ);
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else if (condop == LIR_ule)
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JBE(targ);
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else if (condop == LIR_ugt)
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JA(targ);
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else //if (condop == LIR_uge)
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JAE(targ);
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}
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at = _nIns;
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asm_cmp(cond);
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return at;
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}
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@ -121,7 +121,9 @@ typedef enum {
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EQ = 0x0, // Equal
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NE = 0x1, // Not Equal
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CS = 0x2, // Carry Set (or HS)
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HS = 0x2,
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CC = 0x3, // Carry Clear (or LO)
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LO = 0x3,
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MI = 0x4, // MInus
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PL = 0x5, // PLus
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VS = 0x6, // oVerflow Set
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@ -133,10 +135,19 @@ typedef enum {
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GT = 0xC, // Greater Than
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LE = 0xD, // Less or Equal
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AL = 0xE, // ALways
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// Note that condition code NV is unpredictable on ARMv3 and ARMv4, and has
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// special meaning for ARMv5 onwards. As such, it should never be used in
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// an instruction encoding unless the special (ARMv5+) meaning is required.
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NV = 0xF // NeVer
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} ConditionCode;
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#define IsCond(_cc) (((_cc) & 0xf) == (_cc))
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// Bit 0 of the condition code can be flipped to obtain the opposite condition.
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// However, this won't work for AL because its opposite — NV — has special
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// meaning.
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#define OppositeCond(cc) ((ConditionCode)((unsigned int)(cc)^0x1))
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typedef int RegisterMask;
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typedef struct _FragInfo {
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RegisterMask needRestoring;
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