зеркало из https://github.com/mozilla/gecko-dev.git
Bug 1313336 - ARM64 wasmLoad and wasmStore masm instructions. r=jolesen
--HG-- extra : rebase_source : c6d1a2e881027a8ff19af75d78de4ba61bc9f212 extra : source : affa83b4c7892c90cf691cbf60eb3b1427b19a6f
This commit is contained in:
Lars T Hansen
Родитель
5f0fbf8882
Коммит
0e74aff0c4
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@ -1489,23 +1489,23 @@ class MacroAssembler : public MacroAssemblerSpecific
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void wasmStore(const wasm::MemoryAccessDesc& access, AnyRegister value, Operand dstAddr) DEFINED_ON(x86, x64);
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void wasmStoreI64(const wasm::MemoryAccessDesc& access, Register64 value, Operand dstAddr) DEFINED_ON(x86);
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// For all the ARM wasmLoad and wasmStore functions, `ptr` MUST equal
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// `ptrScratch`, and that register will be updated based on conditions
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// For all the ARM and ARM64 wasmLoad and wasmStore functions, `ptr` MUST
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// equal `ptrScratch`, and that register will be updated based on conditions
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// listed below (where it is only mentioned as `ptr`).
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// `ptr` will be updated if access.offset() != 0 or access.type() == Scalar::Int64.
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void wasmLoad(const wasm::MemoryAccessDesc& access, Register memoryBase, Register ptr,
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Register ptrScratch, AnyRegister output)
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DEFINED_ON(arm, mips_shared);
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DEFINED_ON(arm, arm64, mips_shared);
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void wasmLoadI64(const wasm::MemoryAccessDesc& access, Register memoryBase, Register ptr,
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Register ptrScratch, Register64 output)
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DEFINED_ON(arm, mips32, mips64);
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DEFINED_ON(arm, arm64, mips32, mips64);
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void wasmStore(const wasm::MemoryAccessDesc& access, AnyRegister value, Register memoryBase,
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Register ptr, Register ptrScratch)
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DEFINED_ON(arm, mips_shared);
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DEFINED_ON(arm, arm64, mips_shared);
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void wasmStoreI64(const wasm::MemoryAccessDesc& access, Register64 value, Register memoryBase,
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Register ptr, Register ptrScratch)
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DEFINED_ON(arm, mips32, mips64);
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DEFINED_ON(arm, arm64, mips32, mips64);
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// `ptr` will always be updated.
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void wasmUnalignedLoad(const wasm::MemoryAccessDesc& access, Register memoryBase, Register ptr,
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@ -242,6 +242,147 @@ MacroAssemblerCompat::breakpoint()
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Brk((code++) & 0xffff);
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}
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// Either `any` is valid or `sixtyfour` is valid. Return a 32-bit ARMRegister
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// in the first case and an ARMRegister of the desired size in the latter case.
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static inline ARMRegister
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SelectGPReg(AnyRegister any, Register64 sixtyfour, unsigned size = 64)
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{
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MOZ_ASSERT(any.isValid() != (sixtyfour != Register64::Invalid()));
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if (sixtyfour == Register64::Invalid())
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return ARMRegister(any.gpr(), 32);
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return ARMRegister(sixtyfour.reg, size);
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}
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// Assert that `sixtyfour` is invalid and then return an FP register from `any`
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// of the desired size.
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static inline ARMFPRegister
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SelectFPReg(AnyRegister any, Register64 sixtyfour, unsigned size)
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{
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MOZ_ASSERT(sixtyfour == Register64::Invalid());
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return ARMFPRegister(any.fpu(), size);
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}
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void
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MacroAssemblerCompat::wasmLoadImpl(const wasm::MemoryAccessDesc& access, Register memoryBase_,
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Register ptr_, Register ptrScratch_, AnyRegister outany,
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Register64 out64)
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{
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uint32_t offset = access.offset();
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MOZ_ASSERT(offset < wasm::OffsetGuardLimit);
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MOZ_ASSERT(ptr_ == ptrScratch_);
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ARMRegister memoryBase(memoryBase_, 64);
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ARMRegister ptr(ptr_, 64);
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if (offset)
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Add(ptr, ptr, Operand(offset));
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asMasm().memoryBarrierBefore(access.sync());
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MemOperand srcAddr(memoryBase, ptr);
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size_t loadOffset = asMasm().currentOffset();
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switch (access.type()) {
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case Scalar::Int8:
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Ldrsb(SelectGPReg(outany, out64), srcAddr);
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break;
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case Scalar::Uint8:
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Ldrb(SelectGPReg(outany, out64), srcAddr);
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break;
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case Scalar::Int16:
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Ldrsh(SelectGPReg(outany, out64), srcAddr);
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break;
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case Scalar::Uint16:
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Ldrh(SelectGPReg(outany, out64), srcAddr);
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break;
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case Scalar::Int32:
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if (out64 != Register64::Invalid())
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Ldrsw(SelectGPReg(outany, out64), srcAddr);
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else
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Ldr(SelectGPReg(outany, out64, 32), srcAddr);
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break;
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case Scalar::Uint32:
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Ldr(SelectGPReg(outany, out64, 32), srcAddr);
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break;
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case Scalar::Int64:
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Ldr(SelectGPReg(outany, out64), srcAddr);
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break;
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case Scalar::Float32:
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Ldr(SelectFPReg(outany, out64, 32), srcAddr);
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break;
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case Scalar::Float64:
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Ldr(SelectFPReg(outany, out64, 64), srcAddr);
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break;
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case Scalar::Uint8Clamped:
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case Scalar::MaxTypedArrayViewType:
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case Scalar::Float32x4:
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case Scalar::Int32x4:
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case Scalar::Int8x16:
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case Scalar::Int16x8:
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MOZ_CRASH("unexpected array type");
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}
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append(access, loadOffset, framePushed());
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asMasm().memoryBarrierAfter(access.sync());
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}
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void
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MacroAssemblerCompat::wasmStoreImpl(const wasm::MemoryAccessDesc& access, AnyRegister valany,
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Register64 val64, Register memoryBase_, Register ptr_,
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Register ptrScratch_)
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{
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uint32_t offset = access.offset();
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MOZ_ASSERT(offset < wasm::OffsetGuardLimit);
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MOZ_ASSERT(ptr_ == ptrScratch_);
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ARMRegister memoryBase(memoryBase_, 64);
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ARMRegister ptr(ptr_, 64);
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if (offset)
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Add(ptr, ptr, Operand(offset));
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asMasm().memoryBarrierBefore(access.sync());
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MemOperand dstAddr(memoryBase, ptr);
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size_t storeOffset = asMasm().currentOffset();
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switch (access.type()) {
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case Scalar::Int8:
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case Scalar::Uint8:
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Strb(SelectGPReg(valany, val64), dstAddr);
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break;
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case Scalar::Int16:
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case Scalar::Uint16:
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Strh(SelectGPReg(valany, val64), dstAddr);
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break;
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case Scalar::Int32:
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case Scalar::Uint32:
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Str(SelectGPReg(valany, val64), dstAddr);
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break;
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case Scalar::Int64:
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Str(SelectGPReg(valany, val64), dstAddr);
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break;
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case Scalar::Float32:
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Str(SelectFPReg(valany, val64, 32), dstAddr);
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break;
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case Scalar::Float64:
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Str(SelectFPReg(valany, val64, 64), dstAddr);
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break;
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case Scalar::Float32x4:
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case Scalar::Int32x4:
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case Scalar::Int8x16:
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case Scalar::Int16x8:
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case Scalar::Uint8Clamped:
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case Scalar::MaxTypedArrayViewType:
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MOZ_CRASH("unexpected array type");
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}
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append(access, storeOffset, framePushed());
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asMasm().memoryBarrierAfter(access.sync());
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}
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void
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MacroAssembler::reserveStack(uint32_t amount)
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{
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@ -1160,6 +1301,34 @@ MacroAssembler::oolWasmTruncateCheckF64ToI64(FloatRegister input, Register64 out
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wasmTrap(wasm::Trap::IntegerOverflow, off);
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}
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void
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MacroAssembler::wasmLoad(const wasm::MemoryAccessDesc& access, Register memoryBase, Register ptr,
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Register ptrScratch, AnyRegister output)
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{
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wasmLoadImpl(access, memoryBase, ptr, ptrScratch, output, Register64::Invalid());
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}
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void
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MacroAssembler::wasmLoadI64(const wasm::MemoryAccessDesc& access, Register memoryBase, Register ptr,
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Register ptrScratch, Register64 output)
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{
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wasmLoadImpl(access, memoryBase, ptr, ptrScratch, AnyRegister(), output);
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}
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void
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MacroAssembler::wasmStore(const wasm::MemoryAccessDesc& access, AnyRegister value,
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Register memoryBase, Register ptr, Register ptrScratch)
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{
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wasmStoreImpl(access, value, Register64::Invalid(), memoryBase, ptr, ptrScratch);
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}
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void
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MacroAssembler::wasmStoreI64(const wasm::MemoryAccessDesc& access, Register64 value,
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Register memoryBase, Register ptr, Register ptrScratch)
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{
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wasmStoreImpl(access, AnyRegister(), value, memoryBase, ptr, ptrScratch);
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}
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// ========================================================================
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// Convert floating point.
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@ -1926,6 +1926,13 @@ class MacroAssemblerCompat : public vixl::MacroAssembler
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return value;
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}
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void wasmLoadImpl(const wasm::MemoryAccessDesc& access, Register memoryBase,
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Register ptr, Register ptrScratch, AnyRegister outany,
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Register64 out64);
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void wasmStoreImpl(const wasm::MemoryAccessDesc& access, AnyRegister valany,
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Register64 val64, Register memoryBase, Register ptr,
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Register ptrScratch);
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// Emit a BLR or NOP instruction. ToggleCall can be used to patch
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// this instruction.
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CodeOffset toggledCall(JitCode* target, bool enabled) {
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