Fixed edge case in nanojit register allocation for shl/shr (bug 465135, r=gal).

js/src/nanojit/Nativei386.cpp

@@ -1024,18 +1024,7 @@ namespace nanojit
 		RegisterMask allow = GpRegs;
 		bool forceReg = (op == LIR_mul || !rhs->isconst());
 
-#ifdef NANOJIT_ARM
-		// Arm can't do an immediate op with immediates
-		// outside of +/-255 (for AND) r outside of
-		// 0..255 for others.
-		if (!forceReg)
-		{
-			if (rhs->isconst() && !isU8(rhs->constval()))
-				forceReg = true;
-		}
-#endif
-
-		if (lhs != rhs && forceReg)
+		if ((lhs != rhs || (op == LIR_lsh || op == LIR_rsh || op == LIR_ush)) && forceReg)
 		{
 			if ((rb = asm_binop_rhs_reg(ins)) == UnknownReg) {
 				rb = findRegFor(rhs, allow);

js/src/trace-test.js

@@ -1876,6 +1876,14 @@ function testBug465145() {
 	for (var z = 0; z < 2; ++z) { x = y };
 }
 
+function testTrueShiftTrue() {
+    var a = new Array(5);
+    for (var i=0;i<5;++i) a[i] = "" + (true << true);
+    return a.join(",");
+}
+testTrueShiftTrue.expected = "2,2,2,2,2";
+test(testTrueShiftTrue);
+
 // BEGIN MANDELBROT STUFF
 // XXXbz I would dearly like to wrap it up into a function to avoid polluting
 // the global scope, but the function ends up heavyweight, and then we lose on