Bug 1438727: [Part 16] Support shifts in CacheIR r=tcampbell

--HG--
extra : rebase_source : 1d2ec177ccb644debbe9aef7067b94374a2f0900
This commit is contained in:
Matthew Gaudet 2018-05-08 18:32:37 -04:00
Родитель 3356cf50eb
Коммит 19e3a1f44e
6 изменённых файлов: 114 добавлений и 9 удалений

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@ -177,6 +177,9 @@ warmup(funURsh1, [[1,1,0], [5,1,2], [63,31,0], [4294967295,2147483647,1], [-2,10
var funURsh2 = (a, b) => { return a >>> b; }
warmup(funURsh2, [[true,1,0], [5,true,2], [63,false,63], [false, 20, 0]]);
//URsh Int32
var funURsh3 = (a, b) => { return a >>> b; }
warmup(funURsh3, [[4294967295, 0, 4294967295]]);
// Other Test cases that Have been useful:
for (var k=0; k < 30; k++) {

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@ -4959,6 +4959,9 @@ DoCacheIRBinaryArithFallback(JSContext* cx, BaselineFrame* frame, ICBinaryArith_
case JSOP_MUL:
case JSOP_DIV:
case JSOP_MOD:
case JSOP_URSH:
case JSOP_RSH:
case JSOP_LSH:
break;
default:
return false; // Fallback to shared IC.

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@ -5208,15 +5208,7 @@ BinaryArithIRGenerator::tryAttachDouble()
bool
BinaryArithIRGenerator::tryAttachInt32()
{
if (op_ != JSOP_ADD && op_ != JSOP_SUB &&
op_ != JSOP_BITOR && op_ != JSOP_BITAND &&
op_ != JSOP_BITXOR && op_ != JSOP_MUL &&
op_ != JSOP_DIV && op_ != JSOP_MOD)
{
return false;
}
if (!lhs_.isInt32() || !rhs_.isInt32())
if (!lhs_.isInt32() || !rhs_.isInt32() || op_ == JSOP_POW)
return false;
ValOperandId lhsId(writer.setInputOperandId(0));
@ -5258,6 +5250,18 @@ BinaryArithIRGenerator::tryAttachInt32()
writer.int32BitAndResult(lhsIntId, rhsIntId);
trackAttached("BinaryArith.Int32.BitAnd");
break;
case JSOP_LSH:
writer.int32LeftShiftResult(lhsIntId, rhsIntId);
trackAttached("BinaryArith.Int32.LeftShift");
break;
case JSOP_RSH:
writer.int32RightShiftResult(lhsIntId, rhsIntId);
trackAttached("BinaryArith.Int32.RightShift");
break;
case JSOP_URSH:
writer.int32URightShiftResult(lhsIntId, rhsIntId, res_.isDouble());
trackAttached("BinaryArith.Int32.UnsignedRightShift");
break;
default:
MOZ_CRASH("Unhandled op in tryAttachInt32");
}
@ -5316,6 +5320,18 @@ BinaryArithIRGenerator::tryAttachBooleanWithInt32()
writer.int32BitAndResult(lhsIntId, rhsIntId);
trackAttached("BinaryArith.BooleanInt32.BitAnd");
break;
case JSOP_LSH:
writer.int32LeftShiftResult(lhsIntId, rhsIntId);
trackAttached("BinaryArith.BooleanInt32.LeftShift");
break;
case JSOP_RSH:
writer.int32RightShiftResult(lhsIntId, rhsIntId);
trackAttached("BinaryArith.BooleanInt32.RightShift");
break;
case JSOP_URSH:
writer.int32URightShiftResult(lhsIntId, rhsIntId, res_.isDouble());
trackAttached("BinaryArith.BooleanInt32.UnsignedRightShift");
break;
default:
MOZ_CRASH("Unhandled op in tryAttachInt32");
}

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@ -305,6 +305,9 @@ extern const char* CacheKindNames[];
_(Int32BitOrResult) \
_(Int32BitXorResult) \
_(Int32BitAndResult) \
_(Int32LeftShiftResult) \
_(Int32RightShiftResult) \
_(Int32URightShiftResult) \
_(Int32NotResult) \
_(Int32NegationResult) \
_(DoubleNegationResult) \
@ -1063,6 +1066,19 @@ class MOZ_RAII CacheIRWriter : public JS::CustomAutoRooter
writeOpWithOperandId(CacheOp::Int32BitAndResult, lhs);
writeOperandId(rhs);
}
void int32LeftShiftResult(Int32OperandId lhs, Int32OperandId rhs) {
writeOpWithOperandId(CacheOp::Int32LeftShiftResult, lhs);
writeOperandId(rhs);
}
void int32RightShiftResult(Int32OperandId lhs, Int32OperandId rhs) {
writeOpWithOperandId(CacheOp::Int32RightShiftResult, lhs);
writeOperandId(rhs);
}
void int32URightShiftResult(Int32OperandId lhs, Int32OperandId rhs, bool allowDouble) {
writeOpWithOperandId(CacheOp::Int32URightShiftResult, lhs);
writeOperandId(rhs);
buffer_.writeByte(uint32_t(allowDouble));
}
void int32NotResult(Int32OperandId id) {
writeOpWithOperandId(CacheOp::Int32NotResult, id);
}

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@ -2202,8 +2202,72 @@ CacheIRCompiler::emitInt32BitAndResult()
return true;
}
bool
CacheIRCompiler::emitInt32LeftShiftResult()
{
AutoOutputRegister output(*this);
Register lhs = allocator.useRegister(masm, reader.int32OperandId());
Register rhs = allocator.useRegister(masm, reader.int32OperandId());
//Mask shift amount as specified by 12.9.3.1 Step 7
masm.and32(Imm32(0x1F), rhs);
masm.flexibleLshift32(rhs, lhs);
EmitStoreResult(masm, lhs, JSVAL_TYPE_INT32, output);
return true;
}
bool
CacheIRCompiler::emitInt32RightShiftResult()
{
AutoOutputRegister output(*this);
Register lhs = allocator.useRegister(masm, reader.int32OperandId());
Register rhs = allocator.useRegister(masm, reader.int32OperandId());
//Mask shift amount as specified by 12.9.4.1 Step 7
masm.and32(Imm32(0x1F), rhs);
masm.flexibleRshift32Arithmetic(rhs, lhs);
EmitStoreResult(masm, lhs, JSVAL_TYPE_INT32, output);
return true;
}
bool
CacheIRCompiler::emitInt32URightShiftResult()
{
AutoOutputRegister output(*this);
Register lhs = allocator.useRegister(masm, reader.int32OperandId());
Register rhs = allocator.useRegister(masm, reader.int32OperandId());
bool allowDouble = reader.readBool();
FailurePath* failure;
if (!addFailurePath(&failure))
return false;
//Mask shift amount as specified by 12.9.4.1 Step 7
masm.and32(Imm32(0x1F), rhs);
masm.flexibleRshift32(rhs, lhs);
Label intDone,floatDone;
if (allowDouble) {
Label toUint;
masm.branchTest32(Assembler::Signed, lhs, lhs, &toUint);
masm.jump(&intDone);
masm.bind(&toUint);
masm.convertUInt32ToDouble(lhs, ScratchDoubleReg);
masm.boxDouble(ScratchDoubleReg, output.valueReg(), ScratchDoubleReg);
masm.jump(&floatDone);
} else {
masm.branchTest32(Assembler::Signed, lhs, lhs, failure->label());
}
masm.bind(&intDone);
EmitStoreResult(masm, lhs, JSVAL_TYPE_INT32, output);
masm.bind(&floatDone);
return true;
}
bool
CacheIRCompiler::emitInt32NegationResult()
{

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@ -65,6 +65,9 @@ namespace jit {
_(Int32BitOrResult) \
_(Int32BitXorResult) \
_(Int32BitAndResult) \
_(Int32LeftShiftResult) \
_(Int32RightShiftResult) \
_(Int32URightShiftResult) \
_(Int32NegationResult) \
_(Int32NotResult) \
_(DoubleNegationResult) \