From 3e84a842b9ad16ab5295bcdeea4a017348fd2f6d Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Fri, 30 Jan 2015 16:05:56 -0800 Subject: [PATCH] Bug 1125202 - SpiderMonkey: Reorganize the x86 BaseAssembler codebase r=jandem --- js/src/asmjs/AsmJSModule.cpp | 18 +- js/src/asmjs/AsmJSSignalHandlers.cpp | 128 +- js/src/jit/shared/Assembler-x86-shared.cpp | 2 +- js/src/jit/shared/Assembler-x86-shared.h | 84 +- js/src/jit/shared/BaseAssembler-x86-shared.h | 1180 ++++------------- .../jit/shared/CodeGenerator-x86-shared.cpp | 12 +- js/src/jit/shared/Constants-x86-shared.h | 222 ++++ js/src/jit/shared/Encoding-x86-shared.h | 317 +++++ js/src/jit/shared/MacroAssembler-x86-shared.h | 6 +- js/src/jit/shared/Patching-x86-shared.h | 137 ++ js/src/jit/x64/Architecture-x64.h | 86 +- js/src/jit/x64/Assembler-x64.cpp | 22 +- js/src/jit/x64/Assembler-x64.h | 76 +- js/src/jit/x64/MacroAssembler-x64.h | 20 +- js/src/jit/x86/Architecture-x86.h | 54 +- js/src/jit/x86/Assembler-x86.cpp | 4 +- js/src/jit/x86/Assembler-x86.h | 48 +- 17 files changed, 1224 insertions(+), 1192 deletions(-) create mode 100644 js/src/jit/shared/Constants-x86-shared.h create mode 100644 js/src/jit/shared/Encoding-x86-shared.h create mode 100644 js/src/jit/shared/Patching-x86-shared.h diff --git a/js/src/asmjs/AsmJSModule.cpp b/js/src/asmjs/AsmJSModule.cpp index b065064a4c6e..e4d4f5951bbd 100644 --- a/js/src/asmjs/AsmJSModule.cpp +++ b/js/src/asmjs/AsmJSModule.cpp @@ -784,13 +784,13 @@ AsmJSModule::initHeap(Handle heap, JSContext *cx // i.e. ptr >= heapLength + 1 - data-type-byte-size // (Note that we need >= as this is what codegen uses.) size_t scalarByteSize = TypedArrayElemSize(access.type()); - X86Assembler::setPointer(access.patchLengthAt(code_), - (void*)(heap->byteLength() + 1 - scalarByteSize)); + X86Encoding::SetPointer(access.patchLengthAt(code_), + (void*)(heap->byteLength() + 1 - scalarByteSize)); } void *addr = access.patchOffsetAt(code_); - uint32_t disp = reinterpret_cast(X86Assembler::getPointer(addr)); + uint32_t disp = reinterpret_cast(X86Encoding::GetPointer(addr)); MOZ_ASSERT(disp <= INT32_MAX); - X86Assembler::setPointer(addr, (void *)(heapOffset + disp)); + X86Encoding::SetPointer(addr, (void *)(heapOffset + disp)); } #elif defined(JS_CODEGEN_X64) // Even with signal handling being used for most bounds checks, there may be @@ -806,7 +806,7 @@ AsmJSModule::initHeap(Handle heap, JSContext *cx if (access.hasLengthCheck()) { // See comment above for x86 codegen. size_t scalarByteSize = TypedArrayElemSize(access.type()); - X86Assembler::setInt32(access.patchLengthAt(code_), heapLength + 1 - scalarByteSize); + X86Encoding::SetInt32(access.patchLengthAt(code_), heapLength + 1 - scalarByteSize); } } #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_MIPS) @@ -828,9 +828,9 @@ AsmJSModule::restoreHeapToInitialState(ArrayBufferObjectMaybeShared *maybePrevBu for (unsigned i = 0; i < heapAccesses_.length(); i++) { const jit::AsmJSHeapAccess &access = heapAccesses_[i]; void *addr = access.patchOffsetAt(code_); - uint8_t *ptr = reinterpret_cast(X86Assembler::getPointer(addr)); + uint8_t *ptr = reinterpret_cast(X86Encoding::GetPointer(addr)); MOZ_ASSERT(ptr >= ptrBase); - X86Assembler::setPointer(addr, (void *)(ptr - ptrBase)); + X86Encoding::SetPointer(addr, (void *)(ptr - ptrBase)); } } #endif @@ -1678,7 +1678,7 @@ AsmJSModule::setProfilingEnabled(bool enabled, JSContext *cx) uint8_t *callerRetAddr = code_ + cs.returnAddressOffset(); #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64) - void *callee = X86Assembler::getRel32Target(callerRetAddr); + void *callee = X86Encoding::GetRel32Target(callerRetAddr); #elif defined(JS_CODEGEN_ARM) uint8_t *caller = callerRetAddr - 4; Instruction *callerInsn = reinterpret_cast(caller); @@ -1706,7 +1706,7 @@ AsmJSModule::setProfilingEnabled(bool enabled, JSContext *cx) uint8_t *newCallee = enabled ? profilingEntry : entry; #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64) - X86Assembler::setRel32(callerRetAddr, newCallee); + X86Encoding::SetRel32(callerRetAddr, newCallee); #elif defined(JS_CODEGEN_ARM) new (caller) InstBLImm(BOffImm(newCallee - caller), Assembler::Always); #elif defined(JS_CODEGEN_MIPS) diff --git a/js/src/asmjs/AsmJSSignalHandlers.cpp b/js/src/asmjs/AsmJSSignalHandlers.cpp index 68ac55c66a5a..35400435007c 100644 --- a/js/src/asmjs/AsmJSSignalHandlers.cpp +++ b/js/src/asmjs/AsmJSSignalHandlers.cpp @@ -382,42 +382,42 @@ SetRegisterToCoercedUndefined(CONTEXT *context, Scalar::Type viewType, AnyRegist { if (reg.isFloat()) { switch (reg.fpu().code()) { - case X86Registers::xmm0: SetXMMRegToNaN(viewType, &XMM_sig(context, 0)); break; - case X86Registers::xmm1: SetXMMRegToNaN(viewType, &XMM_sig(context, 1)); break; - case X86Registers::xmm2: SetXMMRegToNaN(viewType, &XMM_sig(context, 2)); break; - case X86Registers::xmm3: SetXMMRegToNaN(viewType, &XMM_sig(context, 3)); break; - case X86Registers::xmm4: SetXMMRegToNaN(viewType, &XMM_sig(context, 4)); break; - case X86Registers::xmm5: SetXMMRegToNaN(viewType, &XMM_sig(context, 5)); break; - case X86Registers::xmm6: SetXMMRegToNaN(viewType, &XMM_sig(context, 6)); break; - case X86Registers::xmm7: SetXMMRegToNaN(viewType, &XMM_sig(context, 7)); break; - case X86Registers::xmm8: SetXMMRegToNaN(viewType, &XMM_sig(context, 8)); break; - case X86Registers::xmm9: SetXMMRegToNaN(viewType, &XMM_sig(context, 9)); break; - case X86Registers::xmm10: SetXMMRegToNaN(viewType, &XMM_sig(context, 10)); break; - case X86Registers::xmm11: SetXMMRegToNaN(viewType, &XMM_sig(context, 11)); break; - case X86Registers::xmm12: SetXMMRegToNaN(viewType, &XMM_sig(context, 12)); break; - case X86Registers::xmm13: SetXMMRegToNaN(viewType, &XMM_sig(context, 13)); break; - case X86Registers::xmm14: SetXMMRegToNaN(viewType, &XMM_sig(context, 14)); break; - case X86Registers::xmm15: SetXMMRegToNaN(viewType, &XMM_sig(context, 15)); break; + case X86Encoding::xmm0: SetXMMRegToNaN(viewType, &XMM_sig(context, 0)); break; + case X86Encoding::xmm1: SetXMMRegToNaN(viewType, &XMM_sig(context, 1)); break; + case X86Encoding::xmm2: SetXMMRegToNaN(viewType, &XMM_sig(context, 2)); break; + case X86Encoding::xmm3: SetXMMRegToNaN(viewType, &XMM_sig(context, 3)); break; + case X86Encoding::xmm4: SetXMMRegToNaN(viewType, &XMM_sig(context, 4)); break; + case X86Encoding::xmm5: SetXMMRegToNaN(viewType, &XMM_sig(context, 5)); break; + case X86Encoding::xmm6: SetXMMRegToNaN(viewType, &XMM_sig(context, 6)); break; + case X86Encoding::xmm7: SetXMMRegToNaN(viewType, &XMM_sig(context, 7)); break; + case X86Encoding::xmm8: SetXMMRegToNaN(viewType, &XMM_sig(context, 8)); break; + case X86Encoding::xmm9: SetXMMRegToNaN(viewType, &XMM_sig(context, 9)); break; + case X86Encoding::xmm10: SetXMMRegToNaN(viewType, &XMM_sig(context, 10)); break; + case X86Encoding::xmm11: SetXMMRegToNaN(viewType, &XMM_sig(context, 11)); break; + case X86Encoding::xmm12: SetXMMRegToNaN(viewType, &XMM_sig(context, 12)); break; + case X86Encoding::xmm13: SetXMMRegToNaN(viewType, &XMM_sig(context, 13)); break; + case X86Encoding::xmm14: SetXMMRegToNaN(viewType, &XMM_sig(context, 14)); break; + case X86Encoding::xmm15: SetXMMRegToNaN(viewType, &XMM_sig(context, 15)); break; default: MOZ_CRASH(); } } else { switch (reg.gpr().code()) { - case X86Registers::eax: RAX_sig(context) = 0; break; - case X86Registers::ecx: RCX_sig(context) = 0; break; - case X86Registers::edx: RDX_sig(context) = 0; break; - case X86Registers::ebx: RBX_sig(context) = 0; break; - case X86Registers::esp: RSP_sig(context) = 0; break; - case X86Registers::ebp: RBP_sig(context) = 0; break; - case X86Registers::esi: RSI_sig(context) = 0; break; - case X86Registers::edi: RDI_sig(context) = 0; break; - case X86Registers::r8: R8_sig(context) = 0; break; - case X86Registers::r9: R9_sig(context) = 0; break; - case X86Registers::r10: R10_sig(context) = 0; break; - case X86Registers::r11: R11_sig(context) = 0; break; - case X86Registers::r12: R12_sig(context) = 0; break; - case X86Registers::r13: R13_sig(context) = 0; break; - case X86Registers::r14: R14_sig(context) = 0; break; - case X86Registers::r15: R15_sig(context) = 0; break; + case X86Encoding::rax: RAX_sig(context) = 0; break; + case X86Encoding::rcx: RCX_sig(context) = 0; break; + case X86Encoding::rdx: RDX_sig(context) = 0; break; + case X86Encoding::rbx: RBX_sig(context) = 0; break; + case X86Encoding::rsp: RSP_sig(context) = 0; break; + case X86Encoding::rbp: RBP_sig(context) = 0; break; + case X86Encoding::rsi: RSI_sig(context) = 0; break; + case X86Encoding::rdi: RDI_sig(context) = 0; break; + case X86Encoding::r8: R8_sig(context) = 0; break; + case X86Encoding::r9: R9_sig(context) = 0; break; + case X86Encoding::r10: R10_sig(context) = 0; break; + case X86Encoding::r11: R11_sig(context) = 0; break; + case X86Encoding::r12: R12_sig(context) = 0; break; + case X86Encoding::r13: R13_sig(context) = 0; break; + case X86Encoding::r14: R14_sig(context) = 0; break; + case X86Encoding::r15: R15_sig(context) = 0; break; default: MOZ_CRASH(); } } @@ -551,22 +551,22 @@ SetRegisterToCoercedUndefined(mach_port_t rtThread, x86_thread_state64_t &state, Scalar::Type viewType = heapAccess.type(); switch (heapAccess.loadedReg().fpu().code()) { - case X86Registers::xmm0: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm0); break; - case X86Registers::xmm1: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm1); break; - case X86Registers::xmm2: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm2); break; - case X86Registers::xmm3: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm3); break; - case X86Registers::xmm4: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm4); break; - case X86Registers::xmm5: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm5); break; - case X86Registers::xmm6: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm6); break; - case X86Registers::xmm7: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm7); break; - case X86Registers::xmm8: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm8); break; - case X86Registers::xmm9: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm9); break; - case X86Registers::xmm10: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm10); break; - case X86Registers::xmm11: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm11); break; - case X86Registers::xmm12: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm12); break; - case X86Registers::xmm13: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm13); break; - case X86Registers::xmm14: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm14); break; - case X86Registers::xmm15: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm15); break; + case X86Encoding::xmm0: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm0); break; + case X86Encoding::xmm1: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm1); break; + case X86Encoding::xmm2: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm2); break; + case X86Encoding::xmm3: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm3); break; + case X86Encoding::xmm4: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm4); break; + case X86Encoding::xmm5: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm5); break; + case X86Encoding::xmm6: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm6); break; + case X86Encoding::xmm7: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm7); break; + case X86Encoding::xmm8: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm8); break; + case X86Encoding::xmm9: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm9); break; + case X86Encoding::xmm10: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm10); break; + case X86Encoding::xmm11: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm11); break; + case X86Encoding::xmm12: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm12); break; + case X86Encoding::xmm13: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm13); break; + case X86Encoding::xmm14: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm14); break; + case X86Encoding::xmm15: SetXMMRegToNaN(viewType, &fstate.__fpu_xmm15); break; default: MOZ_CRASH(); } @@ -575,22 +575,22 @@ SetRegisterToCoercedUndefined(mach_port_t rtThread, x86_thread_state64_t &state, return false; } else { switch (heapAccess.loadedReg().gpr().code()) { - case X86Registers::eax: state.__rax = 0; break; - case X86Registers::ecx: state.__rcx = 0; break; - case X86Registers::edx: state.__rdx = 0; break; - case X86Registers::ebx: state.__rbx = 0; break; - case X86Registers::esp: state.__rsp = 0; break; - case X86Registers::ebp: state.__rbp = 0; break; - case X86Registers::esi: state.__rsi = 0; break; - case X86Registers::edi: state.__rdi = 0; break; - case X86Registers::r8: state.__r8 = 0; break; - case X86Registers::r9: state.__r9 = 0; break; - case X86Registers::r10: state.__r10 = 0; break; - case X86Registers::r11: state.__r11 = 0; break; - case X86Registers::r12: state.__r12 = 0; break; - case X86Registers::r13: state.__r13 = 0; break; - case X86Registers::r14: state.__r14 = 0; break; - case X86Registers::r15: state.__r15 = 0; break; + case X86Encoding::rax: state.__rax = 0; break; + case X86Encoding::rcx: state.__rcx = 0; break; + case X86Encoding::rdx: state.__rdx = 0; break; + case X86Encoding::rbx: state.__rbx = 0; break; + case X86Encoding::rsp: state.__rsp = 0; break; + case X86Encoding::rbp: state.__rbp = 0; break; + case X86Encoding::rsi: state.__rsi = 0; break; + case X86Encoding::rdi: state.__rdi = 0; break; + case X86Encoding::r8: state.__r8 = 0; break; + case X86Encoding::r9: state.__r9 = 0; break; + case X86Encoding::r10: state.__r10 = 0; break; + case X86Encoding::r11: state.__r11 = 0; break; + case X86Encoding::r12: state.__r12 = 0; break; + case X86Encoding::r13: state.__r13 = 0; break; + case X86Encoding::r14: state.__r14 = 0; break; + case X86Encoding::r15: state.__r15 = 0; break; default: MOZ_CRASH(); } } diff --git a/js/src/jit/shared/Assembler-x86-shared.cpp b/js/src/jit/shared/Assembler-x86-shared.cpp index 9908ed1084c6..71c6ca5cd050 100644 --- a/js/src/jit/shared/Assembler-x86-shared.cpp +++ b/js/src/jit/shared/Assembler-x86-shared.cpp @@ -50,7 +50,7 @@ TraceDataRelocations(JSTracer *trc, uint8_t *buffer, CompactBufferReader &reader { while (reader.more()) { size_t offset = reader.readUnsigned(); - void **ptr = X86Assembler::getPointerRef(buffer + offset); + void **ptr = X86Encoding::GetPointerRef(buffer + offset); #ifdef JS_PUNBOX64 // All pointers on x64 will have the top bits cleared. If those bits diff --git a/js/src/jit/shared/Assembler-x86-shared.h b/js/src/jit/shared/Assembler-x86-shared.h index a851a21735c2..b150b5e800b6 100644 --- a/js/src/jit/shared/Assembler-x86-shared.h +++ b/js/src/jit/shared/Assembler-x86-shared.h @@ -68,7 +68,7 @@ class Operand { } explicit Operand(AbsoluteAddress address) : kind_(MEM_ADDRESS32), - disp_(X86Assembler::addressImmediate(address.addr)) + disp_(X86Encoding::AddressImmediate(address.addr)) { } Address toAddress() const { @@ -216,10 +216,10 @@ class AssemblerX86Shared : public AssemblerShared } protected: - X86Assembler masm; + X86Encoding::BaseAssembler masm; - typedef X86Assembler::JmpSrc JmpSrc; - typedef X86Assembler::JmpDst JmpDst; + typedef X86Encoding::JmpSrc JmpSrc; + typedef X86Encoding::JmpDst JmpDst; public: AssemblerX86Shared() @@ -229,23 +229,23 @@ class AssemblerX86Shared : public AssemblerShared } enum Condition { - Equal = X86Assembler::ConditionE, - NotEqual = X86Assembler::ConditionNE, - Above = X86Assembler::ConditionA, - AboveOrEqual = X86Assembler::ConditionAE, - Below = X86Assembler::ConditionB, - BelowOrEqual = X86Assembler::ConditionBE, - GreaterThan = X86Assembler::ConditionG, - GreaterThanOrEqual = X86Assembler::ConditionGE, - LessThan = X86Assembler::ConditionL, - LessThanOrEqual = X86Assembler::ConditionLE, - Overflow = X86Assembler::ConditionO, - Signed = X86Assembler::ConditionS, - NotSigned = X86Assembler::ConditionNS, - Zero = X86Assembler::ConditionE, - NonZero = X86Assembler::ConditionNE, - Parity = X86Assembler::ConditionP, - NoParity = X86Assembler::ConditionNP + Equal = X86Encoding::ConditionE, + NotEqual = X86Encoding::ConditionNE, + Above = X86Encoding::ConditionA, + AboveOrEqual = X86Encoding::ConditionAE, + Below = X86Encoding::ConditionB, + BelowOrEqual = X86Encoding::ConditionBE, + GreaterThan = X86Encoding::ConditionG, + GreaterThanOrEqual = X86Encoding::ConditionGE, + LessThan = X86Encoding::ConditionL, + LessThanOrEqual = X86Encoding::ConditionLE, + Overflow = X86Encoding::ConditionO, + Signed = X86Encoding::ConditionS, + NotSigned = X86Encoding::ConditionNS, + Zero = X86Encoding::ConditionE, + NonZero = X86Encoding::ConditionNE, + Parity = X86Encoding::ConditionP, + NoParity = X86Encoding::ConditionNP }; // If this bit is set, the vucomisd operands have to be inverted. @@ -788,10 +788,10 @@ class AssemblerX86Shared : public AssemblerShared void jSrc(Condition cond, Label *label) { if (label->bound()) { // The jump can be immediately encoded to the correct destination. - masm.jCC_i(static_cast(cond), JmpDst(label->offset())); + masm.jCC_i(static_cast(cond), JmpDst(label->offset())); } else { // Thread the jump list through the unpatched jump targets. - JmpSrc j = masm.jCC(static_cast(cond)); + JmpSrc j = masm.jCC(static_cast(cond)); JmpSrc prev = JmpSrc(label->use(j.offset())); masm.setNextJump(j, prev); } @@ -823,7 +823,7 @@ class AssemblerX86Shared : public AssemblerShared } JmpSrc jSrc(Condition cond, RepatchLabel *label) { - JmpSrc j = masm.jCC(static_cast(cond)); + JmpSrc j = masm.jCC(static_cast(cond)); if (label->bound()) { // The jump can be immediately patched to the correct destination. masm.linkJump(j, JmpDst(label->offset())); @@ -869,12 +869,12 @@ class AssemblerX86Shared : public AssemblerShared } void cmpEAX(Label *label) { cmpSrc(label); } void bind(Label *label) { - X86Assembler::JmpDst dst(masm.label()); + JmpDst dst(masm.label()); if (label->used()) { bool more; - X86Assembler::JmpSrc jmp(label->offset()); + JmpSrc jmp(label->offset()); do { - X86Assembler::JmpSrc next; + JmpSrc next; more = masm.nextJump(jmp, &next); masm.linkJump(jmp, dst); jmp = next; @@ -883,9 +883,9 @@ class AssemblerX86Shared : public AssemblerShared label->bind(dst.offset()); } void bind(RepatchLabel *label) { - X86Assembler::JmpDst dst(masm.label()); + JmpDst dst(masm.label()); if (label->used()) { - X86Assembler::JmpSrc jmp(label->offset()); + JmpSrc jmp(label->offset()); masm.linkJump(jmp, dst); } label->bind(dst.offset()); @@ -898,9 +898,9 @@ class AssemblerX86Shared : public AssemblerShared void retarget(Label *label, Label *target) { if (label->used()) { bool more; - X86Assembler::JmpSrc jmp(label->offset()); + JmpSrc jmp(label->offset()); do { - X86Assembler::JmpSrc next; + JmpSrc next; more = masm.nextJump(jmp, &next); if (target->bound()) { @@ -922,15 +922,15 @@ class AssemblerX86Shared : public AssemblerShared if (label->used()) { intptr_t src = label->offset(); do { - intptr_t next = reinterpret_cast(X86Assembler::getPointer(raw + src)); - X86Assembler::setPointer(raw + src, address); + intptr_t next = reinterpret_cast(X86Encoding::GetPointer(raw + src)); + X86Encoding::SetPointer(raw + src, address); src = next; } while (src != AbsoluteLabel::INVALID_OFFSET); } label->bind(); } - // See Bind and X86Assembler::setPointer. + // See Bind and X86Encoding::setPointer. size_t labelOffsetToPatchOffset(size_t offset) { return offset - sizeof(void*); } @@ -1040,7 +1040,7 @@ class AssemblerX86Shared : public AssemblerShared masm.cmpw_rr(rhs.code(), lhs.code()); } void setCC(Condition cond, Register r) { - masm.setCC_r(static_cast(cond), r.code()); + masm.setCC_r(static_cast(cond), r.code()); } void testb(Register rhs, Register lhs) { MOZ_ASSERT(GeneralRegisterSet(Registers::SingleByteRegs).has(rhs)); @@ -1694,19 +1694,19 @@ class AssemblerX86Shared : public AssemblerShared } } void vcmpeqps(const Operand &src1, FloatRegister src0, FloatRegister dest) { - vcmpps(X86Assembler::ConditionCmp_EQ, src1, src0, dest); + vcmpps(X86Encoding::ConditionCmp_EQ, src1, src0, dest); } void vcmpltps(const Operand &src1, FloatRegister src0, FloatRegister dest) { - vcmpps(X86Assembler::ConditionCmp_LT, src1, src0, dest); + vcmpps(X86Encoding::ConditionCmp_LT, src1, src0, dest); } void vcmpleps(const Operand &src1, FloatRegister src0, FloatRegister dest) { - vcmpps(X86Assembler::ConditionCmp_LE, src1, src0, dest); + vcmpps(X86Encoding::ConditionCmp_LE, src1, src0, dest); } void vcmpunordps(const Operand &src1, FloatRegister src0, FloatRegister dest) { - vcmpps(X86Assembler::ConditionCmp_UNORD, src1, src0, dest); + vcmpps(X86Encoding::ConditionCmp_UNORD, src1, src0, dest); } void vcmpneqps(const Operand &src1, FloatRegister src0, FloatRegister dest) { - vcmpps(X86Assembler::ConditionCmp_NEQ, src1, src0, dest); + vcmpps(X86Encoding::ConditionCmp_NEQ, src1, src0, dest); } void vrcpps(const Operand &src, FloatRegister dest) { MOZ_ASSERT(HasSSE2()); @@ -2333,11 +2333,11 @@ class AssemblerX86Shared : public AssemblerShared MOZ_ASSERT(HasSSE2()); masm.vsqrtss_rr(src1.code(), src0.code(), dest.code()); } - void vroundsd(X86Assembler::RoundingMode mode, FloatRegister src1, FloatRegister src0, FloatRegister dest) { + void vroundsd(X86Encoding::RoundingMode mode, FloatRegister src1, FloatRegister src0, FloatRegister dest) { MOZ_ASSERT(HasSSE41()); masm.vroundsd_irr(mode, src1.code(), src0.code(), dest.code()); } - void vroundss(X86Assembler::RoundingMode mode, FloatRegister src1, FloatRegister src0, FloatRegister dest) { + void vroundss(X86Encoding::RoundingMode mode, FloatRegister src1, FloatRegister src0, FloatRegister dest) { MOZ_ASSERT(HasSSE41()); masm.vroundss_irr(mode, src1.code(), src0.code(), dest.code()); } diff --git a/js/src/jit/shared/BaseAssembler-x86-shared.h b/js/src/jit/shared/BaseAssembler-x86-shared.h index 4be3804e4501..2bcd89ca293a 100644 --- a/js/src/jit/shared/BaseAssembler-x86-shared.h +++ b/js/src/jit/shared/BaseAssembler-x86-shared.h @@ -32,594 +32,23 @@ #include "mozilla/IntegerPrintfMacros.h" -#include - #include "jit/shared/AssemblerBuffer-x86-shared.h" - -#include "js/Vector.h" +#include "jit/shared/Encoding-x86-shared.h" +#include "jit/shared/Patching-x86-shared.h" namespace js { namespace jit { -inline bool CAN_SIGN_EXTEND_8_32(int32_t value) { return value == (int32_t)(int8_t)value; } -inline bool CAN_SIGN_EXTEND_16_32(int32_t value) { return value == (int32_t)(int16_t)value; } -inline bool CAN_ZERO_EXTEND_8_32(int32_t value) { return value == (int32_t)(uint8_t)value; } -inline bool CAN_ZERO_EXTEND_8H_32(int32_t value) { return value == (value & 0xff00); } -inline bool CAN_ZERO_EXTEND_16_32(int32_t value) { return value == (int32_t)(uint16_t)value; } -inline bool CAN_ZERO_EXTEND_32_64(int32_t value) { return value >= 0; } +namespace X86Encoding { -namespace X86Registers { - enum RegisterID { - eax, - ecx, - edx, - ebx, - esp, - ebp, - esi, - edi - -#ifdef JS_CODEGEN_X64 - ,r8, - r9, - r10, - r11, - r12, - r13, - r14, - r15 -#endif - ,invalid_reg - }; - - enum XMMRegisterID { - xmm0, - xmm1, - xmm2, - xmm3, - xmm4, - xmm5, - xmm6, - xmm7 -#ifdef JS_CODEGEN_X64 - ,xmm8, - xmm9, - xmm10, - xmm11, - xmm12, - xmm13, - xmm14, - xmm15 -#endif - ,invalid_xmm - }; - - static const char *XMMRegName(XMMRegisterID fpreg) - { - static const char *const names[] = { - "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7" -#ifdef JS_CODEGEN_X64 - , "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15" -#endif - }; - int off = fpreg - xmm0; - MOZ_ASSERT(off >= 0 && size_t(off) < mozilla::ArrayLength(names)); - return names[off]; - } - -#ifdef JS_CODEGEN_X64 - static const char *GPReg64Name(RegisterID reg) - { - static const char *const names[] = { - "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", - "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" - }; - int off = reg - eax; - MOZ_ASSERT(off >= 0 && size_t(off) < mozilla::ArrayLength(names)); - return names[off]; - } -#endif - - static const char *GPReg32Name(RegisterID reg) - { - static const char *const names[] = { - "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi" -#ifdef JS_CODEGEN_X64 - , "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" -#endif - }; - int off = reg - eax; - MOZ_ASSERT(off >= 0 && size_t(off) < mozilla::ArrayLength(names)); - return names[off]; - } - - static const char *GPReg16Name(RegisterID reg) - { - static const char *const names[] = { - "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di" -#ifdef JS_CODEGEN_X64 - , "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" -#endif - }; - int off = reg - eax; - MOZ_ASSERT(off >= 0 && size_t(off) < mozilla::ArrayLength(names)); - return names[off]; - } - - static const char *GPReg8Name(RegisterID reg) - { - // For %spl through %dil, assume we'll have a REX prefix. - static const char *const names[] = { - "%al", "%cl", "%dl", "%bl" -#ifdef JS_CODEGEN_X64 - , "%spl", "%bpl", "%sil", "%dil", - "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" -#endif - }; - int off = reg - eax; - MOZ_ASSERT(off >= 0 && size_t(off) < mozilla::ArrayLength(names)); - return names[off]; - } - - // Like GPReg8Name, but emits non-REX names, when appropriate - static const char *GPReg8Name_norex(RegisterID reg) - { - // The same as names above, except that %spl through %dil are replaced - // by %ah through %bh since there is to be no REX prefix. - static const char *const names[] = { - "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh" -#ifdef JS_CODEGEN_X64 - , "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" -#endif - }; - int off = reg - eax; - MOZ_ASSERT(off >= 0 && size_t(off) < mozilla::ArrayLength(names)); - return names[off]; - } - - static const char *GPRegName(RegisterID reg) - { -#ifdef JS_CODEGEN_X64 - return GPReg64Name(reg); -#else - return GPReg32Name(reg); -#endif - } - - inline bool hasSubregL(RegisterID reg) - { -#ifdef JS_CODEGEN_X64 - // In 64-bit mode, all registers have an 8-bit lo subreg. - return true; -#else - // In 32-bit mode, only the first four registers do. - return reg <= ebx; -#endif - } - - inline bool hasSubregH(RegisterID reg) - { - // The first four registers always have h registers. However, note that - // on x64, h registers may not be used in instructions using REX - // prefixes. Also note that this may depend on what other registers are - // used! - return reg <= ebx; - } - - inline RegisterID getSubregH(RegisterID reg) - { - MOZ_ASSERT(hasSubregH(reg)); - return RegisterID(reg + 4); - } - - // Byte operand register spl & above require a REX prefix (to prevent - // the 'H' registers be accessed). - inline bool ByteRegRequiresRex(RegisterID reg) - { - return reg >= esp; - } -} /* namespace X86Registers */ - -class X86Assembler : public GenericAssembler { +class BaseAssembler : public GenericAssembler { public: - typedef X86Registers::RegisterID RegisterID; - typedef X86Registers::XMMRegisterID XMMRegisterID; - typedef XMMRegisterID FPRegisterID; - - enum Condition { - ConditionO, - ConditionNO, - ConditionB, - ConditionAE, - ConditionE, - ConditionNE, - ConditionBE, - ConditionA, - ConditionS, - ConditionNS, - ConditionP, - ConditionNP, - ConditionL, - ConditionGE, - ConditionLE, - ConditionG, - - ConditionC = ConditionB, - ConditionNC = ConditionAE - }; - - // Conditions for CMP instructions (CMPSS, CMPSD, CMPPS, CMPPD, etc). - enum ConditionCmp { - ConditionCmp_EQ = 0x0, - ConditionCmp_LT = 0x1, - ConditionCmp_LE = 0x2, - ConditionCmp_UNORD = 0x3, - ConditionCmp_NEQ = 0x4, - ConditionCmp_NLT = 0x5, - ConditionCmp_NLE = 0x6, - ConditionCmp_ORD = 0x7, - }; - - static const char* nameCC(Condition cc) - { - static const char* const names[16] - = { "o ", "no", "b ", "ae", "e ", "ne", "be", "a ", - "s ", "ns", "p ", "np", "l ", "ge", "le", "g " }; - int ix = (int)cc; - MOZ_ASSERT(ix >= 0 && size_t(ix) < mozilla::ArrayLength(names)); - return names[ix]; - } - - // Rounding modes for ROUNDSD. - enum RoundingMode { - RoundToNearest = 0x0, - RoundDown = 0x1, - RoundUp = 0x2, - RoundToZero = 0x3 - }; - -private: - enum OneByteOpcodeID { - OP_ADD_EbGb = 0x00, - OP_ADD_EvGv = 0x01, - OP_ADD_GvEv = 0x03, - OP_ADD_EAXIv = 0x05, - OP_OR_EbGb = 0x08, - OP_OR_EvGv = 0x09, - OP_OR_GvEv = 0x0B, - OP_OR_EAXIv = 0x0D, - OP_2BYTE_ESCAPE = 0x0F, - OP_AND_EbGb = 0x20, - OP_AND_EvGv = 0x21, - OP_AND_GvEv = 0x23, - OP_AND_EAXIv = 0x25, - OP_SUB_EbGb = 0x28, - OP_SUB_EvGv = 0x29, - OP_SUB_GvEv = 0x2B, - OP_SUB_EAXIv = 0x2D, - OP_XOR_EbGb = 0x30, - OP_XOR_EvGv = 0x31, - OP_XOR_GvEv = 0x33, - OP_XOR_EAXIv = 0x35, - OP_CMP_EvGv = 0x39, - OP_CMP_GvEv = 0x3B, - OP_CMP_EAXIv = 0x3D, -#ifdef JS_CODEGEN_X64 - PRE_REX = 0x40, -#endif - OP_PUSH_EAX = 0x50, - OP_POP_EAX = 0x58, -#ifdef JS_CODEGEN_X86 - OP_PUSHA = 0x60, - OP_POPA = 0x61, -#endif -#ifdef JS_CODEGEN_X64 - OP_MOVSXD_GvEv = 0x63, -#endif - PRE_OPERAND_SIZE = 0x66, - PRE_SSE_66 = 0x66, - OP_PUSH_Iz = 0x68, - OP_IMUL_GvEvIz = 0x69, - OP_PUSH_Ib = 0x6a, - OP_IMUL_GvEvIb = 0x6b, - OP_JCC_rel8 = 0x70, - OP_GROUP1_EbIb = 0x80, - OP_GROUP1_EvIz = 0x81, - OP_GROUP1_EvIb = 0x83, - OP_TEST_EbGb = 0x84, - OP_TEST_EvGv = 0x85, - OP_XCHG_GvEv = 0x87, - OP_MOV_EbGv = 0x88, - OP_MOV_EvGv = 0x89, - OP_MOV_GvEb = 0x8A, - OP_MOV_GvEv = 0x8B, - OP_LEA = 0x8D, - OP_GROUP1A_Ev = 0x8F, - OP_NOP = 0x90, - OP_PUSHFLAGS = 0x9C, - OP_POPFLAGS = 0x9D, - OP_CDQ = 0x99, - OP_MOV_EAXOv = 0xA1, - OP_MOV_OvEAX = 0xA3, - OP_TEST_EAXIb = 0xA8, - OP_TEST_EAXIv = 0xA9, - OP_MOV_EAXIv = 0xB8, - OP_GROUP2_EvIb = 0xC1, - OP_RET_Iz = 0xC2, - PRE_VEX_C4 = 0xC4, - PRE_VEX_C5 = 0xC5, - OP_RET = 0xC3, - OP_GROUP11_EvIb = 0xC6, - OP_GROUP11_EvIz = 0xC7, - OP_INT3 = 0xCC, - OP_GROUP2_Ev1 = 0xD1, - OP_GROUP2_EvCL = 0xD3, - OP_FPU6 = 0xDD, - OP_FPU6_F32 = 0xD9, - OP_CALL_rel32 = 0xE8, - OP_JMP_rel32 = 0xE9, - OP_JMP_rel8 = 0xEB, - PRE_LOCK = 0xF0, - PRE_SSE_F2 = 0xF2, - PRE_SSE_F3 = 0xF3, - OP_HLT = 0xF4, - OP_GROUP3_EbIb = 0xF6, - OP_GROUP3_Ev = 0xF7, - OP_GROUP3_EvIz = 0xF7, // OP_GROUP3_Ev has an immediate, when instruction is a test. - OP_GROUP5_Ev = 0xFF - }; - - enum ShiftID { - Shift_vpsrld = 2, - Shift_vpsrlq = 2, - Shift_vpsrldq = 3, - Shift_vpsrad = 4, - Shift_vpslld = 6, - Shift_vpsllq = 6 - }; - - enum TwoByteOpcodeID { - OP2_UD2 = 0x0B, - OP2_MOVSD_VsdWsd = 0x10, - OP2_MOVPS_VpsWps = 0x10, - OP2_MOVSD_WsdVsd = 0x11, - OP2_MOVPS_WpsVps = 0x11, - OP2_MOVHLPS_VqUq = 0x12, - OP2_MOVSLDUP_VpsWps = 0x12, - OP2_UNPCKLPS_VsdWsd = 0x14, - OP2_UNPCKHPS_VsdWsd = 0x15, - OP2_MOVLHPS_VqUq = 0x16, - OP2_MOVSHDUP_VpsWps = 0x16, - OP2_MOVAPD_VsdWsd = 0x28, - OP2_MOVAPS_VsdWsd = 0x28, - OP2_MOVAPS_WsdVsd = 0x29, - OP2_CVTSI2SD_VsdEd = 0x2A, - OP2_CVTTSD2SI_GdWsd = 0x2C, - OP2_UCOMISD_VsdWsd = 0x2E, - OP2_MOVMSKPD_EdVd = 0x50, - OP2_ANDPS_VpsWps = 0x54, - OP2_ANDNPS_VpsWps = 0x55, - OP2_ORPS_VpsWps = 0x56, - OP2_XORPS_VpsWps = 0x57, - OP2_ADDSD_VsdWsd = 0x58, - OP2_ADDPS_VpsWps = 0x58, - OP2_MULSD_VsdWsd = 0x59, - OP2_MULPS_VpsWps = 0x59, - OP2_CVTSS2SD_VsdEd = 0x5A, - OP2_CVTSD2SS_VsdEd = 0x5A, - OP2_CVTTPS2DQ_VdqWps = 0x5B, - OP2_CVTDQ2PS_VpsWdq = 0x5B, - OP2_SUBSD_VsdWsd = 0x5C, - OP2_SUBPS_VpsWps = 0x5C, - OP2_MINSD_VsdWsd = 0x5D, - OP2_MINSS_VssWss = 0x5D, - OP2_MINPS_VpsWps = 0x5D, - OP2_DIVSD_VsdWsd = 0x5E, - OP2_DIVPS_VpsWps = 0x5E, - OP2_MAXSD_VsdWsd = 0x5F, - OP2_MAXSS_VssWss = 0x5F, - OP2_MAXPS_VpsWps = 0x5F, - OP2_SQRTSD_VsdWsd = 0x51, - OP2_SQRTSS_VssWss = 0x51, - OP2_SQRTPS_VpsWps = 0x51, - OP2_RSQRTPS_VpsWps = 0x52, - OP2_RCPPS_VpsWps = 0x53, - OP2_ANDPD_VpdWpd = 0x54, - OP2_ORPD_VpdWpd = 0x56, - OP2_XORPD_VpdWpd = 0x57, - OP2_PCMPGTD_VdqWdq = 0x66, - OP2_MOVD_VdEd = 0x6E, - OP2_MOVDQ_VsdWsd = 0x6F, - OP2_MOVDQ_VdqWdq = 0x6F, - OP2_PSHUFD_VdqWdqIb = 0x70, - OP2_PSLLD_UdqIb = 0x72, - OP2_PSRAD_UdqIb = 0x72, - OP2_PSRLD_UdqIb = 0x72, - OP2_PSRLDQ_Vd = 0x73, - OP2_PCMPEQW = 0x75, - OP2_PCMPEQD_VdqWdq = 0x76, - OP2_MOVD_EdVd = 0x7E, - OP2_MOVDQ_WdqVdq = 0x7F, - OP2_JCC_rel32 = 0x80, - OP_SETCC = 0x90, - OP_FENCE = 0xAE, - OP2_IMUL_GvEv = 0xAF, - OP2_CMPXCHG_GvEb = 0xB0, - OP2_CMPXCHG_GvEw = 0xB1, - OP2_BSR_GvEv = 0xBD, - OP2_MOVSX_GvEb = 0xBE, - OP2_MOVSX_GvEw = 0xBF, - OP2_MOVZX_GvEb = 0xB6, - OP2_MOVZX_GvEw = 0xB7, - OP2_XADD_EbGb = 0xC0, - OP2_XADD_EvGv = 0xC1, - OP2_CMPPS_VpsWps = 0xC2, - OP2_PEXTRW_GdUdIb = 0xC5, - OP2_SHUFPS_VpsWpsIb = 0xC6, - OP2_PSRLD_VdqWdq = 0xD2, - OP2_PANDDQ_VdqWdq = 0xDB, - OP2_PANDNDQ_VdqWdq = 0xDF, - OP2_PSRAD_VdqWdq = 0xE2, - OP2_PORDQ_VdqWdq = 0xEB, - OP2_PXORDQ_VdqWdq = 0xEF, - OP2_PSLLD_VdqWdq = 0xF2, - OP2_PMULUDQ_VdqWdq = 0xF4, - OP2_PSUBD_VdqWdq = 0xFA, - OP2_PADDD_VdqWdq = 0xFE - }; - - // Test whether the given opcode should be printed with its operands reversed. - static bool IsXMMReversedOperands(TwoByteOpcodeID opcode) { - switch (opcode) { - case OP2_MOVSD_WsdVsd: // also OP2_MOVPS_WpsVps - case OP2_MOVAPS_WsdVsd: - case OP2_MOVDQ_WdqVdq: - case OP3_PEXTRD_EdVdqIb: - return true; - default: - break; - } - return false; - } - - enum ThreeByteOpcodeID { - OP3_ROUNDSS_VsdWsd = 0x0A, - OP3_ROUNDSD_VsdWsd = 0x0B, - OP3_BLENDVPS_VdqWdq = 0x14, - OP3_PEXTRD_EdVdqIb = 0x16, - OP3_BLENDPS_VpsWpsIb = 0x0C, - OP3_PTEST_VdVd = 0x17, - OP3_INSERTPS_VpsUps = 0x21, - OP3_PINSRD_VdqEdIb = 0x22, - OP3_PMULLD_VdqWdq = 0x40, - OP3_VBLENDVPS_VdqWdq = 0x4A - }; - - enum ThreeByteEscape { - ESCAPE_BLENDVPS = 0x38, - ESCAPE_PMULLD = 0x38, - ESCAPE_PTEST = 0x38, - ESCAPE_PINSRD = 0x3A, - ESCAPE_PEXTRD = 0x3A, - ESCAPE_ROUNDSD = 0x3A, - ESCAPE_INSERTPS = 0x3A, - ESCAPE_BLENDPS = 0x3A, - ESCAPE_VBLENDVPS = 0x3A - }; - - enum VexOperandType { - VEX_PS = 0, - VEX_PD = 1, - VEX_SS = 2, - VEX_SD = 3 - }; - - OneByteOpcodeID jccRel8(Condition cond) - { - return (OneByteOpcodeID)(OP_JCC_rel8 + cond); - } - TwoByteOpcodeID jccRel32(Condition cond) - { - return (TwoByteOpcodeID)(OP2_JCC_rel32 + cond); - } - - TwoByteOpcodeID setccOpcode(Condition cond) - { - return (TwoByteOpcodeID)(OP_SETCC + cond); - } - - enum GroupOpcodeID { - GROUP1_OP_ADD = 0, - GROUP1_OP_OR = 1, - GROUP1_OP_ADC = 2, - GROUP1_OP_AND = 4, - GROUP1_OP_SUB = 5, - GROUP1_OP_XOR = 6, - GROUP1_OP_CMP = 7, - - GROUP1A_OP_POP = 0, - - GROUP2_OP_SHL = 4, - GROUP2_OP_SHR = 5, - GROUP2_OP_SAR = 7, - - GROUP3_OP_TEST = 0, - GROUP3_OP_NOT = 2, - GROUP3_OP_NEG = 3, - GROUP3_OP_IMUL = 5, - GROUP3_OP_DIV = 6, - GROUP3_OP_IDIV = 7, - - GROUP5_OP_INC = 0, - GROUP5_OP_DEC = 1, - GROUP5_OP_CALLN = 2, - GROUP5_OP_JMPN = 4, - GROUP5_OP_PUSH = 6, - - FPU6_OP_FLD = 0, - FPU6_OP_FISTTP = 1, - FPU6_OP_FSTP = 3, - - GROUP11_MOV = 0 - }; - -public: - X86Assembler() + BaseAssembler() : useVEX_(true) { } void disableVEX() { useVEX_ = false; } - class JmpSrc { - public: - JmpSrc() - : m_offset(-1) - { - } - - explicit JmpSrc(int32_t offset) - : m_offset(offset) - { - } - - int32_t offset() const { - return m_offset; - } - - bool isSet() const { - return m_offset != -1; - } - - private: - int m_offset; - }; - - class JmpDst { - public: - JmpDst() - : m_offset(-1) - , m_used(false) - { - } - - bool isUsed() const { return m_used; } - void used() { m_used = true; } - bool isValid() const { return m_offset != -1; } - - explicit JmpDst(int32_t offset) - : m_offset(offset) - , m_used(false) - { - MOZ_ASSERT(m_offset == offset); - } - int32_t offset() const { - return m_offset; - } - private: - signed int m_offset : 31; - bool m_used : 1; - }; - size_t size() const { return m_formatter.size(); } const unsigned char *buffer() const { return m_formatter.buffer(); } unsigned char *data() { return m_formatter.data(); } @@ -736,7 +165,7 @@ public: m_formatter.oneByteOp(OP_GROUP1_EvIb, dst, GROUP1_OP_ADD); m_formatter.immediate8s(imm); } else { - if (dst == X86Registers::eax) + if (dst == rax) m_formatter.oneByteOp(OP_ADD_EAXIv); else m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_ADD); @@ -747,7 +176,7 @@ public: { // 32-bit immediate always, for patching. spew("addl $0x%04x, %s", imm, GPReg32Name(dst)); - if (dst == X86Registers::eax) + if (dst == rax) m_formatter.oneByteOp(OP_ADD_EAXIv); else m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_ADD); @@ -792,7 +221,7 @@ public: m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_ADD); m_formatter.immediate8s(imm); } else { - if (dst == X86Registers::eax) + if (dst == rax) m_formatter.oneByteOp64(OP_ADD_EAXIv); else m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_ADD); @@ -901,15 +330,15 @@ public: void vpmulld_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) { - threeByteOpSimd("vpmulld", VEX_PD, OP3_PMULLD_VdqWdq, ESCAPE_PMULLD, src1, src0, dst); + threeByteOpSimd("vpmulld", VEX_PD, OP3_PMULLD_VdqWdq, ESCAPE_38, src1, src0, dst); } void vpmulld_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst) { - threeByteOpSimd("vpmulld", VEX_PD, OP3_PMULLD_VdqWdq, ESCAPE_PMULLD, offset, base, src0, dst); + threeByteOpSimd("vpmulld", VEX_PD, OP3_PMULLD_VdqWdq, ESCAPE_38, offset, base, src0, dst); } void vpmulld_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst) { - threeByteOpSimd("vpmulld", VEX_PD, OP3_PMULLD_VdqWdq, ESCAPE_PMULLD, address, src0, dst); + threeByteOpSimd("vpmulld", VEX_PD, OP3_PMULLD_VdqWdq, ESCAPE_38, address, src0, dst); } void vaddps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) @@ -1015,7 +444,7 @@ public: m_formatter.oneByteOp(OP_GROUP1_EvIb, dst, GROUP1_OP_AND); m_formatter.immediate8s(imm); } else { - if (dst == X86Registers::eax) + if (dst == rax) m_formatter.oneByteOp(OP_AND_EAXIv); else m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_AND); @@ -1079,7 +508,7 @@ public: m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_AND); m_formatter.immediate8s(imm); } else { - if (dst == X86Registers::eax) + if (dst == rax) m_formatter.oneByteOp64(OP_AND_EAXIv); else m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_AND); @@ -1175,7 +604,7 @@ public: m_formatter.oneByteOp(OP_GROUP1_EvIb, dst, GROUP1_OP_OR); m_formatter.immediate8s(imm); } else { - if (dst == X86Registers::eax) + if (dst == rax) m_formatter.oneByteOp(OP_OR_EAXIv); else m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_OR); @@ -1215,7 +644,7 @@ public: m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_OR); m_formatter.immediate8s(imm); } else { - if (dst == X86Registers::eax) + if (dst == rax) m_formatter.oneByteOp64(OP_OR_EAXIv); else m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_OR); @@ -1267,7 +696,7 @@ public: m_formatter.oneByteOp(OP_GROUP1_EvIb, dst, GROUP1_OP_SUB); m_formatter.immediate8s(imm); } else { - if (dst == X86Registers::eax) + if (dst == rax) m_formatter.oneByteOp(OP_SUB_EAXIv); else m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_SUB); @@ -1319,7 +748,7 @@ public: m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_SUB); m_formatter.immediate8s(imm); } else { - if (dst == X86Registers::eax) + if (dst == rax) m_formatter.oneByteOp64(OP_SUB_EAXIv); else m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_SUB); @@ -1377,7 +806,7 @@ public: m_formatter.oneByteOp(OP_GROUP1_EvIb, dst, GROUP1_OP_XOR); m_formatter.immediate8s(imm); } else { - if (dst == X86Registers::eax) + if (dst == rax) m_formatter.oneByteOp(OP_XOR_EAXIv); else m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_XOR); @@ -1399,7 +828,7 @@ public: m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_XOR); m_formatter.immediate8s(imm); } else { - if (dst == X86Registers::eax) + if (dst == rax) m_formatter.oneByteOp64(OP_XOR_EAXIv); else m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_XOR); @@ -1654,7 +1083,7 @@ public: m_formatter.oneByteOp(OP_GROUP1_EvIb, lhs, GROUP1_OP_CMP); m_formatter.immediate8s(rhs); } else { - if (lhs == X86Registers::eax) + if (lhs == rax) m_formatter.oneByteOp(OP_CMP_EAXIv); else m_formatter.oneByteOp(OP_GROUP1_EvIz, lhs, GROUP1_OP_CMP); @@ -1665,7 +1094,7 @@ public: void cmpl_i32r(int32_t rhs, RegisterID lhs) { spew("cmpl $0x%04x, %s", rhs, GPReg32Name(lhs)); - if (lhs == X86Registers::eax) + if (lhs == rax) m_formatter.oneByteOp(OP_CMP_EAXIv); else m_formatter.oneByteOp(OP_GROUP1_EvIz, lhs, GROUP1_OP_CMP); @@ -1789,7 +1218,7 @@ public: m_formatter.oneByteOp64(OP_GROUP1_EvIb, lhs, GROUP1_OP_CMP); m_formatter.immediate8s(rhs); } else { - if (lhs == X86Registers::eax) + if (lhs == rax) m_formatter.oneByteOp64(OP_CMP_EAXIv); else m_formatter.oneByteOp64(OP_GROUP1_EvIz, lhs, GROUP1_OP_CMP); @@ -1905,18 +1334,18 @@ public: { // If the mask fits in an 8-bit immediate, we can use testb with an // 8-bit subreg. - if (CAN_ZERO_EXTEND_8_32(rhs) && X86Registers::hasSubregL(lhs)) { + if (CAN_ZERO_EXTEND_8_32(rhs) && HasSubregL(lhs)) { testb_ir(rhs, lhs); return; } // If the mask is a subset of 0xff00, we can use testb with an h reg, if // one happens to be available. - if (CAN_ZERO_EXTEND_8H_32(rhs) && X86Registers::hasSubregH(lhs)) { - testb_ir_norex(rhs >> 8, X86Registers::getSubregH(lhs)); + if (CAN_ZERO_EXTEND_8H_32(rhs) && HasSubregH(lhs)) { + testb_ir_norex(rhs >> 8, GetSubregH(lhs)); return; } spew("testl $0x%x, %s", rhs, GPReg32Name(lhs)); - if (lhs == X86Registers::eax) + if (lhs == rax) m_formatter.oneByteOp(OP_TEST_EAXIv); else m_formatter.oneByteOp(OP_GROUP3_EvIz, lhs, GROUP3_OP_TEST); @@ -1974,7 +1403,7 @@ public: return; } spew("testq $0x%" PRIx64 ", %s", int64_t(rhs), GPReg64Name(lhs)); - if (lhs == X86Registers::eax) + if (lhs == rax) m_formatter.oneByteOp64(OP_TEST_EAXIv); else m_formatter.oneByteOp64(OP_GROUP3_EvIz, lhs, GROUP3_OP_TEST); @@ -2006,7 +1435,7 @@ public: void testb_ir(int32_t rhs, RegisterID lhs) { spew("testb $0x%x, %s", rhs, GPReg8Name(lhs)); - if (lhs == X86Registers::eax) + if (lhs == rax) m_formatter.oneByteOp8(OP_TEST_EAXIb); else m_formatter.oneByteOp8(OP_GROUP3_EbIb, lhs, GROUP3_OP_TEST); @@ -2015,16 +1444,16 @@ public: // Like testb_ir, but never emits a REX prefix. This may be used to // reference ah..bh. - void testb_ir_norex(int32_t rhs, RegisterID lhs) + void testb_ir_norex(int32_t rhs, HRegisterID lhs) { - spew("testb $0x%x, %s", rhs, GPReg8Name_norex(lhs)); + spew("testb $0x%x, %s", rhs, HRegName8(lhs)); m_formatter.oneByteOp8_norex(OP_GROUP3_EbIb, lhs, GROUP3_OP_TEST); m_formatter.immediate8(rhs); } void setCC_r(Condition cond, RegisterID lhs) { - spew("set%s %s", nameCC(cond), GPReg8Name(lhs)); + spew("set%s %s", CCName(cond), GPReg8Name(lhs)); m_formatter.twoByteOp8(setccOpcode(cond), lhs, (GroupOpcodeID)0); } @@ -2125,8 +1554,8 @@ public: void movl_mEAX(const void* addr) { #ifdef JS_CODEGEN_X64 - if (isAddressImmediate(addr)) { - movl_mr(addr, X86Registers::eax); + if (IsAddressImmediate(addr)) { + movl_mr(addr, rax); return; } #endif @@ -2158,7 +1587,7 @@ public: void movl_mr(const void* base, RegisterID index, int scale, RegisterID dst) { - int32_t disp = addressImmediate(base); + int32_t disp = AddressImmediate(base); spew("movl " MEM_os ", %s", ADDR_os(disp, index, scale), GPReg32Name(dst)); m_formatter.oneByteOp_disp32(OP_MOV_GvEv, disp, index, scale, dst); @@ -2172,9 +1601,9 @@ public: void movl_mr(const void* addr, RegisterID dst) { - if (dst == X86Registers::eax + if (dst == rax #ifdef JS_CODEGEN_X64 - && !isAddressImmediate(addr) + && !IsAddressImmediate(addr) #endif ) { @@ -2262,8 +1691,8 @@ public: void movl_EAXm(const void* addr) { #ifdef JS_CODEGEN_X64 - if (isAddressImmediate(addr)) { - movl_rm(X86Registers::eax, addr); + if (IsAddressImmediate(addr)) { + movl_rm(rax, addr); return; } #endif @@ -2304,7 +1733,7 @@ public: void movq_rm(RegisterID src, const void* addr) { - if (src == X86Registers::eax && !isAddressImmediate(addr)) { + if (src == rax && !IsAddressImmediate(addr)) { movq_EAXm(addr); return; } @@ -2315,8 +1744,8 @@ public: void movq_mEAX(const void* addr) { - if (isAddressImmediate(addr)) { - movq_mr(addr, X86Registers::eax); + if (IsAddressImmediate(addr)) { + movq_mr(addr, rax); return; } @@ -2327,8 +1756,8 @@ public: void movq_EAXm(const void* addr) { - if (isAddressImmediate(addr)) { - movq_rm(X86Registers::eax, addr); + if (IsAddressImmediate(addr)) { + movq_rm(rax, addr); return; } @@ -2357,7 +1786,7 @@ public: void movq_mr(const void* addr, RegisterID dst) { - if (dst == X86Registers::eax && !isAddressImmediate(addr)) { + if (dst == rax && !IsAddressImmediate(addr)) { movq_mEAX(addr); return; } @@ -2446,9 +1875,9 @@ public: #endif void movl_rm(RegisterID src, const void* addr) { - if (src == X86Registers::eax + if (src == rax #ifdef JS_CODEGEN_X64 - && !isAddressImmediate(addr) + && !IsAddressImmediate(addr) #endif ) { movl_EAXm(addr); @@ -2744,7 +2173,7 @@ public: void jCC_i(Condition cond, JmpDst dst) { int32_t diff = dst.offset() - m_formatter.size(); - spew("j%s .Llabel%d", nameCC(cond), dst.offset()); + spew("j%s .Llabel%d", CCName(cond), dst.offset()); // The jump immediate is an offset from the end of the jump instruction. // A conditional jump instruction is either 1 byte opcode and 1 byte @@ -2763,7 +2192,7 @@ public: { m_formatter.twoByteOp(jccRel32(cond)); JmpSrc r = m_formatter.immediateRel32(); - spew("j%s .Lfrom%d", nameCC(cond), r.offset()); + spew("j%s .Lfrom%d", CCName(cond), r.offset()); return r; } @@ -2814,33 +2243,33 @@ public: } void vrcpps_rr(XMMRegisterID src, XMMRegisterID dst) { - twoByteOpSimd("vrcpps", VEX_PS, OP2_RCPPS_VpsWps, src, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vrcpps", VEX_PS, OP2_RCPPS_VpsWps, src, invalid_xmm, dst); } void vrcpps_mr(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd("vrcpps", VEX_PS, OP2_RCPPS_VpsWps, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vrcpps", VEX_PS, OP2_RCPPS_VpsWps, offset, base, invalid_xmm, dst); } void vrcpps_mr(const void* address, XMMRegisterID dst) { - twoByteOpSimd("vrcpps", VEX_PS, OP2_RCPPS_VpsWps, address, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vrcpps", VEX_PS, OP2_RCPPS_VpsWps, address, invalid_xmm, dst); } void vrsqrtps_rr(XMMRegisterID src, XMMRegisterID dst) { - twoByteOpSimd("vrsqrtps", VEX_PS, OP2_RSQRTPS_VpsWps, src, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vrsqrtps", VEX_PS, OP2_RSQRTPS_VpsWps, src, invalid_xmm, dst); } void vrsqrtps_mr(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd("vrsqrtps", VEX_PS, OP2_RSQRTPS_VpsWps, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vrsqrtps", VEX_PS, OP2_RSQRTPS_VpsWps, offset, base, invalid_xmm, dst); } void vrsqrtps_mr(const void* address, XMMRegisterID dst) { - twoByteOpSimd("vrsqrtps", VEX_PS, OP2_RSQRTPS_VpsWps, address, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vrsqrtps", VEX_PS, OP2_RSQRTPS_VpsWps, address, invalid_xmm, dst); } void vsqrtps_rr(XMMRegisterID src, XMMRegisterID dst) { - twoByteOpSimd("vsqrtps", VEX_PS, OP2_SQRTPS_VpsWps, src, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vsqrtps", VEX_PS, OP2_SQRTPS_VpsWps, src, invalid_xmm, dst); } void vsqrtps_mr(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd("vsqrtps", VEX_PS, OP2_SQRTPS_VpsWps, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vsqrtps", VEX_PS, OP2_SQRTPS_VpsWps, offset, base, invalid_xmm, dst); } void vsqrtps_mr(const void* address, XMMRegisterID dst) { - twoByteOpSimd("vsqrtps", VEX_PS, OP2_SQRTPS_VpsWps, address, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vsqrtps", VEX_PS, OP2_SQRTPS_VpsWps, address, invalid_xmm, dst); } void vaddsd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) @@ -2894,12 +2323,12 @@ public: void vcvttps2dq_rr(XMMRegisterID src, XMMRegisterID dst) { - twoByteOpSimd("vcvttps2dq", VEX_SS, OP2_CVTTPS2DQ_VdqWps, src, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vcvttps2dq", VEX_SS, OP2_CVTTPS2DQ_VdqWps, src, invalid_xmm, dst); } void vcvtdq2ps_rr(XMMRegisterID src, XMMRegisterID dst) { - twoByteOpSimd("vcvtdq2ps", VEX_PS, OP2_CVTDQ2PS_VpsWdq, src, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vcvtdq2ps", VEX_PS, OP2_CVTDQ2PS_VpsWdq, src, invalid_xmm, dst); } #ifdef JS_CODEGEN_X64 @@ -3039,15 +2468,15 @@ public: void vpshufd_irr(uint32_t mask, XMMRegisterID src, XMMRegisterID dst) { - twoByteOpImmSimd("vpshufd", VEX_PD, OP2_PSHUFD_VdqWdqIb, mask, src, X86Registers::invalid_xmm, dst); + twoByteOpImmSimd("vpshufd", VEX_PD, OP2_PSHUFD_VdqWdqIb, mask, src, invalid_xmm, dst); } void vpshufd_imr(uint32_t mask, int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpImmSimd("vpshufd", VEX_PD, OP2_PSHUFD_VdqWdqIb, mask, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpImmSimd("vpshufd", VEX_PD, OP2_PSHUFD_VdqWdqIb, mask, offset, base, invalid_xmm, dst); } void vpshufd_imr(uint32_t mask, const void* address, XMMRegisterID dst) { - twoByteOpImmSimd("vpshufd", VEX_PD, OP2_PSHUFD_VdqWdqIb, mask, address, X86Registers::invalid_xmm, dst); + twoByteOpImmSimd("vpshufd", VEX_PD, OP2_PSHUFD_VdqWdqIb, mask, address, invalid_xmm, dst); } void vshufps_irr(uint32_t mask, XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) @@ -3076,19 +2505,19 @@ public: void vpsrldq_ir(uint32_t count, XMMRegisterID src, XMMRegisterID dst) { MOZ_ASSERT(count < 16); - shiftOpImmSimd("vpsrldq", OP2_PSRLDQ_Vd, Shift_vpsrldq, count, src, dst); + shiftOpImmSimd("vpsrldq", OP2_PSRLDQ_Vd, ShiftID::vpsrldq, count, src, dst); } void vpsllq_ir(uint32_t count, XMMRegisterID src, XMMRegisterID dst) { MOZ_ASSERT(count < 64); - shiftOpImmSimd("vpsllq", OP2_PSRLDQ_Vd, Shift_vpsllq, count, src, dst); + shiftOpImmSimd("vpsllq", OP2_PSRLDQ_Vd, ShiftID::vpsllq, count, src, dst); } void vpsrlq_ir(uint32_t count, XMMRegisterID src, XMMRegisterID dst) { MOZ_ASSERT(count < 64); - shiftOpImmSimd("vpsrlq", OP2_PSRLDQ_Vd, Shift_vpsrlq, count, src, dst); + shiftOpImmSimd("vpsrlq", OP2_PSRLDQ_Vd, ShiftID::vpsrlq, count, src, dst); } void vpslld_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) @@ -3099,7 +2528,7 @@ public: void vpslld_ir(uint32_t count, XMMRegisterID src, XMMRegisterID dst) { MOZ_ASSERT(count < 32); - shiftOpImmSimd("vpslld", OP2_PSLLD_UdqIb, Shift_vpslld, count, src, dst); + shiftOpImmSimd("vpslld", OP2_PSLLD_UdqIb, ShiftID::vpslld, count, src, dst); } void vpsrad_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) @@ -3110,7 +2539,7 @@ public: void vpsrad_ir(int32_t count, XMMRegisterID src, XMMRegisterID dst) { MOZ_ASSERT(count < 32); - shiftOpImmSimd("vpsrad", OP2_PSRAD_UdqIb, Shift_vpsrad, count, src, dst); + shiftOpImmSimd("vpsrad", OP2_PSRAD_UdqIb, ShiftID::vpsrad, count, src, dst); } void vpsrld_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) @@ -3121,7 +2550,7 @@ public: void vpsrld_ir(uint32_t count, XMMRegisterID src, XMMRegisterID dst) { MOZ_ASSERT(count < 32); - shiftOpImmSimd("vpsrld", OP2_PSRLD_UdqIb, Shift_vpsrld, count, src, dst); + shiftOpImmSimd("vpsrld", OP2_PSRLD_UdqIb, ShiftID::vpsrld, count, src, dst); } void vmovmskpd_rr(XMMRegisterID src, RegisterID dst) @@ -3135,7 +2564,7 @@ public: } void vptest_rr(XMMRegisterID rhs, XMMRegisterID lhs) { - threeByteOpSimd("vptest", VEX_PD, OP3_PTEST_VdVd, ESCAPE_PTEST, rhs, X86Registers::invalid_xmm, lhs); + threeByteOpSimd("vptest", VEX_PD, OP3_PTEST_VdVd, ESCAPE_38, rhs, invalid_xmm, lhs); } void vmovd_rr(XMMRegisterID src, RegisterID dst) @@ -3145,7 +2574,7 @@ public: void vmovd_rr(RegisterID src, XMMRegisterID dst) { - twoByteOpInt32Simd("vmovd", VEX_PD, OP2_MOVD_VdEd, src, X86Registers::invalid_xmm, dst); + twoByteOpInt32Simd("vmovd", VEX_PD, OP2_MOVD_VdEd, src, invalid_xmm, dst); } #ifdef JS_CODEGEN_X64 @@ -3156,68 +2585,68 @@ public: void vmovq_rr(RegisterID src, XMMRegisterID dst) { - twoByteOpInt64Simd("vmovq", VEX_PD, OP2_MOVD_VdEd, src, X86Registers::invalid_xmm, dst); + twoByteOpInt64Simd("vmovq", VEX_PD, OP2_MOVD_VdEd, src, invalid_xmm, dst); } #endif void vmovsd_rm(XMMRegisterID src, int32_t offset, RegisterID base) { - twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, offset, base, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, offset, base, invalid_xmm, src); } void vmovsd_rm_disp32(XMMRegisterID src, int32_t offset, RegisterID base) { - twoByteOpSimd_disp32("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, offset, base, X86Registers::invalid_xmm, src); + twoByteOpSimd_disp32("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, offset, base, invalid_xmm, src); } void vmovss_rm(XMMRegisterID src, int32_t offset, RegisterID base) { - twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, offset, base, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, offset, base, invalid_xmm, src); } void vmovss_rm_disp32(XMMRegisterID src, int32_t offset, RegisterID base) { - twoByteOpSimd_disp32("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, offset, base, X86Registers::invalid_xmm, src); + twoByteOpSimd_disp32("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, offset, base, invalid_xmm, src); } void vmovss_mr(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, offset, base, invalid_xmm, dst); } void vmovss_mr_disp32(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd_disp32("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd_disp32("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, offset, base, invalid_xmm, dst); } void vmovsd_rm(XMMRegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale) { - twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, offset, base, index, scale, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, offset, base, index, scale, invalid_xmm, src); } void vmovss_rm(XMMRegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale) { - twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, offset, base, index, scale, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, offset, base, index, scale, invalid_xmm, src); } void vmovss_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst) { - twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, offset, base, index, scale, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, offset, base, index, scale, invalid_xmm, dst); } void vmovsd_mr(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, offset, base, invalid_xmm, dst); } void vmovsd_mr_disp32(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd_disp32("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd_disp32("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, offset, base, invalid_xmm, dst); } void vmovsd_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst) { - twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, offset, base, index, scale, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, offset, base, index, scale, invalid_xmm, dst); } // Note that the register-to-register form of vmovsd does not write to the @@ -3237,83 +2666,83 @@ public: void vmovsd_mr(const void* address, XMMRegisterID dst) { - twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, address, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, address, invalid_xmm, dst); } void vmovss_mr(const void* address, XMMRegisterID dst) { - twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, address, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, address, invalid_xmm, dst); } void vmovups_mr(const void* address, XMMRegisterID dst) { - twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_VpsWps, address, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_VpsWps, address, invalid_xmm, dst); } void vmovdqu_mr(const void* address, XMMRegisterID dst) { - twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_VdqWdq, address, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_VdqWdq, address, invalid_xmm, dst); } void vmovsd_rm(XMMRegisterID src, const void* address) { - twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, address, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, address, invalid_xmm, src); } void vmovss_rm(XMMRegisterID src, const void* address) { - twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, address, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, address, invalid_xmm, src); } void vmovdqa_rm(XMMRegisterID src, const void* address) { - twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, address, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, address, invalid_xmm, src); } void vmovaps_rm(XMMRegisterID src, const void* address) { - twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_WsdVsd, address, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_WsdVsd, address, invalid_xmm, src); } void vmovdqu_rm(XMMRegisterID src, const void* address) { - twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_WdqVdq, address, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_WdqVdq, address, invalid_xmm, src); } void vmovups_rm(XMMRegisterID src, const void* address) { - twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_WpsVps, address, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_WpsVps, address, invalid_xmm, src); } #ifdef JS_CODEGEN_X64 MOZ_WARN_UNUSED_RESULT JmpSrc vmovsd_ripr(XMMRegisterID dst) { - return twoByteRipOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, X86Registers::invalid_xmm, dst); + return twoByteRipOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, invalid_xmm, dst); } MOZ_WARN_UNUSED_RESULT JmpSrc vmovss_ripr(XMMRegisterID dst) { - return twoByteRipOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, X86Registers::invalid_xmm, dst); + return twoByteRipOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, invalid_xmm, dst); } MOZ_WARN_UNUSED_RESULT JmpSrc vmovsd_rrip(XMMRegisterID src) { - return twoByteRipOpSimd("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, X86Registers::invalid_xmm, src); + return twoByteRipOpSimd("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, invalid_xmm, src); } MOZ_WARN_UNUSED_RESULT JmpSrc vmovss_rrip(XMMRegisterID src) { - return twoByteRipOpSimd("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, X86Registers::invalid_xmm, src); + return twoByteRipOpSimd("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, invalid_xmm, src); } MOZ_WARN_UNUSED_RESULT JmpSrc vmovdqa_rrip(XMMRegisterID src) { - return twoByteRipOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, X86Registers::invalid_xmm, src); + return twoByteRipOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, invalid_xmm, src); } MOZ_WARN_UNUSED_RESULT JmpSrc vmovaps_rrip(XMMRegisterID src) { - return twoByteRipOpSimd("vmovdqa", VEX_PS, OP2_MOVAPS_WsdVsd, X86Registers::invalid_xmm, src); + return twoByteRipOpSimd("vmovdqa", VEX_PS, OP2_MOVAPS_WsdVsd, invalid_xmm, src); } #endif @@ -3324,53 +2753,53 @@ public: // one register in [xmm8,xmm15] and one in [xmm0,xmm7], use the // opcode which swaps the operands, as that way we can get a two-byte // VEX in that case. - if (src >= X86Registers::xmm8 && dst < X86Registers::xmm8) { - twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_WsdVsd, dst, X86Registers::invalid_xmm, src); + if (src >= xmm8 && dst < xmm8) { + twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_WsdVsd, dst, invalid_xmm, src); return; } #endif - twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, src, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, src, invalid_xmm, dst); } void vmovaps_rm(XMMRegisterID src, int32_t offset, RegisterID base) { - twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_WsdVsd, offset, base, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_WsdVsd, offset, base, invalid_xmm, src); } void vmovaps_rm(XMMRegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale) { - twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_WsdVsd, offset, base, index, scale, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_WsdVsd, offset, base, index, scale, invalid_xmm, src); } void vmovaps_mr(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, offset, base, invalid_xmm, dst); } void vmovaps_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst) { - twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, offset, base, index, scale, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, offset, base, index, scale, invalid_xmm, dst); } void vmovups_rm(XMMRegisterID src, int32_t offset, RegisterID base) { - twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_WpsVps, offset, base, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_WpsVps, offset, base, invalid_xmm, src); } void vmovups_rm_disp32(XMMRegisterID src, int32_t offset, RegisterID base) { - twoByteOpSimd_disp32("vmovups", VEX_PS, OP2_MOVPS_WpsVps, offset, base, X86Registers::invalid_xmm, src); + twoByteOpSimd_disp32("vmovups", VEX_PS, OP2_MOVPS_WpsVps, offset, base, invalid_xmm, src); } void vmovups_rm(XMMRegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale) { - twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_WpsVps, offset, base, index, scale, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_WpsVps, offset, base, index, scale, invalid_xmm, src); } void vmovups_mr(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_VpsWps, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_VpsWps, offset, base, invalid_xmm, dst); } void vmovups_mr_disp32(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd_disp32("vmovups", VEX_PS, OP2_MOVPS_VpsWps, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd_disp32("vmovups", VEX_PS, OP2_MOVPS_VpsWps, offset, base, invalid_xmm, dst); } void vmovups_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst) { - twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_VpsWps, offset, base, index, scale, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_VpsWps, offset, base, index, scale, invalid_xmm, dst); } void vmovapd_rr(XMMRegisterID src, XMMRegisterID dst) @@ -3380,66 +2809,66 @@ public: // one register in [xmm8,xmm15] and one in [xmm0,xmm7], use the // opcode which swaps the operands, as that way we can get a two-byte // VEX in that case. - if (src >= X86Registers::xmm8 && dst < X86Registers::xmm8) { - twoByteOpSimd("vmovapd", VEX_PD, OP2_MOVAPS_WsdVsd, dst, X86Registers::invalid_xmm, src); + if (src >= xmm8 && dst < xmm8) { + twoByteOpSimd("vmovapd", VEX_PD, OP2_MOVAPS_WsdVsd, dst, invalid_xmm, src); return; } #endif - twoByteOpSimd("vmovapd", VEX_PD, OP2_MOVAPD_VsdWsd, src, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovapd", VEX_PD, OP2_MOVAPD_VsdWsd, src, invalid_xmm, dst); } #ifdef JS_CODEGEN_X64 MOZ_WARN_UNUSED_RESULT JmpSrc vmovaps_ripr(XMMRegisterID dst) { - return twoByteRipOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, X86Registers::invalid_xmm, dst); + return twoByteRipOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, invalid_xmm, dst); } MOZ_WARN_UNUSED_RESULT JmpSrc vmovdqa_ripr(XMMRegisterID dst) { - return twoByteRipOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, X86Registers::invalid_xmm, dst); + return twoByteRipOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, invalid_xmm, dst); } #else void vmovaps_mr(const void* address, XMMRegisterID dst) { - twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, address, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, address, invalid_xmm, dst); } void vmovdqa_mr(const void* address, XMMRegisterID dst) { - twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, address, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, address, invalid_xmm, dst); } #endif // JS_CODEGEN_X64 void vmovdqu_rm(XMMRegisterID src, int32_t offset, RegisterID base) { - twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_WdqVdq, offset, base, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_WdqVdq, offset, base, invalid_xmm, src); } void vmovdqu_rm_disp32(XMMRegisterID src, int32_t offset, RegisterID base) { - twoByteOpSimd_disp32("vmovdqu", VEX_SS, OP2_MOVDQ_WdqVdq, offset, base, X86Registers::invalid_xmm, src); + twoByteOpSimd_disp32("vmovdqu", VEX_SS, OP2_MOVDQ_WdqVdq, offset, base, invalid_xmm, src); } void vmovdqu_rm(XMMRegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale) { - twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_WdqVdq, offset, base, index, scale, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_WdqVdq, offset, base, index, scale, invalid_xmm, src); } void vmovdqu_mr(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_VdqWdq, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_VdqWdq, offset, base, invalid_xmm, dst); } void vmovdqu_mr_disp32(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd_disp32("vmovdqu", VEX_SS, OP2_MOVDQ_VdqWdq, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd_disp32("vmovdqu", VEX_SS, OP2_MOVDQ_VdqWdq, offset, base, invalid_xmm, dst); } void vmovdqu_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst) { - twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_VdqWdq, offset, base, index, scale, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_VdqWdq, offset, base, index, scale, invalid_xmm, dst); } void vmovdqa_rr(XMMRegisterID src, XMMRegisterID dst) @@ -3449,33 +2878,33 @@ public: // one register in [xmm8,xmm15] and one in [xmm0,xmm7], use the // opcode which swaps the operands, as that way we can get a two-byte // VEX in that case. - if (src >= X86Registers::xmm8 && dst < X86Registers::xmm8) { - twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, dst, X86Registers::invalid_xmm, src); + if (src >= xmm8 && dst < xmm8) { + twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, dst, invalid_xmm, src); return; } #endif - twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, src, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, src, invalid_xmm, dst); } void vmovdqa_rm(XMMRegisterID src, int32_t offset, RegisterID base) { - twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, offset, base, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, offset, base, invalid_xmm, src); } void vmovdqa_rm(XMMRegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale) { - twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, offset, base, index, scale, X86Registers::invalid_xmm, src); + twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, offset, base, index, scale, invalid_xmm, src); } void vmovdqa_mr(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, offset, base, invalid_xmm, dst); } void vmovdqa_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst) { - twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, offset, base, index, scale, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, offset, base, index, scale, invalid_xmm, dst); } void vmulsd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) @@ -3646,39 +3075,39 @@ public: void vroundsd_irr(RoundingMode mode, XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) { - threeByteOpImmSimd("vroundsd", VEX_PD, OP3_ROUNDSD_VsdWsd, ESCAPE_ROUNDSD, mode, src1, src0, dst); + threeByteOpImmSimd("vroundsd", VEX_PD, OP3_ROUNDSD_VsdWsd, ESCAPE_3A, mode, src1, src0, dst); } void vroundss_irr(RoundingMode mode, XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) { - threeByteOpImmSimd("vroundss", VEX_PD, OP3_ROUNDSS_VsdWsd, ESCAPE_ROUNDSD, mode, src1, src0, dst); + threeByteOpImmSimd("vroundss", VEX_PD, OP3_ROUNDSS_VsdWsd, ESCAPE_3A, mode, src1, src0, dst); } void vinsertps_irr(uint32_t mask, XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) { - threeByteOpImmSimd("vinsertps", VEX_PD, OP3_INSERTPS_VpsUps, ESCAPE_INSERTPS, mask, src1, src0, dst); + threeByteOpImmSimd("vinsertps", VEX_PD, OP3_INSERTPS_VpsUps, ESCAPE_3A, mask, src1, src0, dst); } void vinsertps_imr(uint32_t mask, int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst) { - threeByteOpImmSimd("vinsertps", VEX_PD, OP3_INSERTPS_VpsUps, ESCAPE_INSERTPS, mask, offset, base, src0, dst); + threeByteOpImmSimd("vinsertps", VEX_PD, OP3_INSERTPS_VpsUps, ESCAPE_3A, mask, offset, base, src0, dst); } void vpinsrd_irr(unsigned lane, RegisterID src1, XMMRegisterID src0, XMMRegisterID dst) { MOZ_ASSERT(lane < 4); - threeByteOpImmInt32Simd("vpinsrd", VEX_PD, OP3_PINSRD_VdqEdIb, ESCAPE_PINSRD, lane, src1, src0, dst); + threeByteOpImmInt32Simd("vpinsrd", VEX_PD, OP3_PINSRD_VdqEdIb, ESCAPE_3A, lane, src1, src0, dst); } void vpinsrd_imr(unsigned lane, int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst) { MOZ_ASSERT(lane < 4); - threeByteOpImmInt32Simd("vpinsrd", VEX_PD, OP3_PINSRD_VdqEdIb, ESCAPE_PINSRD, lane, offset, base, src0, dst); + threeByteOpImmInt32Simd("vpinsrd", VEX_PD, OP3_PINSRD_VdqEdIb, ESCAPE_3A, lane, offset, base, src0, dst); } void vpextrd_irr(unsigned lane, XMMRegisterID src, RegisterID dst) { MOZ_ASSERT(lane < 4); - threeByteOpImmSimdInt32("vpextrd", VEX_PD, OP3_PEXTRD_EdVdqIb, ESCAPE_PEXTRD, lane, (XMMRegisterID)dst, (RegisterID)src); + threeByteOpImmSimdInt32("vpextrd", VEX_PD, OP3_PEXTRD_EdVdqIb, ESCAPE_3A, lane, (XMMRegisterID)dst, (RegisterID)src); } void vpextrd_irm(unsigned lane, XMMRegisterID src, int32_t offset, RegisterID base) @@ -3686,7 +3115,7 @@ public: MOZ_ASSERT(lane < 4); spew("pextrd $0x%x, %s, " MEM_ob, lane, XMMRegName(src), ADDR_ob(offset, base)); m_formatter.prefix(PRE_SSE_66); - m_formatter.threeByteOp(OP3_PEXTRD_EdVdqIb, ESCAPE_PEXTRD, offset, base, (RegisterID)src); + m_formatter.threeByteOp(OP3_PEXTRD_EdVdqIb, ESCAPE_3A, offset, base, (RegisterID)src); m_formatter.immediate8u(lane); } @@ -3694,14 +3123,14 @@ public: { MOZ_ASSERT(imm < 16); // Despite being a "ps" instruction, vblendps is encoded with the "pd" prefix. - threeByteOpImmSimd("vblendps", VEX_PD, OP3_BLENDPS_VpsWpsIb, ESCAPE_BLENDPS, imm, src1, src0, dst); + threeByteOpImmSimd("vblendps", VEX_PD, OP3_BLENDPS_VpsWpsIb, ESCAPE_3A, imm, src1, src0, dst); } void vblendps_imr(unsigned imm, int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst) { MOZ_ASSERT(imm < 16); // Despite being a "ps" instruction, vblendps is encoded with the "pd" prefix. -threeByteOpImmSimd("vblendps", VEX_PD, OP3_BLENDPS_VpsWpsIb, ESCAPE_BLENDPS, imm, offset, base, src0, dst); +threeByteOpImmSimd("vblendps", VEX_PD, OP3_BLENDPS_VpsWpsIb, ESCAPE_3A, imm, offset, base, src0, dst); } void vblendvps_rr(XMMRegisterID mask, XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) { @@ -3713,20 +3142,20 @@ threeByteOpImmSimd("vblendps", VEX_PD, OP3_BLENDPS_VpsWpsIb, ESCAPE_BLENDPS, imm void vmovsldup_rr(XMMRegisterID src, XMMRegisterID dst) { - twoByteOpSimd("vmovsldup", VEX_SS, OP2_MOVSLDUP_VpsWps, src, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovsldup", VEX_SS, OP2_MOVSLDUP_VpsWps, src, invalid_xmm, dst); } void vmovsldup_mr(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd("vmovsldup", VEX_SS, OP2_MOVSLDUP_VpsWps, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovsldup", VEX_SS, OP2_MOVSLDUP_VpsWps, offset, base, invalid_xmm, dst); } void vmovshdup_rr(XMMRegisterID src, XMMRegisterID dst) { - twoByteOpSimd("vmovshdup", VEX_SS, OP2_MOVSHDUP_VpsWps, src, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovshdup", VEX_SS, OP2_MOVSHDUP_VpsWps, src, invalid_xmm, dst); } void vmovshdup_mr(int32_t offset, RegisterID base, XMMRegisterID dst) { - twoByteOpSimd("vmovshdup", VEX_SS, OP2_MOVSHDUP_VpsWps, offset, base, X86Registers::invalid_xmm, dst); + twoByteOpSimd("vmovshdup", VEX_SS, OP2_MOVSHDUP_VpsWps, offset, base, invalid_xmm, dst); } void vminsd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) @@ -3869,17 +3298,7 @@ threeByteOpImmSimd("vblendps", VEX_PD, OP3_BLENDPS_VpsWpsIb, ESCAPE_BLENDPS, imm } // Linking & patching: - // - // 'link' and 'patch' methods are for use on unprotected code - such as the - // code within the AssemblerBuffer, and code being patched by the patch - // buffer. Once code has been finalized it is (platform support permitting) - // within a non- writable region of memory; to modify the code in an - // execute-only execuable pool the 'repatch' and 'relink' methods should be - // used. - // Like Lua's emitter, we thread jump lists through the unpatched target - // field, which will get fixed up when the label (which has a pointer to the - // head of the jump list) is bound. bool nextJump(const JmpSrc& from, JmpSrc* next) { // Sanity check - if the assembler has OOM'd, it will start overwriting @@ -3888,7 +3307,7 @@ threeByteOpImmSimd("vblendps", VEX_PD, OP3_BLENDPS_VpsWpsIb, ESCAPE_BLENDPS, imm return false; const unsigned char* code = m_formatter.data(); - int32_t offset = getInt32(code + from.offset()); + int32_t offset = GetInt32(code + from.offset()); if (offset == -1) return false; *next = JmpSrc(offset); @@ -3902,7 +3321,7 @@ threeByteOpImmSimd("vblendps", VEX_PD, OP3_BLENDPS_VpsWpsIb, ESCAPE_BLENDPS, imm return; unsigned char* code = m_formatter.data(); - setInt32(code + from.offset(), to.offset()); + SetInt32(code + from.offset(), to.offset()); } void linkJump(JmpSrc from, JmpDst to) @@ -3917,13 +3336,7 @@ threeByteOpImmSimd("vblendps", VEX_PD, OP3_BLENDPS_VpsWpsIb, ESCAPE_BLENDPS, imm spew(".set .Lfrom%d, .Llabel%d", from.offset(), to.offset()); unsigned char* code = m_formatter.data(); - setRel32(code + from.offset(), code + to.offset()); - } - - static bool canRelinkJump(void* from, void* to) - { - intptr_t offset = static_cast(to) - static_cast(from); - return (offset == static_cast(offset)); + SetRel32(code + from.offset(), code + to.offset()); } void executableCopy(void* buffer) @@ -3931,64 +3344,14 @@ threeByteOpImmSimd("vblendps", VEX_PD, OP3_BLENDPS_VpsWpsIb, ESCAPE_BLENDPS, imm memcpy(buffer, m_formatter.buffer(), size()); } - static void setRel32(void* from, void* to) - { - intptr_t offset = static_cast(to) - static_cast(from); - MOZ_ASSERT(offset == static_cast(offset), - "offset is too great for a 32-bit relocation"); - if (offset != static_cast(offset)) - MOZ_CRASH("offset is too great for a 32-bit relocation"); + private: + static bool CAN_SIGN_EXTEND_8_32(int32_t value) { return value == (int32_t)(int8_t)value; } + static bool CAN_SIGN_EXTEND_16_32(int32_t value) { return value == (int32_t)(int16_t)value; } + static bool CAN_ZERO_EXTEND_8_32(int32_t value) { return value == (int32_t)(uint8_t)value; } + static bool CAN_ZERO_EXTEND_8H_32(int32_t value) { return value == (value & 0xff00); } + static bool CAN_ZERO_EXTEND_16_32(int32_t value) { return value == (int32_t)(uint16_t)value; } + static bool CAN_ZERO_EXTEND_32_64(int32_t value) { return value >= 0; } - setInt32(from, offset); - } - - static void *getRel32Target(void* where) - { - int32_t rel = getInt32(where); - return (char *)where + rel; - } - - static void *getPointer(const void* where) - { - return static_cast(where)[-1]; - } - - static void **getPointerRef(void* where) - { - return &static_cast(where)[-1]; - } - - static void setPointer(void* where, const void* value) - { - static_cast(where)[-1] = value; - } - - // Test whether the given address will fit in an address immediate field. - // This is always true on x86, but on x64 it's only true for addreses which - // fit in the 32-bit immediate field. - static bool isAddressImmediate(const void *address) { - intptr_t value = reinterpret_cast(address); - int32_t immediate = static_cast(value); - return value == immediate; - } - - // Convert the given address to a 32-bit immediate field value. This is a - // no-op on x86, but on x64 it asserts that the address is actually a valid - // address immediate. - static int32_t addressImmediate(const void *address) { -#ifdef JS_CODEGEN_X64 - // x64's 64-bit addresses don't all fit in the 32-bit immediate. - MOZ_ASSERT(isAddressImmediate(address)); -#endif - return static_cast(reinterpret_cast(address)); - } - - static void setInt32(void* where, int32_t value) - { - static_cast(where)[-1] = value; - } - -private: // Methods for encoding SIMD instructions via either legacy SSE encoding or // VEX encoding. @@ -3996,7 +3359,7 @@ private: { // If we don't have AVX or it's disabled, use the legacy SSE encoding. if (!useVEX_) { - MOZ_ASSERT(src0 == X86Registers::invalid_xmm || src0 == dst, + MOZ_ASSERT(src0 == invalid_xmm || src0 == dst, "Legacy SSE (pre-AVX) encoding requires the output register to be " "the same as the src0 input register"); return true; @@ -4017,13 +3380,13 @@ private: MOZ_ASSERT(src0 == dst, "Legacy SSE (pre-AVX) encoding requires the output register to be " "the same as the src0 input register"); - MOZ_ASSERT(mask == X86Registers::xmm0, + MOZ_ASSERT(mask == xmm0, "Legacy SSE (pre-AVX) encoding for blendv requires the mask to be " "in xmm0"); return true; } - return src0 == dst && mask == X86Registers::xmm0; + return src0 == dst && mask == xmm0; } bool useLegacySSEEncodingForOtherOutput() @@ -4055,7 +3418,7 @@ private: m_formatter.twoByteRipOpVex(ty, opcode, 0, src0, dst); JmpSrc label(m_formatter.size()); - if (src0 == X86Registers::invalid_xmm) { + if (src0 == invalid_xmm) { if (IsXMMReversedOperands(opcode)) spew("%-11s%s, " MEM_o32r "", name, XMMRegName(dst), ADDR_o32r(label.offset())); else @@ -4080,7 +3443,7 @@ private: return; } - if (src0 == X86Registers::invalid_xmm) { + if (src0 == invalid_xmm) { if (IsXMMReversedOperands(opcode)) spew("%-11s%s, %s", name, XMMRegName(dst), XMMRegName(rm)); else @@ -4102,7 +3465,7 @@ private: return; } - if (src0 == X86Registers::invalid_xmm) + if (src0 == invalid_xmm) spew("%-11s$0x%x, %s, %s", name, imm, XMMRegName(rm), XMMRegName(dst)); else spew("%-11s$0x%x, %s, %s, %s", name, imm, XMMRegName(rm), XMMRegName(src0), XMMRegName(dst)); @@ -4126,7 +3489,7 @@ private: return; } - if (src0 == X86Registers::invalid_xmm) { + if (src0 == invalid_xmm) { if (IsXMMReversedOperands(opcode)) spew("%-11s%s, " MEM_ob, name, XMMRegName(dst), ADDR_ob(offset, base)); else @@ -4151,7 +3514,7 @@ private: return; } - if (src0 == X86Registers::invalid_xmm) { + if (src0 == invalid_xmm) { if (IsXMMReversedOperands(opcode)) spew("%-11s%s, " MEM_o32b, name, XMMRegName(dst), ADDR_o32b(offset, base)); else @@ -4198,7 +3561,7 @@ private: return; } - if (src0 == X86Registers::invalid_xmm) { + if (src0 == invalid_xmm) { if (IsXMMReversedOperands(opcode)) { spew("%-11s%s, " MEM_obs, name, XMMRegName(dst), ADDR_obs(offset, base, index, scale)); @@ -4226,7 +3589,7 @@ private: return; } - if (src0 == X86Registers::invalid_xmm) { + if (src0 == invalid_xmm) { if (IsXMMReversedOperands(opcode)) spew("%-11s%s, %p", name, XMMRegName(dst), address); else @@ -4266,7 +3629,7 @@ private: return; } - if (src0 == X86Registers::invalid_xmm) { + if (src0 == invalid_xmm) { if (IsXMMReversedOperands(opcode)) spew("%-11s%s, %s", name, XMMRegName(dst), GPReg32Name(rm)); else @@ -4291,7 +3654,7 @@ private: return; } - if (src0 == X86Registers::invalid_xmm) { + if (src0 == invalid_xmm) { if (IsXMMReversedOperands(opcode)) spew("%-11s%s, %s", name, XMMRegName(dst), GPRegName(rm)); else @@ -4324,7 +3687,7 @@ private: spew("%-11s%s, %s", name, XMMRegName((XMMRegisterID)dst), GPReg32Name((RegisterID)rm)); else spew("%-11s%s, %s", name, XMMRegName(rm), GPReg32Name(dst)); - m_formatter.twoByteOpVex(ty, opcode, (RegisterID)rm, X86Registers::invalid_xmm, dst); + m_formatter.twoByteOpVex(ty, opcode, (RegisterID)rm, invalid_xmm, dst); } void twoByteOpImmSimdInt32(const char *name, VexOperandType ty, TwoByteOpcodeID opcode, @@ -4339,7 +3702,7 @@ private: } spew("%-11s$0x%x, %s, %s", name, imm, XMMRegName(rm), GPReg32Name(dst)); - m_formatter.twoByteOpVex(ty, opcode, (RegisterID)rm, X86Registers::invalid_xmm, dst); + m_formatter.twoByteOpVex(ty, opcode, (RegisterID)rm, invalid_xmm, dst); m_formatter.immediate8u(imm); } @@ -4365,7 +3728,7 @@ private: spew("%-11s%s, %s", name, XMMRegName((XMMRegisterID)dst), GPRegName((RegisterID)rm)); else spew("%-11s%s, %s", name, XMMRegName(rm), GPRegName(dst)); - m_formatter.twoByteOpVex64(ty, opcode, (RegisterID)rm, X86Registers::invalid_xmm, (XMMRegisterID)dst); + m_formatter.twoByteOpVex64(ty, opcode, (RegisterID)rm, invalid_xmm, (XMMRegisterID)dst); } #endif @@ -4380,7 +3743,7 @@ private: } spew("%-11s%s, %s", name, XMMRegName(rm), XMMRegName(reg)); - m_formatter.twoByteOpVex(ty, opcode, (RegisterID)rm, X86Registers::invalid_xmm, (XMMRegisterID)reg); + m_formatter.twoByteOpVex(ty, opcode, (RegisterID)rm, invalid_xmm, (XMMRegisterID)reg); } void twoByteOpSimdFlags(const char *name, VexOperandType ty, TwoByteOpcodeID opcode, @@ -4396,7 +3759,7 @@ private: spew("%-11s" MEM_ob ", %s", name, ADDR_ob(offset, base), XMMRegName(reg)); - m_formatter.twoByteOpVex(ty, opcode, offset, base, X86Registers::invalid_xmm, (XMMRegisterID)reg); + m_formatter.twoByteOpVex(ty, opcode, offset, base, invalid_xmm, (XMMRegisterID)reg); } void threeByteOpSimd(const char *name, VexOperandType ty, ThreeByteOpcodeID opcode, @@ -4532,7 +3895,7 @@ private: spew("%-11s$0x%x, %s, %s", name, imm, XMMRegName((XMMRegisterID)dst), GPReg32Name((RegisterID)src)); else spew("%-11s$0x%x, %s, %s", name, imm, XMMRegName(src), GPReg32Name(dst)); - m_formatter.threeByteOpVex(ty, opcode, escape, (RegisterID)src, X86Registers::invalid_xmm, dst); + m_formatter.threeByteOpVex(ty, opcode, escape, (RegisterID)src, invalid_xmm, dst); m_formatter.immediate8u(imm); } @@ -4549,7 +3912,7 @@ private: } spew("%-11s$0x%x, " MEM_ob ", %s", name, imm, ADDR_ob(offset, base), GPReg32Name(dst)); - m_formatter.threeByteOpVex(ty, opcode, escape, offset, base, X86Registers::invalid_xmm, dst); + m_formatter.threeByteOpVex(ty, opcode, escape, offset, base, invalid_xmm, dst); m_formatter.immediate8u(imm); } @@ -4561,14 +3924,14 @@ private: spew("blendvps %s, %s", XMMRegName(rm), XMMRegName(dst)); // Even though a "ps" instruction, vblendv is encoded with the "pd" prefix. m_formatter.legacySSEPrefix(VEX_PD); - m_formatter.threeByteOp(OP3_BLENDVPS_VdqWdq, ESCAPE_BLENDVPS, (RegisterID)rm, dst); + m_formatter.threeByteOp(OP3_BLENDVPS_VdqWdq, ESCAPE_3A, (RegisterID)rm, dst); return; } spew("vblendvps %s, %s, %s, %s", XMMRegName(mask), XMMRegName(rm), XMMRegName(src0), XMMRegName(dst)); // Even though a "ps" instruction, vblendv is encoded with the "pd" prefix. - m_formatter.vblendvOpVex(VEX_PD, OP3_VBLENDVPS_VdqWdq, ESCAPE_VBLENDVPS, + m_formatter.vblendvOpVex(VEX_PD, OP3_VBLENDVPS_VdqWdq, ESCAPE_3A, mask, (RegisterID)rm, src0, dst); } @@ -4578,14 +3941,14 @@ private: spew("blendvps " MEM_ob ", %s", ADDR_ob(offset, base), XMMRegName(dst)); // Even though a "ps" instruction, vblendv is encoded with the "pd" prefix. m_formatter.legacySSEPrefix(VEX_PD); - m_formatter.threeByteOp(OP3_BLENDVPS_VdqWdq, ESCAPE_BLENDVPS, offset, base, dst); + m_formatter.threeByteOp(OP3_BLENDVPS_VdqWdq, ESCAPE_3A, offset, base, dst); return; } spew("vblendvps %s, " MEM_ob ", %s, %s", XMMRegName(mask), ADDR_ob(offset, base), XMMRegName(src0), XMMRegName(dst)); // Even though a "ps" instruction, vblendv is encoded with the "pd" prefix. - m_formatter.vblendvOpVex(VEX_PD, OP3_VBLENDVPS_VdqWdq, ESCAPE_VBLENDVPS, + m_formatter.vblendvOpVex(VEX_PD, OP3_VBLENDVPS_VdqWdq, ESCAPE_3A, mask, offset, base, src0, dst); } @@ -4605,15 +3968,8 @@ private: m_formatter.immediate8u(imm); } - static int32_t getInt32(const void* where) - { - return static_cast(where)[-1]; - } - class X86InstructionFormatter { - static const int maxInstructionSize = 16; - public: // Legacy prefix bytes: // @@ -4652,20 +4008,20 @@ private: void oneByteOp(OneByteOpcodeID opcode) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); m_buffer.putByteUnchecked(opcode); } void oneByteOp(OneByteOpcodeID opcode, RegisterID reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(0, 0, reg); m_buffer.putByteUnchecked(opcode + (reg & 7)); } void oneByteOp(OneByteOpcodeID opcode, RegisterID rm, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, rm); m_buffer.putByteUnchecked(opcode); registerModRM(rm, reg); @@ -4673,7 +4029,7 @@ private: void oneByteOp(OneByteOpcodeID opcode, int32_t offset, RegisterID base, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, base); m_buffer.putByteUnchecked(opcode); memoryModRM(offset, base, reg); @@ -4681,7 +4037,7 @@ private: void oneByteOp_disp32(OneByteOpcodeID opcode, int32_t offset, RegisterID base, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, base); m_buffer.putByteUnchecked(opcode); memoryModRM_disp32(offset, base, reg); @@ -4689,7 +4045,7 @@ private: void oneByteOp(OneByteOpcodeID opcode, int32_t offset, RegisterID base, RegisterID index, int scale, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, index, base); m_buffer.putByteUnchecked(opcode); memoryModRM(offset, base, index, scale, reg); @@ -4697,7 +4053,7 @@ private: void oneByteOp_disp32(OneByteOpcodeID opcode, int32_t offset, RegisterID index, int scale, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, index, 0); m_buffer.putByteUnchecked(opcode); memoryModRM_disp32(offset, index, scale, reg); @@ -4705,7 +4061,7 @@ private: void oneByteOp(OneByteOpcodeID opcode, const void* address, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, 0); m_buffer.putByteUnchecked(opcode); memoryModRM_disp32(address, reg); @@ -4713,7 +4069,7 @@ private: void oneByteOp_disp32(OneByteOpcodeID opcode, const void* address, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, 0); m_buffer.putByteUnchecked(opcode); memoryModRM_disp32(address, reg); @@ -4721,7 +4077,7 @@ private: #ifdef JS_CODEGEN_X64 void oneByteRipOp(OneByteOpcodeID opcode, int ripOffset, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, 0); m_buffer.putByteUnchecked(opcode); putModRm(ModRmMemoryNoDisp, noBase, reg); @@ -4730,7 +4086,7 @@ private: void oneByteRipOp64(OneByteOpcodeID opcode, int ripOffset, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexW(reg, 0, 0); m_buffer.putByteUnchecked(opcode); putModRm(ModRmMemoryNoDisp, noBase, reg); @@ -4739,7 +4095,7 @@ private: void twoByteRipOp(TwoByteOpcodeID opcode, int ripOffset, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, 0); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(opcode); @@ -4761,14 +4117,14 @@ private: void twoByteOp(TwoByteOpcodeID opcode) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(opcode); } void twoByteOp(TwoByteOpcodeID opcode, RegisterID rm, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, rm); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(opcode); @@ -4787,7 +4143,7 @@ private: void twoByteOp(TwoByteOpcodeID opcode, int32_t offset, RegisterID base, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, base); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(opcode); @@ -4806,7 +4162,7 @@ private: void twoByteOp_disp32(TwoByteOpcodeID opcode, int32_t offset, RegisterID base, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, base); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(opcode); @@ -4825,7 +4181,7 @@ private: void twoByteOp(TwoByteOpcodeID opcode, int32_t offset, RegisterID base, RegisterID index, int scale, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, index, base); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(opcode); @@ -4845,7 +4201,7 @@ private: void twoByteOp(TwoByteOpcodeID opcode, const void* address, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, 0); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(opcode); @@ -4864,7 +4220,7 @@ private: void threeByteOp(ThreeByteOpcodeID opcode, ThreeByteEscape escape, RegisterID rm, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, rm); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(escape); @@ -4878,8 +4234,8 @@ private: int r = (reg >> 3), x = 0, b = (rm >> 3); int m = 0, w = 0, v = src0, l = 0; switch (escape) { - case 0x38: m = 2; break; // 0x0F 0x38 - case 0x3A: m = 3; break; // 0x0F 0x3A + case ESCAPE_38: m = 2; break; + case ESCAPE_3A: m = 3; break; default: MOZ_CRASH("unexpected escape"); } threeOpVex(ty, r, x, b, m, w, v, l, opcode); @@ -4888,7 +4244,7 @@ private: void threeByteOp(ThreeByteOpcodeID opcode, ThreeByteEscape escape, int32_t offset, RegisterID base, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, base); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(escape); @@ -4902,8 +4258,8 @@ private: int r = (reg >> 3), x = 0, b = (base >> 3); int m = 0, w = 0, v = src0, l = 0; switch (escape) { - case 0x38: m = 2; break; // 0x0F 0x38 - case 0x3A: m = 3; break; // 0x0F 0x3A + case ESCAPE_38: m = 2; break; + case ESCAPE_3A: m = 3; break; default: MOZ_CRASH("unexpected escape"); } threeOpVex(ty, r, x, b, m, w, v, l, opcode); @@ -4912,7 +4268,7 @@ private: void threeByteOp(ThreeByteOpcodeID opcode, ThreeByteEscape escape, const void* address, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexIfNeeded(reg, 0, 0); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(escape); @@ -4926,8 +4282,8 @@ private: int r = (reg >> 3), x = 0, b = 0; int m = 0, w = 0, v = src0, l = 0; switch (escape) { - case 0x38: m = 2; break; // 0x0F 0x38 - case 0x3A: m = 3; break; // 0x0F 0x3A + case ESCAPE_38: m = 2; break; + case ESCAPE_3A: m = 3; break; default: MOZ_CRASH("unexpected escape"); } threeOpVex(ty, r, x, b, m, w, v, l, opcode); @@ -4940,8 +4296,8 @@ private: int r = (reg >> 3), x = 0, b = (rm >> 3); int m = 0, w = 0, v = src0, l = 0; switch (escape) { - case 0x38: m = 2; break; // 0x0F 0x38 - case 0x3A: m = 3; break; // 0x0F 0x3A + case ESCAPE_38: m = 2; break; + case ESCAPE_3A: m = 3; break; default: MOZ_CRASH("unexpected escape"); } threeOpVex(ty, r, x, b, m, w, v, l, opcode); @@ -4955,8 +4311,8 @@ private: int r = (reg >> 3), x = 0, b = (base >> 3); int m = 0, w = 0, v = src0, l = 0; switch (escape) { - case 0x38: m = 2; break; // 0x0F 0x38 - case 0x3A: m = 3; break; // 0x0F 0x3A + case ESCAPE_38: m = 2; break; + case ESCAPE_3A: m = 3; break; default: MOZ_CRASH("unexpected escape"); } threeOpVex(ty, r, x, b, m, w, v, l, opcode); @@ -4973,21 +4329,21 @@ private: void oneByteOp64(OneByteOpcodeID opcode) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexW(0, 0, 0); m_buffer.putByteUnchecked(opcode); } void oneByteOp64(OneByteOpcodeID opcode, RegisterID reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexW(0, 0, reg); m_buffer.putByteUnchecked(opcode + (reg & 7)); } void oneByteOp64(OneByteOpcodeID opcode, RegisterID rm, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexW(reg, 0, rm); m_buffer.putByteUnchecked(opcode); registerModRM(rm, reg); @@ -4995,7 +4351,7 @@ private: void oneByteOp64(OneByteOpcodeID opcode, int32_t offset, RegisterID base, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexW(reg, 0, base); m_buffer.putByteUnchecked(opcode); memoryModRM(offset, base, reg); @@ -5003,7 +4359,7 @@ private: void oneByteOp64_disp32(OneByteOpcodeID opcode, int32_t offset, RegisterID base, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexW(reg, 0, base); m_buffer.putByteUnchecked(opcode); memoryModRM_disp32(offset, base, reg); @@ -5011,7 +4367,7 @@ private: void oneByteOp64(OneByteOpcodeID opcode, int32_t offset, RegisterID base, RegisterID index, int scale, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexW(reg, index, base); m_buffer.putByteUnchecked(opcode); memoryModRM(offset, base, index, scale, reg); @@ -5019,7 +4375,7 @@ private: void oneByteOp64(OneByteOpcodeID opcode, const void* address, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexW(reg, 0, 0); m_buffer.putByteUnchecked(opcode); memoryModRM(address, reg); @@ -5027,7 +4383,7 @@ private: void twoByteOp64(TwoByteOpcodeID opcode, RegisterID rm, int reg) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); emitRexW(reg, 0, rm); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(opcode); @@ -5058,36 +4414,36 @@ private: // byte of the second four registers (spl..dil). // // Address operands should still be checked using regRequiresRex(), - // while ByteRegRequiresRex() is provided to check byte register + // while byteRegRequiresRex() is provided to check byte register // operands. void oneByteOp8(OneByteOpcodeID opcode) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); m_buffer.putByteUnchecked(opcode); } void oneByteOp8(OneByteOpcodeID opcode, RegisterID rm, GroupOpcodeID groupOp) { - m_buffer.ensureSpace(maxInstructionSize); - emitRexIf(X86Registers::ByteRegRequiresRex(rm), 0, 0, rm); + m_buffer.ensureSpace(MaxInstructionSize); + emitRexIf(byteRegRequiresRex(rm), 0, 0, rm); m_buffer.putByteUnchecked(opcode); registerModRM(rm, groupOp); } // Like oneByteOp8, but never emits a REX prefix. - void oneByteOp8_norex(OneByteOpcodeID opcode, RegisterID rm, GroupOpcodeID groupOp) + void oneByteOp8_norex(OneByteOpcodeID opcode, HRegisterID rm, GroupOpcodeID groupOp) { - MOZ_ASSERT(!regRequiresRex(rm)); - m_buffer.ensureSpace(maxInstructionSize); + MOZ_ASSERT(!regRequiresRex(RegisterID(rm))); + m_buffer.ensureSpace(MaxInstructionSize); m_buffer.putByteUnchecked(opcode); - registerModRM(rm, groupOp); + registerModRM(RegisterID(rm), groupOp); } void oneByteOp8(OneByteOpcodeID opcode, int32_t offset, RegisterID base, RegisterID reg) { - m_buffer.ensureSpace(maxInstructionSize); - emitRexIf(X86Registers::ByteRegRequiresRex(reg), reg, 0, base); + m_buffer.ensureSpace(MaxInstructionSize); + emitRexIf(byteRegRequiresRex(reg), reg, 0, base); m_buffer.putByteUnchecked(opcode); memoryModRM(offset, base, reg); } @@ -5095,8 +4451,8 @@ private: void oneByteOp8_disp32(OneByteOpcodeID opcode, int32_t offset, RegisterID base, RegisterID reg) { - m_buffer.ensureSpace(maxInstructionSize); - emitRexIf(X86Registers::ByteRegRequiresRex(reg), reg, 0, base); + m_buffer.ensureSpace(MaxInstructionSize); + emitRexIf(byteRegRequiresRex(reg), reg, 0, base); m_buffer.putByteUnchecked(opcode); memoryModRM_disp32(offset, base, reg); } @@ -5104,24 +4460,24 @@ private: void oneByteOp8(OneByteOpcodeID opcode, int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID reg) { - m_buffer.ensureSpace(maxInstructionSize); - emitRexIf(X86Registers::ByteRegRequiresRex(reg), reg, index, base); + m_buffer.ensureSpace(MaxInstructionSize); + emitRexIf(byteRegRequiresRex(reg), reg, index, base); m_buffer.putByteUnchecked(opcode); memoryModRM(offset, base, index, scale, reg); } void oneByteOp8(OneByteOpcodeID opcode, const void* address, RegisterID reg) { - m_buffer.ensureSpace(maxInstructionSize); - emitRexIf(X86Registers::ByteRegRequiresRex(reg), reg, 0, 0); + m_buffer.ensureSpace(MaxInstructionSize); + emitRexIf(byteRegRequiresRex(reg), reg, 0, 0); m_buffer.putByteUnchecked(opcode); memoryModRM_disp32(address, reg); } void twoByteOp8(TwoByteOpcodeID opcode, RegisterID rm, RegisterID reg) { - m_buffer.ensureSpace(maxInstructionSize); - emitRexIf(X86Registers::ByteRegRequiresRex(reg)|X86Registers::ByteRegRequiresRex(rm), reg, 0, rm); + m_buffer.ensureSpace(MaxInstructionSize); + emitRexIf(byteRegRequiresRex(reg)|byteRegRequiresRex(rm), reg, 0, rm); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(opcode); registerModRM(rm, reg); @@ -5133,8 +4489,8 @@ private: // prefix to disambiguate it from ah..bh. void twoByteOp8_movx(TwoByteOpcodeID opcode, RegisterID rm, RegisterID reg) { - m_buffer.ensureSpace(maxInstructionSize); - emitRexIf(regRequiresRex(reg)|X86Registers::ByteRegRequiresRex(rm), reg, 0, rm); + m_buffer.ensureSpace(MaxInstructionSize); + emitRexIf(regRequiresRex(reg)|byteRegRequiresRex(rm), reg, 0, rm); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(opcode); registerModRM(rm, reg); @@ -5142,8 +4498,8 @@ private: void twoByteOp8(TwoByteOpcodeID opcode, RegisterID rm, GroupOpcodeID groupOp) { - m_buffer.ensureSpace(maxInstructionSize); - emitRexIf(X86Registers::ByteRegRequiresRex(rm), 0, 0, rm); + m_buffer.ensureSpace(MaxInstructionSize); + emitRexIf(byteRegRequiresRex(rm), 0, 0, rm); m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE); m_buffer.putByteUnchecked(opcode); registerModRM(rm, groupOp); @@ -5274,19 +4630,28 @@ private: // Internals; ModRm and REX formatters. - static const RegisterID noBase = X86Registers::ebp; - static const RegisterID hasSib = X86Registers::esp; - static const RegisterID noIndex = X86Registers::esp; -#ifdef JS_CODEGEN_X64 - static const RegisterID noBase2 = X86Registers::r13; - static const RegisterID hasSib2 = X86Registers::r12; - - // Registers r8 & above require a REX prefixe. - bool regRequiresRex(int reg) + // Byte operand register spl & above requir a REX prefix, which precludes + // use of the h registers in the same instruction. + static bool byteRegRequiresRex(RegisterID reg) { - return (reg >= X86Registers::r8); +#ifdef JS_CODEGEN_X64 + return reg >= rsp; +#else + return false; +#endif } + // For non-byte sizes, registers r8 & above always require a REX prefix. + static bool regRequiresRex(RegisterID reg) + { +#ifdef JS_CODEGEN_X64 + return reg >= r8; +#else + return false; +#endif + } + +#ifdef JS_CODEGEN_X64 // Format a REX prefix byte. void emitRex(bool w, int r, int x, int b) { @@ -5299,7 +4664,7 @@ private: emitRex(true, r, x, b); } - // Used for operations with byte operands - use ByteRegRequiresRex() to + // Used for operations with byte operands - use byteRegRequiresRex() to // check register operands, regRequiresRex() to check other registers // (i.e. address base & index). // @@ -5308,19 +4673,23 @@ private: // oneByteOp8 functionality such that r, x, and b can all be used. void emitRexIf(bool condition, int r, int x, int b) { - if (condition || regRequiresRex(r) || regRequiresRex(x) || regRequiresRex(b)) + if (condition || + regRequiresRex(RegisterID(r)) || + regRequiresRex(RegisterID(x)) || + regRequiresRex(RegisterID(b))) + { emitRex(false, r, x, b); + } } // Used for word sized operations, will plant a REX prefix if necessary // (if any register is r8 or above). void emitRexIfNeeded(int r, int x, int b) { - emitRexIf(regRequiresRex(r) || regRequiresRex(x) || regRequiresRex(b), r, x, b); + emitRexIf(false, r, x, b); } #else // No REX prefix bytes on 32-bit x86. - bool regRequiresRex(int) { return false; } void emitRexIf(bool condition, int, int, int) { MOZ_ASSERT(!condition, "32-bit x86 should never use a REX prefix"); @@ -5328,13 +4697,6 @@ private: void emitRexIfNeeded(int, int, int) {} #endif - enum ModRmMode { - ModRmMemoryNoDisp, - ModRmMemoryDisp8, - ModRmMemoryDisp32, - ModRmRegister - }; - void putModRm(ModRmMode mode, RegisterID rm, int reg) { m_buffer.putByteUnchecked((mode << 6) | ((reg & 7) << 3) | (rm & 7)); @@ -5450,7 +4812,7 @@ private: void memoryModRM_disp32(const void* address, int reg) { - int32_t disp = addressImmediate(address); + int32_t disp = AddressImmediate(address); #ifdef JS_CODEGEN_X64 // On x64-64, non-RIP-relative absolute mode requires a SIB. @@ -5470,9 +4832,9 @@ private: void threeOpVex(VexOperandType p, int r, int x, int b, int m, int w, int v, int l, int opcode) { - m_buffer.ensureSpace(maxInstructionSize); + m_buffer.ensureSpace(MaxInstructionSize); - if (v == X86Registers::invalid_xmm) + if (v == invalid_xmm) v = XMMRegisterID(0); if (x == 0 && b == 0 && m == 1 && w == 0) { @@ -5495,6 +4857,8 @@ private: bool useVEX_; }; +} // namespace X86Encoding + } // namespace jit } // namespace js diff --git a/js/src/jit/shared/CodeGenerator-x86-shared.cpp b/js/src/jit/shared/CodeGenerator-x86-shared.cpp index 461df0f66c2d..61486cb4af4f 100644 --- a/js/src/jit/shared/CodeGenerator-x86-shared.cpp +++ b/js/src/jit/shared/CodeGenerator-x86-shared.cpp @@ -1601,7 +1601,7 @@ CodeGeneratorX86Shared::visitFloor(LFloor *lir) bailoutFrom(&bailout, lir->snapshot()); // Round toward -Infinity. - masm.vroundsd(X86Assembler::RoundDown, input, scratch, scratch); + masm.vroundsd(X86Encoding::RoundDown, input, scratch, scratch); bailoutCvttsd2si(scratch, output, lir->snapshot()); } else { @@ -1658,7 +1658,7 @@ CodeGeneratorX86Shared::visitFloorF(LFloorF *lir) bailoutFrom(&bailout, lir->snapshot()); // Round toward -Infinity. - masm.vroundss(X86Assembler::RoundDown, input, scratch, scratch); + masm.vroundss(X86Encoding::RoundDown, input, scratch, scratch); bailoutCvttss2si(scratch, output, lir->snapshot()); } else { @@ -1723,7 +1723,7 @@ CodeGeneratorX86Shared::visitCeil(LCeil *lir) // x <= -1 or x > -0 masm.bind(&lessThanMinusOne); // Round toward +Infinity. - masm.vroundsd(X86Assembler::RoundUp, input, scratch, scratch); + masm.vroundsd(X86Encoding::RoundUp, input, scratch, scratch); bailoutCvttsd2si(scratch, output, lir->snapshot()); return; } @@ -1775,7 +1775,7 @@ CodeGeneratorX86Shared::visitCeilF(LCeilF *lir) // x <= -1 or x > -0 masm.bind(&lessThanMinusOne); // Round toward +Infinity. - masm.vroundss(X86Assembler::RoundUp, input, scratch, scratch); + masm.vroundss(X86Encoding::RoundUp, input, scratch, scratch); bailoutCvttss2si(scratch, output, lir->snapshot()); return; } @@ -1850,7 +1850,7 @@ CodeGeneratorX86Shared::visitRound(LRound *lir) // Add 0.5 and round toward -Infinity. The result is stored in the temp // register (currently contains 0.5). masm.addDouble(input, temp); - masm.vroundsd(X86Assembler::RoundDown, temp, scratch, scratch); + masm.vroundsd(X86Encoding::RoundDown, temp, scratch, scratch); // Truncate. bailoutCvttsd2si(scratch, output, lir->snapshot()); @@ -1933,7 +1933,7 @@ CodeGeneratorX86Shared::visitRoundF(LRoundF *lir) // Add 0.5 and round toward -Infinity. The result is stored in the temp // register (currently contains 0.5). masm.addFloat32(input, temp); - masm.vroundss(X86Assembler::RoundDown, temp, scratch, scratch); + masm.vroundss(X86Encoding::RoundDown, temp, scratch, scratch); // Truncate. bailoutCvttss2si(scratch, output, lir->snapshot()); diff --git a/js/src/jit/shared/Constants-x86-shared.h b/js/src/jit/shared/Constants-x86-shared.h new file mode 100644 index 000000000000..aff6a1d8c68d --- /dev/null +++ b/js/src/jit/shared/Constants-x86-shared.h @@ -0,0 +1,222 @@ +/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*- + * vim: set ts=8 sts=4 et sw=4 tw=99: + * This Source Code Form is subject to the terms of the Mozilla Public + * License, v. 2.0. If a copy of the MPL was not distributed with this + * file, You can obtain one at http://mozilla.org/MPL/2.0/. */ + +#ifndef jit_shared_Constants_x86_shared_h +#define jit_shared_Constants_x86_shared_h + +namespace js { +namespace jit { + +namespace X86Encoding { + +enum RegisterID { + rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi +#ifdef JS_CODEGEN_X64 + ,r8, r9, r10, r11, r12, r13, r14, r15 +#endif + ,invalid_reg +}; + +enum HRegisterID { + ah = rsp, + ch = rbp, + dh = rsi, + bh = rdi +}; + +enum XMMRegisterID { + xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7 +#ifdef JS_CODEGEN_X64 + ,xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 +#endif + ,invalid_xmm +}; + +inline const char *XMMRegName(XMMRegisterID reg) +{ + static const char *const names[] = { + "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7" +#ifdef JS_CODEGEN_X64 + ,"%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15" +#endif + }; + MOZ_ASSERT(size_t(reg) < mozilla::ArrayLength(names)); + return names[reg]; +} + +#ifdef JS_CODEGEN_X64 +inline const char *GPReg64Name(RegisterID reg) +{ + static const char *const names[] = { + "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi" +#ifdef JS_CODEGEN_X64 + ,"%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" +#endif + }; + MOZ_ASSERT(size_t(reg) < mozilla::ArrayLength(names)); + return names[reg]; +} +#endif + +inline const char *GPReg32Name(RegisterID reg) +{ + static const char *const names[] = { + "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi" +#ifdef JS_CODEGEN_X64 + ,"%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" +#endif + }; + MOZ_ASSERT(size_t(reg) < mozilla::ArrayLength(names)); + return names[reg]; +} + +inline const char *GPReg16Name(RegisterID reg) +{ + static const char *const names[] = { + "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di" +#ifdef JS_CODEGEN_X64 + ,"%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" +#endif + }; + MOZ_ASSERT(size_t(reg) < mozilla::ArrayLength(names)); + return names[reg]; +} + +inline const char *GPReg8Name(RegisterID reg) +{ + static const char *const names[] = { + "%al", "%cl", "%dl", "%bl" +#ifdef JS_CODEGEN_X64 + ,"%spl", "%bpl", "%sil", "%dil", + "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" +#endif + }; + MOZ_ASSERT(size_t(reg) < mozilla::ArrayLength(names)); + return names[reg]; +} + +inline const char *GPRegName(RegisterID reg) +{ +#ifdef JS_CODEGEN_X64 + return GPReg64Name(reg); +#else + return GPReg32Name(reg); +#endif +} + +inline bool HasSubregL(RegisterID reg) +{ +#ifdef JS_CODEGEN_X64 + // In 64-bit mode, all registers have an 8-bit lo subreg. + return true; +#else + // In 32-bit mode, only the first four registers do. + return reg <= rbx; +#endif +} + +inline bool HasSubregH(RegisterID reg) +{ + // The first four registers always have h registers. However, note that + // on x64, h registers may not be used in instructions using REX + // prefixes. Also note that this may depend on what other registers are + // used! + return reg <= rbx; +} + +inline HRegisterID GetSubregH(RegisterID reg) +{ + MOZ_ASSERT(HasSubregH(reg)); + return HRegisterID(reg + 4); +} + +inline const char *HRegName8(HRegisterID reg) +{ + static const char *const names[] = { + "%ah", "%ch", "%dh", "%bh" + }; + size_t index = reg - GetSubregH(rax); + MOZ_ASSERT(index < mozilla::ArrayLength(names)); + return names[index]; +} + +enum Condition { + ConditionO, + ConditionNO, + ConditionB, + ConditionAE, + ConditionE, + ConditionNE, + ConditionBE, + ConditionA, + ConditionS, + ConditionNS, + ConditionP, + ConditionNP, + ConditionL, + ConditionGE, + ConditionLE, + ConditionG, + + ConditionC = ConditionB, + ConditionNC = ConditionAE +}; + +inline const char *CCName(Condition cc) +{ + static const char *const names[] = { + "o ", "no", "b ", "ae", "e ", "ne", "be", "a ", + "s ", "ns", "p ", "np", "l ", "ge", "le", "g " + }; + MOZ_ASSERT(size_t(cc) < mozilla::ArrayLength(names)); + return names[cc]; +} + +// Conditions for CMP instructions (CMPSS, CMPSD, CMPPS, CMPPD, etc). +enum ConditionCmp { + ConditionCmp_EQ = 0x0, + ConditionCmp_LT = 0x1, + ConditionCmp_LE = 0x2, + ConditionCmp_UNORD = 0x3, + ConditionCmp_NEQ = 0x4, + ConditionCmp_NLT = 0x5, + ConditionCmp_NLE = 0x6, + ConditionCmp_ORD = 0x7, +}; + +// Rounding modes for ROUNDSD. +enum RoundingMode { + RoundToNearest = 0x0, + RoundDown = 0x1, + RoundUp = 0x2, + RoundToZero = 0x3 +}; + +// Test whether the given address will fit in an address immediate field. +// This is always true on x86, but on x64 it's only true for addreses which +// fit in the 32-bit immediate field. +inline bool IsAddressImmediate(const void *address) +{ + intptr_t value = reinterpret_cast(address); + int32_t immediate = static_cast(value); + return value == immediate; +} + +// Convert the given address to a 32-bit immediate field value. This is a +// no-op on x86, but on x64 it asserts that the address is actually a valid +// address immediate. +inline int32_t AddressImmediate(const void *address) +{ + MOZ_ASSERT(IsAddressImmediate(address)); + return static_cast(reinterpret_cast(address)); +} + +} // namespace X86Encoding + +} // namespace jit +} // namespace js + +#endif /* jit_shared_Constants_x86_shared_h */ diff --git a/js/src/jit/shared/Encoding-x86-shared.h b/js/src/jit/shared/Encoding-x86-shared.h new file mode 100644 index 000000000000..a513fbd4e0fb --- /dev/null +++ b/js/src/jit/shared/Encoding-x86-shared.h @@ -0,0 +1,317 @@ +/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*- + * vim: set ts=8 sts=4 et sw=4 tw=99: + * This Source Code Form is subject to the terms of the Mozilla Public + * License, v. 2.0. If a copy of the MPL was not distributed with this + * file, You can obtain one at http://mozilla.org/MPL/2.0/. */ + +#ifndef jit_shared_Encoding_x86_shared_h +#define jit_shared_Encoding_x86_shared_h + +#include "jit/shared/Constants-x86-shared.h" + +namespace js { +namespace jit { + +namespace X86Encoding { + +static const size_t MaxInstructionSize = 16; + +enum OneByteOpcodeID { + OP_ADD_EbGb = 0x00, + OP_ADD_EvGv = 0x01, + OP_ADD_GvEv = 0x03, + OP_ADD_EAXIv = 0x05, + OP_OR_EbGb = 0x08, + OP_OR_EvGv = 0x09, + OP_OR_GvEv = 0x0B, + OP_OR_EAXIv = 0x0D, + OP_2BYTE_ESCAPE = 0x0F, + OP_AND_EbGb = 0x20, + OP_AND_EvGv = 0x21, + OP_AND_GvEv = 0x23, + OP_AND_EAXIv = 0x25, + OP_SUB_EbGb = 0x28, + OP_SUB_EvGv = 0x29, + OP_SUB_GvEv = 0x2B, + OP_SUB_EAXIv = 0x2D, + PRE_PREDICT_BRANCH_NOT_TAKEN = 0x2E, + OP_XOR_EbGb = 0x30, + OP_XOR_EvGv = 0x31, + OP_XOR_GvEv = 0x33, + OP_XOR_EAXIv = 0x35, + OP_CMP_EvGv = 0x39, + OP_CMP_GvEv = 0x3B, + OP_CMP_EAXIv = 0x3D, +#ifdef JS_CODEGEN_X64 + PRE_REX = 0x40, +#endif + OP_PUSH_EAX = 0x50, + OP_POP_EAX = 0x58, +#ifdef JS_CODEGEN_X86 + OP_PUSHA = 0x60, + OP_POPA = 0x61, +#endif +#ifdef JS_CODEGEN_X64 + OP_MOVSXD_GvEv = 0x63, +#endif + PRE_OPERAND_SIZE = 0x66, + PRE_SSE_66 = 0x66, + OP_PUSH_Iz = 0x68, + OP_IMUL_GvEvIz = 0x69, + OP_PUSH_Ib = 0x6a, + OP_IMUL_GvEvIb = 0x6b, + OP_JCC_rel8 = 0x70, + OP_GROUP1_EbIb = 0x80, + OP_GROUP1_EvIz = 0x81, + OP_GROUP1_EvIb = 0x83, + OP_TEST_EbGb = 0x84, + OP_TEST_EvGv = 0x85, + OP_XCHG_GvEv = 0x87, + OP_MOV_EbGv = 0x88, + OP_MOV_EvGv = 0x89, + OP_MOV_GvEb = 0x8A, + OP_MOV_GvEv = 0x8B, + OP_LEA = 0x8D, + OP_GROUP1A_Ev = 0x8F, + OP_NOP = 0x90, + OP_PUSHFLAGS = 0x9C, + OP_POPFLAGS = 0x9D, + OP_CDQ = 0x99, + OP_MOV_EAXOv = 0xA1, + OP_MOV_OvEAX = 0xA3, + OP_TEST_EAXIb = 0xA8, + OP_TEST_EAXIv = 0xA9, + OP_MOV_EAXIv = 0xB8, + OP_GROUP2_EvIb = 0xC1, + OP_RET_Iz = 0xC2, + PRE_VEX_C4 = 0xC4, + PRE_VEX_C5 = 0xC5, + OP_RET = 0xC3, + OP_GROUP11_EvIb = 0xC6, + OP_GROUP11_EvIz = 0xC7, + OP_INT3 = 0xCC, + OP_GROUP2_Ev1 = 0xD1, + OP_GROUP2_EvCL = 0xD3, + OP_FPU6 = 0xDD, + OP_FPU6_F32 = 0xD9, + OP_CALL_rel32 = 0xE8, + OP_JMP_rel32 = 0xE9, + OP_JMP_rel8 = 0xEB, + PRE_LOCK = 0xF0, + PRE_SSE_F2 = 0xF2, + PRE_SSE_F3 = 0xF3, + OP_HLT = 0xF4, + OP_GROUP3_EbIb = 0xF6, + OP_GROUP3_Ev = 0xF7, + OP_GROUP3_EvIz = 0xF7, // OP_GROUP3_Ev has an immediate, when instruction is a test. + OP_GROUP5_Ev = 0xFF +}; + +enum class ShiftID { + vpsrld = 2, + vpsrlq = 2, + vpsrldq = 3, + vpsrad = 4, + vpslld = 6, + vpsllq = 6 +}; + +enum TwoByteOpcodeID { + OP2_UD2 = 0x0B, + OP2_MOVSD_VsdWsd = 0x10, + OP2_MOVPS_VpsWps = 0x10, + OP2_MOVSD_WsdVsd = 0x11, + OP2_MOVPS_WpsVps = 0x11, + OP2_MOVHLPS_VqUq = 0x12, + OP2_MOVSLDUP_VpsWps = 0x12, + OP2_UNPCKLPS_VsdWsd = 0x14, + OP2_UNPCKHPS_VsdWsd = 0x15, + OP2_MOVLHPS_VqUq = 0x16, + OP2_MOVSHDUP_VpsWps = 0x16, + OP2_MOVAPD_VsdWsd = 0x28, + OP2_MOVAPS_VsdWsd = 0x28, + OP2_MOVAPS_WsdVsd = 0x29, + OP2_CVTSI2SD_VsdEd = 0x2A, + OP2_CVTTSD2SI_GdWsd = 0x2C, + OP2_UCOMISD_VsdWsd = 0x2E, + OP2_MOVMSKPD_EdVd = 0x50, + OP2_ANDPS_VpsWps = 0x54, + OP2_ANDNPS_VpsWps = 0x55, + OP2_ORPS_VpsWps = 0x56, + OP2_XORPS_VpsWps = 0x57, + OP2_ADDSD_VsdWsd = 0x58, + OP2_ADDPS_VpsWps = 0x58, + OP2_MULSD_VsdWsd = 0x59, + OP2_MULPS_VpsWps = 0x59, + OP2_CVTSS2SD_VsdEd = 0x5A, + OP2_CVTSD2SS_VsdEd = 0x5A, + OP2_CVTTPS2DQ_VdqWps = 0x5B, + OP2_CVTDQ2PS_VpsWdq = 0x5B, + OP2_SUBSD_VsdWsd = 0x5C, + OP2_SUBPS_VpsWps = 0x5C, + OP2_MINSD_VsdWsd = 0x5D, + OP2_MINSS_VssWss = 0x5D, + OP2_MINPS_VpsWps = 0x5D, + OP2_DIVSD_VsdWsd = 0x5E, + OP2_DIVPS_VpsWps = 0x5E, + OP2_MAXSD_VsdWsd = 0x5F, + OP2_MAXSS_VssWss = 0x5F, + OP2_MAXPS_VpsWps = 0x5F, + OP2_SQRTSD_VsdWsd = 0x51, + OP2_SQRTSS_VssWss = 0x51, + OP2_SQRTPS_VpsWps = 0x51, + OP2_RSQRTPS_VpsWps = 0x52, + OP2_RCPPS_VpsWps = 0x53, + OP2_ANDPD_VpdWpd = 0x54, + OP2_ORPD_VpdWpd = 0x56, + OP2_XORPD_VpdWpd = 0x57, + OP2_PCMPGTD_VdqWdq = 0x66, + OP2_MOVD_VdEd = 0x6E, + OP2_MOVDQ_VsdWsd = 0x6F, + OP2_MOVDQ_VdqWdq = 0x6F, + OP2_PSHUFD_VdqWdqIb = 0x70, + OP2_PSLLD_UdqIb = 0x72, + OP2_PSRAD_UdqIb = 0x72, + OP2_PSRLD_UdqIb = 0x72, + OP2_PSRLDQ_Vd = 0x73, + OP2_PCMPEQW = 0x75, + OP2_PCMPEQD_VdqWdq = 0x76, + OP2_MOVD_EdVd = 0x7E, + OP2_MOVDQ_WdqVdq = 0x7F, + OP2_JCC_rel32 = 0x80, + OP_SETCC = 0x90, + OP_FENCE = 0xAE, + OP2_IMUL_GvEv = 0xAF, + OP2_CMPXCHG_GvEb = 0xB0, + OP2_CMPXCHG_GvEw = 0xB1, + OP2_BSR_GvEv = 0xBD, + OP2_MOVSX_GvEb = 0xBE, + OP2_MOVSX_GvEw = 0xBF, + OP2_MOVZX_GvEb = 0xB6, + OP2_MOVZX_GvEw = 0xB7, + OP2_XADD_EbGb = 0xC0, + OP2_XADD_EvGv = 0xC1, + OP2_CMPPS_VpsWps = 0xC2, + OP2_PEXTRW_GdUdIb = 0xC5, + OP2_SHUFPS_VpsWpsIb = 0xC6, + OP2_PSRLD_VdqWdq = 0xD2, + OP2_PANDDQ_VdqWdq = 0xDB, + OP2_PANDNDQ_VdqWdq = 0xDF, + OP2_PSRAD_VdqWdq = 0xE2, + OP2_PORDQ_VdqWdq = 0xEB, + OP2_PXORDQ_VdqWdq = 0xEF, + OP2_PSLLD_VdqWdq = 0xF2, + OP2_PMULUDQ_VdqWdq = 0xF4, + OP2_PSUBD_VdqWdq = 0xFA, + OP2_PADDD_VdqWdq = 0xFE +}; + +enum ThreeByteOpcodeID { + OP3_ROUNDSS_VsdWsd = 0x0A, + OP3_ROUNDSD_VsdWsd = 0x0B, + OP3_BLENDVPS_VdqWdq = 0x14, + OP3_PEXTRD_EdVdqIb = 0x16, + OP3_BLENDPS_VpsWpsIb = 0x0C, + OP3_PTEST_VdVd = 0x17, + OP3_INSERTPS_VpsUps = 0x21, + OP3_PINSRD_VdqEdIb = 0x22, + OP3_PMULLD_VdqWdq = 0x40, + OP3_VBLENDVPS_VdqWdq = 0x4A +}; + +// Test whether the given opcode should be printed with its operands reversed. +inline bool IsXMMReversedOperands(TwoByteOpcodeID opcode) +{ + switch (opcode) { + case OP2_MOVSD_WsdVsd: // also OP2_MOVPS_WpsVps + case OP2_MOVAPS_WsdVsd: + case OP2_MOVDQ_WdqVdq: + case OP3_PEXTRD_EdVdqIb: + return true; + default: + break; + } + return false; +} + +enum ThreeByteEscape { + ESCAPE_38 = 0x38, + ESCAPE_3A = 0x3A +}; + +enum VexOperandType { + VEX_PS = 0, + VEX_PD = 1, + VEX_SS = 2, + VEX_SD = 3 +}; + +inline OneByteOpcodeID jccRel8(Condition cond) +{ + return OneByteOpcodeID(OP_JCC_rel8 + cond); +} +inline TwoByteOpcodeID jccRel32(Condition cond) +{ + return TwoByteOpcodeID(OP2_JCC_rel32 + cond); +} +inline TwoByteOpcodeID setccOpcode(Condition cond) +{ + return TwoByteOpcodeID(OP_SETCC + cond); +} + +enum GroupOpcodeID { + GROUP1_OP_ADD = 0, + GROUP1_OP_OR = 1, + GROUP1_OP_ADC = 2, + GROUP1_OP_AND = 4, + GROUP1_OP_SUB = 5, + GROUP1_OP_XOR = 6, + GROUP1_OP_CMP = 7, + + GROUP1A_OP_POP = 0, + + GROUP2_OP_SHL = 4, + GROUP2_OP_SHR = 5, + GROUP2_OP_SAR = 7, + + GROUP3_OP_TEST = 0, + GROUP3_OP_NOT = 2, + GROUP3_OP_NEG = 3, + GROUP3_OP_IMUL = 5, + GROUP3_OP_DIV = 6, + GROUP3_OP_IDIV = 7, + + GROUP5_OP_INC = 0, + GROUP5_OP_DEC = 1, + GROUP5_OP_CALLN = 2, + GROUP5_OP_JMPN = 4, + GROUP5_OP_PUSH = 6, + + FPU6_OP_FLD = 0, + FPU6_OP_FISTTP = 1, + FPU6_OP_FSTP = 3, + + GROUP11_MOV = 0 +}; + +static const RegisterID noBase = rbp; +static const RegisterID hasSib = rsp; +static const RegisterID noIndex = rsp; +#ifdef JS_CODEGEN_X64 +static const RegisterID noBase2 = r13; +static const RegisterID hasSib2 = r12; +#endif + +enum ModRmMode { + ModRmMemoryNoDisp, + ModRmMemoryDisp8, + ModRmMemoryDisp32, + ModRmRegister +}; + +} // namespace X86Encoding + +} // namespace jit +} // namespace js + +#endif /* jit_shared_Encoding_x86_shared_h */ diff --git a/js/src/jit/shared/MacroAssembler-x86-shared.h b/js/src/jit/shared/MacroAssembler-x86-shared.h index cb73ca6cbf39..b44629231537 100644 --- a/js/src/jit/shared/MacroAssembler-x86-shared.h +++ b/js/src/jit/shared/MacroAssembler-x86-shared.h @@ -213,17 +213,17 @@ class MacroAssemblerX86Shared : public Assembler } void atomic_cmpxchg8(Register newval, const Operand &addr, Register oldval_and_result) { // %eax must be explicitly provided for calling clarity. - MOZ_ASSERT(oldval_and_result.code() == X86Registers::eax); + MOZ_ASSERT(oldval_and_result.code() == X86Encoding::rax); lock_cmpxchg8(newval, addr); } void atomic_cmpxchg16(Register newval, const Operand &addr, Register oldval_and_result) { // %eax must be explicitly provided for calling clarity. - MOZ_ASSERT(oldval_and_result.code() == X86Registers::eax); + MOZ_ASSERT(oldval_and_result.code() == X86Encoding::rax); lock_cmpxchg16(newval, addr); } void atomic_cmpxchg32(Register newval, const Operand &addr, Register oldval_and_result) { // %eax must be explicitly provided for calling clarity. - MOZ_ASSERT(oldval_and_result.code() == X86Registers::eax); + MOZ_ASSERT(oldval_and_result.code() == X86Encoding::rax); lock_cmpxchg32(newval, addr); } diff --git a/js/src/jit/shared/Patching-x86-shared.h b/js/src/jit/shared/Patching-x86-shared.h new file mode 100644 index 000000000000..f7c065b36ae5 --- /dev/null +++ b/js/src/jit/shared/Patching-x86-shared.h @@ -0,0 +1,137 @@ +/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*- + * vim: set ts=8 sts=4 et sw=4 tw=99: + * This Source Code Form is subject to the terms of the Mozilla Public + * License, v. 2.0. If a copy of the MPL was not distributed with this + * file, You can obtain one at http://mozilla.org/MPL/2.0/. */ + +#ifndef jit_shared_Patching_x86_shared_h +#define jit_shared_Patching_x86_shared_h + +namespace js { +namespace jit { + +namespace X86Encoding { + +inline void * +GetPointer(const void* where) +{ + return reinterpret_cast(where)[-1]; +} + +inline void ** +GetPointerRef(void* where) +{ + return &reinterpret_cast(where)[-1]; +} + +inline void +SetPointer(void* where, const void* value) +{ + reinterpret_cast(where)[-1] = value; +} + +inline int32_t +GetInt32(const void* where) +{ + return reinterpret_cast(where)[-1]; +} + +inline void +SetInt32(void* where, int32_t value) +{ + reinterpret_cast(where)[-1] = value; +} + +inline void +AddInt32(void* where, int32_t value) +{ +#ifdef DEBUG + uint32_t x = reinterpret_cast(where)[-1]; + uint32_t y = x + uint32_t(value); + MOZ_ASSERT(value >= 0 ? (int32_t(y) >= int32_t(x)) : (int32_t(y) < int32_t(x))); +#endif + reinterpret_cast(where)[-1] += uint32_t(value); +} + +inline void +SetRel32(void* from, void* to) +{ + intptr_t offset = reinterpret_cast(to) - reinterpret_cast(from); + MOZ_ASSERT(offset == static_cast(offset), + "offset is too great for a 32-bit relocation"); + if (offset != static_cast(offset)) + MOZ_CRASH("offset is too great for a 32-bit relocation"); + + SetInt32(from, offset); +} + +inline void * +GetRel32Target(void* where) +{ + int32_t rel = GetInt32(where); + return (char *)where + rel; +} + +class JmpSrc { + public: + JmpSrc() + : offset_(-1) + { + } + + explicit JmpSrc(int32_t offset) + : offset_(offset) + { + } + + int32_t offset() const { + return offset_; + } + + bool isSet() const { + return offset_ != -1; + } + + private: + int offset_; +}; + +class JmpDst { + public: + JmpDst() + : offset_(-1) + , used_(false) + { + } + + bool isUsed() const { return used_; } + void used() { used_ = true; } + bool isValid() const { return offset_ != -1; } + + explicit JmpDst(int32_t offset) + : offset_(offset) + , used_(false) + { + MOZ_ASSERT(offset_ == offset); + } + int32_t offset() const { + return offset_; + } + private: + int32_t offset_ : 31; + bool used_ : 1; +}; + +inline bool +CanRelinkJump(void* from, void* to) +{ + intptr_t offset = static_cast(to) - static_cast(from); + return (offset == static_cast(offset)); +} + +} // namespace X86Encoding + +} // namespace jit +} // namespace js + +#endif /* jit_shared_Patching_x86_shared_h */ diff --git a/js/src/jit/x64/Architecture-x64.h b/js/src/jit/x64/Architecture-x64.h index 8087501b3f81..3428503838a9 100644 --- a/js/src/jit/x64/Architecture-x64.h +++ b/js/src/jit/x64/Architecture-x64.h @@ -7,7 +7,7 @@ #ifndef jit_x64_Architecture_x64_h #define jit_x64_Architecture_x64_h -#include "jit/shared/BaseAssembler-x86-shared.h" +#include "jit/shared/Constants-x86-shared.h" namespace js { namespace jit { @@ -26,7 +26,7 @@ static const uint32_t ShadowStackSpace = 0; class Registers { public: - typedef X86Registers::RegisterID Code; + typedef X86Encoding::RegisterID Code; typedef uint32_t SetType; static uint32_t SetSize(SetType x) { static_assert(sizeof(SetType) == 4, "SetType must be 32 bits"); @@ -54,8 +54,8 @@ class Registers { return Invalid; } - static const Code StackPointer = X86Registers::esp; - static const Code Invalid = X86Registers::invalid_reg; + static const Code StackPointer = X86Encoding::rsp; + static const Code Invalid = X86Encoding::invalid_reg; static const uint32_t Total = 16; static const uint32_t TotalPhys = 16; @@ -65,46 +65,46 @@ class Registers { static const uint32_t ArgRegMask = # if !defined(_WIN64) - (1 << X86Registers::edi) | - (1 << X86Registers::esi) | + (1 << X86Encoding::rdi) | + (1 << X86Encoding::rsi) | # endif - (1 << X86Registers::edx) | - (1 << X86Registers::ecx) | - (1 << X86Registers::r8) | - (1 << X86Registers::r9); + (1 << X86Encoding::rdx) | + (1 << X86Encoding::rcx) | + (1 << X86Encoding::r8) | + (1 << X86Encoding::r9); static const uint32_t VolatileMask = - (1 << X86Registers::eax) | - (1 << X86Registers::ecx) | - (1 << X86Registers::edx) | + (1 << X86Encoding::rax) | + (1 << X86Encoding::rcx) | + (1 << X86Encoding::rdx) | # if !defined(_WIN64) - (1 << X86Registers::esi) | - (1 << X86Registers::edi) | + (1 << X86Encoding::rsi) | + (1 << X86Encoding::rdi) | # endif - (1 << X86Registers::r8) | - (1 << X86Registers::r9) | - (1 << X86Registers::r10) | - (1 << X86Registers::r11); + (1 << X86Encoding::r8) | + (1 << X86Encoding::r9) | + (1 << X86Encoding::r10) | + (1 << X86Encoding::r11); static const uint32_t NonVolatileMask = - (1 << X86Registers::ebx) | + (1 << X86Encoding::rbx) | #if defined(_WIN64) - (1 << X86Registers::esi) | - (1 << X86Registers::edi) | + (1 << X86Encoding::rsi) | + (1 << X86Encoding::rdi) | #endif - (1 << X86Registers::ebp) | - (1 << X86Registers::r12) | - (1 << X86Registers::r13) | - (1 << X86Registers::r14) | - (1 << X86Registers::r15); + (1 << X86Encoding::rbp) | + (1 << X86Encoding::r12) | + (1 << X86Encoding::r13) | + (1 << X86Encoding::r14) | + (1 << X86Encoding::r15); static const uint32_t WrapperMask = VolatileMask; static const uint32_t SingleByteRegs = VolatileMask | NonVolatileMask; static const uint32_t NonAllocatableMask = - (1 << X86Registers::esp) | - (1 << X86Registers::r11); // This is ScratchReg. + (1 << X86Encoding::rsp) | + (1 << X86Encoding::r11); // This is ScratchReg. static const uint32_t AllocatableMask = AllMask & ~NonAllocatableMask; @@ -113,11 +113,11 @@ class Registers { // Registers returned from a JS -> JS call. static const uint32_t JSCallMask = - (1 << X86Registers::ecx); + (1 << X86Encoding::rcx); // Registers returned from a JS -> C call. static const uint32_t CallMask = - (1 << X86Registers::eax); + (1 << X86Encoding::rax); }; // Smallest integer type that can hold a register bitmask. @@ -125,14 +125,10 @@ typedef uint16_t PackedRegisterMask; class FloatRegisters { public: - typedef X86Registers::XMMRegisterID Code; + typedef X86Encoding::XMMRegisterID Code; typedef uint32_t SetType; static const char *GetName(Code code) { - static const char * const Names[] = { "xmm0", "xmm1", "xmm2", "xmm3", - "xmm4", "xmm5", "xmm6", "xmm7", - "xmm8", "xmm9", "xmm10", "xmm11", - "xmm12", "xmm13", "xmm14", "xmm15" }; - return Names[code]; + return X86Encoding::XMMRegName(code); } static Code FromName(const char *name) { @@ -143,7 +139,7 @@ class FloatRegisters { return Invalid; } - static const Code Invalid = X86Registers::invalid_xmm; + static const Code Invalid = X86Encoding::invalid_xmm; static const uint32_t Total = 16; static const uint32_t TotalPhys = 16; @@ -154,12 +150,12 @@ class FloatRegisters { static const uint32_t AllDoubleMask = AllMask; static const uint32_t VolatileMask = #if defined(_WIN64) - (1 << X86Registers::xmm0) | - (1 << X86Registers::xmm1) | - (1 << X86Registers::xmm2) | - (1 << X86Registers::xmm3) | - (1 << X86Registers::xmm4) | - (1 << X86Registers::xmm5); + (1 << X86Encoding::xmm0) | + (1 << X86Encoding::xmm1) | + (1 << X86Encoding::xmm2) | + (1 << X86Encoding::xmm3) | + (1 << X86Encoding::xmm4) | + (1 << X86Encoding::xmm5); #else AllMask; #endif @@ -169,7 +165,7 @@ class FloatRegisters { static const uint32_t WrapperMask = VolatileMask; static const uint32_t NonAllocatableMask = - (1 << X86Registers::xmm15); // This is ScratchDoubleReg. + (1 << X86Encoding::xmm15); // This is ScratchDoubleReg. static const uint32_t AllocatableMask = AllMask & ~NonAllocatableMask; }; diff --git a/js/src/jit/x64/Assembler-x64.cpp b/js/src/jit/x64/Assembler-x64.cpp index 9846f2b5b21c..111bc1d10a1b 100644 --- a/js/src/jit/x64/Assembler-x64.cpp +++ b/js/src/jit/x64/Assembler-x64.cpp @@ -101,11 +101,11 @@ ABIArgGenerator::next(MIRType type) } // Avoid r11, which is the MacroAssembler's ScratchReg. -const Register ABIArgGenerator::NonArgReturnReg0 = r10; -const Register ABIArgGenerator::NonArgReturnReg1 = r12; -const Register ABIArgGenerator::NonVolatileReg = r13; -const Register ABIArgGenerator::NonArg_VolatileReg = rax; -const Register ABIArgGenerator::NonReturn_VolatileReg0 = rcx; +const Register ABIArgGenerator::NonArgReturnReg0 = jit::r10; +const Register ABIArgGenerator::NonArgReturnReg1 = jit::r12; +const Register ABIArgGenerator::NonVolatileReg = jit::r13; +const Register ABIArgGenerator::NonArg_VolatileReg = jit::rax; +const Register ABIArgGenerator::NonReturn_VolatileReg0 = jit::rcx; void Assembler::writeRelocation(JmpSrc src, Relocation::Kind reloc) @@ -216,8 +216,8 @@ Assembler::executableCopy(uint8_t *buffer) // to jump to a different code block. continue; } - if (X86Assembler::canRelinkJump(src, rp.target)) { - X86Assembler::setRel32(src, rp.target); + if (X86Encoding::CanRelinkJump(src, rp.target)) { + X86Encoding::SetRel32(src, rp.target); } else { // An extended jump table must exist, and its offset must be in // range. @@ -226,11 +226,11 @@ Assembler::executableCopy(uint8_t *buffer) // Patch the jump to go to the extended jump entry. uint8_t *entry = buffer + extendedJumpTable_ + i * SizeOfJumpTableEntry; - X86Assembler::setRel32(src, entry); + X86Encoding::SetRel32(src, entry); // Now patch the pointer, note that we need to align it to // *after* the extended jump, i.e. after the 64-bit immedate. - X86Assembler::setPointer(entry + SizeOfExtendedJump, rp.target); + X86Encoding::SetPointer(entry + SizeOfExtendedJump, rp.target); } } } @@ -268,13 +268,13 @@ class RelocationIterator JitCode * Assembler::CodeFromJump(JitCode *code, uint8_t *jump) { - uint8_t *target = (uint8_t *)X86Assembler::getRel32Target(jump); + uint8_t *target = (uint8_t *)X86Encoding::GetRel32Target(jump); if (target >= code->raw() && target < code->raw() + code->instructionsSize()) { // This jump is within the code buffer, so it has been redirected to // the extended jump table. MOZ_ASSERT(target + SizeOfJumpTableEntry <= code->raw() + code->instructionsSize()); - target = (uint8_t *)X86Assembler::getPointer(target + SizeOfExtendedJump); + target = (uint8_t *)X86Encoding::GetPointer(target + SizeOfExtendedJump); } return JitCode::FromExecutable(target); diff --git a/js/src/jit/x64/Assembler-x64.h b/js/src/jit/x64/Assembler-x64.h index 9f9874d9790c..f9c0bf0194ee 100644 --- a/js/src/jit/x64/Assembler-x64.h +++ b/js/src/jit/x64/Assembler-x64.h @@ -16,39 +16,39 @@ namespace js { namespace jit { -static MOZ_CONSTEXPR_VAR Register rax = { X86Registers::eax }; -static MOZ_CONSTEXPR_VAR Register rbx = { X86Registers::ebx }; -static MOZ_CONSTEXPR_VAR Register rcx = { X86Registers::ecx }; -static MOZ_CONSTEXPR_VAR Register rdx = { X86Registers::edx }; -static MOZ_CONSTEXPR_VAR Register rsi = { X86Registers::esi }; -static MOZ_CONSTEXPR_VAR Register rdi = { X86Registers::edi }; -static MOZ_CONSTEXPR_VAR Register rbp = { X86Registers::ebp }; -static MOZ_CONSTEXPR_VAR Register r8 = { X86Registers::r8 }; -static MOZ_CONSTEXPR_VAR Register r9 = { X86Registers::r9 }; -static MOZ_CONSTEXPR_VAR Register r10 = { X86Registers::r10 }; -static MOZ_CONSTEXPR_VAR Register r11 = { X86Registers::r11 }; -static MOZ_CONSTEXPR_VAR Register r12 = { X86Registers::r12 }; -static MOZ_CONSTEXPR_VAR Register r13 = { X86Registers::r13 }; -static MOZ_CONSTEXPR_VAR Register r14 = { X86Registers::r14 }; -static MOZ_CONSTEXPR_VAR Register r15 = { X86Registers::r15 }; -static MOZ_CONSTEXPR_VAR Register rsp = { X86Registers::esp }; +static MOZ_CONSTEXPR_VAR Register rax = { X86Encoding::rax }; +static MOZ_CONSTEXPR_VAR Register rbx = { X86Encoding::rbx }; +static MOZ_CONSTEXPR_VAR Register rcx = { X86Encoding::rcx }; +static MOZ_CONSTEXPR_VAR Register rdx = { X86Encoding::rdx }; +static MOZ_CONSTEXPR_VAR Register rsi = { X86Encoding::rsi }; +static MOZ_CONSTEXPR_VAR Register rdi = { X86Encoding::rdi }; +static MOZ_CONSTEXPR_VAR Register rbp = { X86Encoding::rbp }; +static MOZ_CONSTEXPR_VAR Register r8 = { X86Encoding::r8 }; +static MOZ_CONSTEXPR_VAR Register r9 = { X86Encoding::r9 }; +static MOZ_CONSTEXPR_VAR Register r10 = { X86Encoding::r10 }; +static MOZ_CONSTEXPR_VAR Register r11 = { X86Encoding::r11 }; +static MOZ_CONSTEXPR_VAR Register r12 = { X86Encoding::r12 }; +static MOZ_CONSTEXPR_VAR Register r13 = { X86Encoding::r13 }; +static MOZ_CONSTEXPR_VAR Register r14 = { X86Encoding::r14 }; +static MOZ_CONSTEXPR_VAR Register r15 = { X86Encoding::r15 }; +static MOZ_CONSTEXPR_VAR Register rsp = { X86Encoding::rsp }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm0 = { X86Registers::xmm0 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm1 = { X86Registers::xmm1 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm2 = { X86Registers::xmm2 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm3 = { X86Registers::xmm3 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm4 = { X86Registers::xmm4 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm5 = { X86Registers::xmm5 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm6 = { X86Registers::xmm6 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm7 = { X86Registers::xmm7 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm8 = { X86Registers::xmm8 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm9 = { X86Registers::xmm9 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm10 = { X86Registers::xmm10 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm11 = { X86Registers::xmm11 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm12 = { X86Registers::xmm12 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm13 = { X86Registers::xmm13 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm14 = { X86Registers::xmm14 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm15 = { X86Registers::xmm15 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm0 = { X86Encoding::xmm0 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm1 = { X86Encoding::xmm1 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm2 = { X86Encoding::xmm2 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm3 = { X86Encoding::xmm3 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm4 = { X86Encoding::xmm4 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm5 = { X86Encoding::xmm5 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm6 = { X86Encoding::xmm6 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm7 = { X86Encoding::xmm7 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm8 = { X86Encoding::xmm8 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm9 = { X86Encoding::xmm9 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm10 = { X86Encoding::xmm10 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm11 = { X86Encoding::xmm11 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm12 = { X86Encoding::xmm12 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm13 = { X86Encoding::xmm13 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm14 = { X86Encoding::xmm14 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm15 = { X86Encoding::xmm15 }; // X86-common synonyms. static MOZ_CONSTEXPR_VAR Register eax = rax; @@ -60,8 +60,8 @@ static MOZ_CONSTEXPR_VAR Register edi = rdi; static MOZ_CONSTEXPR_VAR Register ebp = rbp; static MOZ_CONSTEXPR_VAR Register esp = rsp; -static MOZ_CONSTEXPR_VAR Register InvalidReg = { X86Registers::invalid_reg }; -static MOZ_CONSTEXPR_VAR FloatRegister InvalidFloatReg = { X86Registers::invalid_xmm }; +static MOZ_CONSTEXPR_VAR Register InvalidReg = { X86Encoding::invalid_reg }; +static MOZ_CONSTEXPR_VAR FloatRegister InvalidFloatReg = { X86Encoding::invalid_xmm }; static MOZ_CONSTEXPR_VAR Register StackPointer = rsp; static MOZ_CONSTEXPR_VAR Register FramePointer = rbp; @@ -717,7 +717,7 @@ class Assembler : public AssemblerX86Shared } void j(Condition cond, ImmPtr target, Relocation::Kind reloc = Relocation::HARDCODED) { - JmpSrc src = masm.jCC(static_cast(cond)); + JmpSrc src = masm.jCC(static_cast(cond)); addPendingJump(src, target, reloc); } @@ -767,10 +767,10 @@ class Assembler : public AssemblerX86Shared static inline void PatchJump(CodeLocationJump jump, CodeLocationLabel label) { - if (X86Assembler::canRelinkJump(jump.raw(), label.raw())) { - X86Assembler::setRel32(jump.raw(), label.raw()); + if (X86Encoding::CanRelinkJump(jump.raw(), label.raw())) { + X86Encoding::SetRel32(jump.raw(), label.raw()); } else { - X86Assembler::setRel32(jump.raw(), jump.jumpTableEntry()); + X86Encoding::SetRel32(jump.raw(), jump.jumpTableEntry()); Assembler::PatchJumpEntry(jump.jumpTableEntry(), label.raw()); } } diff --git a/js/src/jit/x64/MacroAssembler-x64.h b/js/src/jit/x64/MacroAssembler-x64.h index 83f1d79f8d49..5083523cecc0 100644 --- a/js/src/jit/x64/MacroAssembler-x64.h +++ b/js/src/jit/x64/MacroAssembler-x64.h @@ -635,7 +635,7 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared } void branch32(Condition cond, AbsoluteAddress lhs, Imm32 rhs, Label *label) { - if (X86Assembler::isAddressImmediate(lhs.addr)) { + if (X86Encoding::IsAddressImmediate(lhs.addr)) { branch32(cond, Operand(lhs), rhs, label); } else { mov(ImmPtr(lhs.addr), ScratchReg); @@ -647,7 +647,7 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared branch32(cond, Address(ScratchReg, 0), rhs, label); } void branch32(Condition cond, AbsoluteAddress lhs, Register rhs, Label *label) { - if (X86Assembler::isAddressImmediate(lhs.addr)) { + if (X86Encoding::IsAddressImmediate(lhs.addr)) { branch32(cond, Operand(lhs), rhs, label); } else { mov(ImmPtr(lhs.addr), ScratchReg); @@ -655,7 +655,7 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared } } void branchTest32(Condition cond, AbsoluteAddress address, Imm32 imm, Label *label) { - if (X86Assembler::isAddressImmediate(address.addr)) { + if (X86Encoding::IsAddressImmediate(address.addr)) { test32(Operand(address), imm); } else { mov(ImmPtr(address.addr), ScratchReg); @@ -667,7 +667,7 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared // Specialization for AbsoluteAddress. void branchPtr(Condition cond, AbsoluteAddress addr, Register ptr, Label *label) { MOZ_ASSERT(ptr != ScratchReg); - if (X86Assembler::isAddressImmediate(addr.addr)) { + if (X86Encoding::IsAddressImmediate(addr.addr)) { branchPtr(cond, Operand(addr), ptr, label); } else { mov(ImmPtr(addr.addr), ScratchReg); @@ -675,7 +675,7 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared } } void branchPtr(Condition cond, AbsoluteAddress addr, ImmWord ptr, Label *label) { - if (X86Assembler::isAddressImmediate(addr.addr)) { + if (X86Encoding::IsAddressImmediate(addr.addr)) { branchPtr(cond, Operand(addr), ptr, label); } else { mov(ImmPtr(addr.addr), ScratchReg); @@ -767,7 +767,7 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared movePtr(noteMaybeNurseryPtr(imm), dest); } void loadPtr(AbsoluteAddress address, Register dest) { - if (X86Assembler::isAddressImmediate(address.addr)) { + if (X86Encoding::IsAddressImmediate(address.addr)) { movq(Operand(address), dest); } else { mov(ImmPtr(address.addr), ScratchReg); @@ -788,7 +788,7 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared shlq(Imm32(1), dest); } void load32(AbsoluteAddress address, Register dest) { - if (X86Assembler::isAddressImmediate(address.addr)) { + if (X86Encoding::IsAddressImmediate(address.addr)) { movl(Operand(address), dest); } else { mov(ImmPtr(address.addr), ScratchReg); @@ -823,7 +823,7 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared movq(src, dest); } void storePtr(Register src, AbsoluteAddress address) { - if (X86Assembler::isAddressImmediate(address.addr)) { + if (X86Encoding::IsAddressImmediate(address.addr)) { movq(src, Operand(address)); } else { mov(ImmPtr(address.addr), ScratchReg); @@ -831,7 +831,7 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared } } void store32(Register src, AbsoluteAddress address) { - if (X86Assembler::isAddressImmediate(address.addr)) { + if (X86Encoding::IsAddressImmediate(address.addr)) { movl(src, Operand(address)); } else { mov(ImmPtr(address.addr), ScratchReg); @@ -1355,7 +1355,7 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared } void inc64(AbsoluteAddress dest) { - if (X86Assembler::isAddressImmediate(dest.addr)) { + if (X86Encoding::IsAddressImmediate(dest.addr)) { addPtr(Imm32(1), Operand(dest)); } else { mov(ImmPtr(dest.addr), ScratchReg); diff --git a/js/src/jit/x86/Architecture-x86.h b/js/src/jit/x86/Architecture-x86.h index 05e3a59fb4dc..08c833cffef6 100644 --- a/js/src/jit/x86/Architecture-x86.h +++ b/js/src/jit/x86/Architecture-x86.h @@ -7,7 +7,7 @@ #ifndef jit_x86_Architecture_x86_h #define jit_x86_Architecture_x86_h -#include "jit/shared/BaseAssembler-x86-shared.h" +#include "jit/shared/Constants-x86-shared.h" namespace js { namespace jit { @@ -35,7 +35,7 @@ static const uint32_t BAILOUT_TABLE_ENTRY_SIZE = 5; class Registers { public: - typedef X86Registers::RegisterID Code; + typedef X86Encoding::RegisterID Code; typedef uint8_t SetType; static uint32_t SetSize(SetType x) { static_assert(sizeof(SetType) == 1, "SetType must be 8 bits"); @@ -48,9 +48,7 @@ class Registers { return 31 - mozilla::CountLeadingZeroes32(x); } static const char *GetName(Code code) { - static const char * const Names[] = { "eax", "ecx", "edx", "ebx", - "esp", "ebp", "esi", "edi" }; - return Names[code]; + return X86Encoding::GPRegName(code); } static Code FromName(const char *name) { @@ -61,8 +59,8 @@ class Registers { return Invalid; } - static const Code StackPointer = X86Registers::esp; - static const Code Invalid = X86Registers::invalid_reg; + static const Code StackPointer = X86Encoding::rsp; + static const Code Invalid = X86Encoding::invalid_reg; static const uint32_t Total = 8; static const uint32_t TotalPhys = 8; @@ -73,28 +71,28 @@ class Registers { static const uint32_t ArgRegMask = 0; static const uint32_t VolatileMask = - (1 << X86Registers::eax) | - (1 << X86Registers::ecx) | - (1 << X86Registers::edx); + (1 << X86Encoding::rax) | + (1 << X86Encoding::rcx) | + (1 << X86Encoding::rdx); static const uint32_t NonVolatileMask = - (1 << X86Registers::ebx) | - (1 << X86Registers::esi) | - (1 << X86Registers::edi) | - (1 << X86Registers::ebp); + (1 << X86Encoding::rbx) | + (1 << X86Encoding::rsi) | + (1 << X86Encoding::rdi) | + (1 << X86Encoding::rbp); static const uint32_t WrapperMask = VolatileMask | - (1 << X86Registers::ebx); + (1 << X86Encoding::rbx); static const uint32_t SingleByteRegs = - (1 << X86Registers::eax) | - (1 << X86Registers::ecx) | - (1 << X86Registers::edx) | - (1 << X86Registers::ebx); + (1 << X86Encoding::rax) | + (1 << X86Encoding::rcx) | + (1 << X86Encoding::rdx) | + (1 << X86Encoding::rbx); static const uint32_t NonAllocatableMask = - (1 << X86Registers::esp); + (1 << X86Encoding::rsp); static const uint32_t AllocatableMask = AllMask & ~NonAllocatableMask; @@ -103,12 +101,12 @@ class Registers { // Registers returned from a JS -> JS call. static const uint32_t JSCallMask = - (1 << X86Registers::ecx) | - (1 << X86Registers::edx); + (1 << X86Encoding::rcx) | + (1 << X86Encoding::rdx); // Registers returned from a JS -> C call. static const uint32_t CallMask = - (1 << X86Registers::eax); + (1 << X86Encoding::rax); }; // Smallest integer type that can hold a register bitmask. @@ -116,12 +114,10 @@ typedef uint8_t PackedRegisterMask; class FloatRegisters { public: - typedef X86Registers::XMMRegisterID Code; + typedef X86Encoding::XMMRegisterID Code; typedef uint32_t SetType; static const char *GetName(Code code) { - static const char * const Names[] = { "xmm0", "xmm1", "xmm2", "xmm3", - "xmm4", "xmm5", "xmm6", "xmm7" }; - return Names[code]; + return X86Encoding::XMMRegName(code); } static Code FromName(const char *name) { @@ -132,7 +128,7 @@ class FloatRegisters { return Invalid; } - static const Code Invalid = X86Registers::invalid_xmm; + static const Code Invalid = X86Encoding::invalid_xmm; static const uint32_t Total = 8; static const uint32_t TotalPhys = 8; @@ -146,7 +142,7 @@ class FloatRegisters { static const uint32_t WrapperMask = VolatileMask; static const uint32_t NonAllocatableMask = - (1 << X86Registers::xmm7); // This is ScratchDoubleReg. + (1 << X86Encoding::xmm7); // This is ScratchDoubleReg. static const uint32_t AllocatableMask = AllMask & ~NonAllocatableMask; }; diff --git a/js/src/jit/x86/Assembler-x86.cpp b/js/src/jit/x86/Assembler-x86.cpp index 8b6812f0d9be..8a4f40f8f105 100644 --- a/js/src/jit/x86/Assembler-x86.cpp +++ b/js/src/jit/x86/Assembler-x86.cpp @@ -58,7 +58,7 @@ Assembler::executableCopy(uint8_t *buffer) for (size_t i = 0; i < jumps_.length(); i++) { RelativePatch &rp = jumps_[i]; - X86Assembler::setRel32(buffer + rp.offset, rp.target); + X86Encoding::SetRel32(buffer + rp.offset, rp.target); } } @@ -87,7 +87,7 @@ class RelocationIterator static inline JitCode * CodeFromJump(uint8_t *jump) { - uint8_t *target = (uint8_t *)X86Assembler::getRel32Target(jump); + uint8_t *target = (uint8_t *)X86Encoding::GetRel32Target(jump); return JitCode::FromExecutable(target); } diff --git a/js/src/jit/x86/Assembler-x86.h b/js/src/jit/x86/Assembler-x86.h index 8aeb92022bd0..27ce2e5eff64 100644 --- a/js/src/jit/x86/Assembler-x86.h +++ b/js/src/jit/x86/Assembler-x86.h @@ -13,31 +13,31 @@ #include "jit/IonCode.h" #include "jit/JitCompartment.h" #include "jit/shared/Assembler-shared.h" -#include "jit/shared/BaseAssembler-x86-shared.h" +#include "jit/shared/Constants-x86-shared.h" namespace js { namespace jit { -static MOZ_CONSTEXPR_VAR Register eax = { X86Registers::eax }; -static MOZ_CONSTEXPR_VAR Register ecx = { X86Registers::ecx }; -static MOZ_CONSTEXPR_VAR Register edx = { X86Registers::edx }; -static MOZ_CONSTEXPR_VAR Register ebx = { X86Registers::ebx }; -static MOZ_CONSTEXPR_VAR Register esp = { X86Registers::esp }; -static MOZ_CONSTEXPR_VAR Register ebp = { X86Registers::ebp }; -static MOZ_CONSTEXPR_VAR Register esi = { X86Registers::esi }; -static MOZ_CONSTEXPR_VAR Register edi = { X86Registers::edi }; +static MOZ_CONSTEXPR_VAR Register eax = { X86Encoding::rax }; +static MOZ_CONSTEXPR_VAR Register ecx = { X86Encoding::rcx }; +static MOZ_CONSTEXPR_VAR Register edx = { X86Encoding::rdx }; +static MOZ_CONSTEXPR_VAR Register ebx = { X86Encoding::rbx }; +static MOZ_CONSTEXPR_VAR Register esp = { X86Encoding::rsp }; +static MOZ_CONSTEXPR_VAR Register ebp = { X86Encoding::rbp }; +static MOZ_CONSTEXPR_VAR Register esi = { X86Encoding::rsi }; +static MOZ_CONSTEXPR_VAR Register edi = { X86Encoding::rdi }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm0 = { X86Registers::xmm0 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm1 = { X86Registers::xmm1 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm2 = { X86Registers::xmm2 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm3 = { X86Registers::xmm3 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm4 = { X86Registers::xmm4 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm5 = { X86Registers::xmm5 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm6 = { X86Registers::xmm6 }; -static MOZ_CONSTEXPR_VAR FloatRegister xmm7 = { X86Registers::xmm7 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm0 = { X86Encoding::xmm0 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm1 = { X86Encoding::xmm1 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm2 = { X86Encoding::xmm2 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm3 = { X86Encoding::xmm3 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm4 = { X86Encoding::xmm4 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm5 = { X86Encoding::xmm5 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm6 = { X86Encoding::xmm6 }; +static MOZ_CONSTEXPR_VAR FloatRegister xmm7 = { X86Encoding::xmm7 }; -static MOZ_CONSTEXPR_VAR Register InvalidReg = { X86Registers::invalid_reg }; -static MOZ_CONSTEXPR_VAR FloatRegister InvalidFloatReg = { X86Registers::invalid_xmm }; +static MOZ_CONSTEXPR_VAR Register InvalidReg = { X86Encoding::invalid_reg }; +static MOZ_CONSTEXPR_VAR FloatRegister InvalidFloatReg = { X86Encoding::invalid_xmm }; static MOZ_CONSTEXPR_VAR Register JSReturnReg_Type = ecx; static MOZ_CONSTEXPR_VAR Register JSReturnReg_Data = edx; @@ -164,7 +164,7 @@ PatchJump(CodeLocationJump jump, CodeLocationLabel label) MOZ_ASSERT(((*x >= 0x80 && *x <= 0x8F) && *(x - 1) == 0x0F) || (*x == 0xE9)); #endif - X86Assembler::setRel32(jump.raw(), label.raw()); + X86Encoding::SetRel32(jump.raw(), label.raw()); } static inline void PatchBackedge(CodeLocationJump &jump_, CodeLocationLabel label, JitRuntime::BackedgeTarget target) @@ -381,7 +381,7 @@ class Assembler : public AssemblerX86Shared } void j(Condition cond, ImmPtr target, Relocation::Kind reloc = Relocation::HARDCODED) { - JmpSrc src = masm.jCC(static_cast(cond)); + JmpSrc src = masm.jCC(static_cast(cond)); addPendingJump(src, target, reloc); } @@ -423,9 +423,9 @@ class Assembler : public AssemblerX86Shared void retarget(Label *label, ImmPtr target, Relocation::Kind reloc) { if (label->used()) { bool more; - X86Assembler::JmpSrc jmp(label->offset()); + X86Encoding::JmpSrc jmp(label->offset()); do { - X86Assembler::JmpSrc next; + X86Encoding::JmpSrc next; more = masm.nextJump(jmp, &next); addPendingJump(jmp, target, reloc); jmp = next; @@ -630,7 +630,7 @@ class Assembler : public AssemblerX86Shared } static bool canUseInSingleByteInstruction(Register reg) { - return !ByteRegRequiresRex(reg.code()); + return X86Encoding::HasSubregL(reg.code()); } };