Bug 1132920: Use movddup for SIMD swizzle pattern (0, 1, 0, 1) on SSE3 enabled machines; r=sunfish

--HG--
extra : rebase_source : ac9196feec31d129c91525eaac2908d7567d3f4b

js/src/jit/shared/Assembler-x86-shared.h

@@ -2170,6 +2170,10 @@ class AssemblerX86Shared : public AssemblerShared
             MOZ_CRASH("unexpected operand kind");
         }
     }
+    void vmovddup(FloatRegister src, FloatRegister dest) {
+        MOZ_ASSERT(HasSSE3());
+        masm.vmovddup_rr(src.encoding(), dest.encoding());
+    }
     void vmovhlps(FloatRegister src1, FloatRegister src0, FloatRegister dest) {
         MOZ_ASSERT(HasSSE2());
         masm.vmovhlps_rr(src1.encoding(), src0.encoding(), dest.encoding());

js/src/jit/shared/BaseAssembler-x86-shared.h

@@ -2684,6 +2684,11 @@ public:
         twoByteOpImmSimd("vshufps", VEX_PS, OP2_SHUFPS_VpsWpsIb, mask, address, src0, dst);
     }
 
+    void vmovddup_rr(XMMRegisterID src, XMMRegisterID dst)
+    {
+        twoByteOpSimd("vmovddup", VEX_SD, OP2_MOVDDUP_VqWq, src, invalid_xmm, dst);
+    }
+
     void vmovhlps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovhlps", VEX_PS, OP2_MOVHLPS_VqUq, src1, src0, dst);

js/src/jit/shared/CodeGenerator-x86-shared.cpp

@@ -2512,6 +2512,10 @@ CodeGeneratorX86Shared::visitSimdSwizzleF(LSimdSwizzleF *ins)
     }
 
     if (ins->lanesMatch(0, 1, 0, 1)) {
+        if (AssemblerX86Shared::HasSSE3() && !AssemblerX86Shared::HasAVX()) {
+            masm.vmovddup(input, output);
+            return;
+        }
         FloatRegister inputCopy = masm.reusedInputFloat32x4(input, output);
         masm.vmovlhps(input, inputCopy, output);
         return;

js/src/jit/shared/Encoding-x86-shared.h

@@ -130,6 +130,7 @@ enum TwoByteOpcodeID {
     OP2_MOVPS_VpsWps    = 0x10,
     OP2_MOVSD_WsdVsd    = 0x11,
     OP2_MOVPS_WpsVps    = 0x11,
+    OP2_MOVDDUP_VqWq    = 0x12,
     OP2_MOVHLPS_VqUq    = 0x12,
     OP2_MOVSLDUP_VpsWps = 0x12,
     OP2_UNPCKLPS_VsdWsd = 0x14,