Lower ARM MIPS NJ_MAX_STACK_ENTRY to 1024 as a workaround for asm_spill() limitations (bug 556175)

Fixme's added, explaining why.

--HG--
extra : convert_revision : 7d102db403b76739c69fbf1e5b1e35bdbeb4b3c6

js/src/nanojit/NativeARM.cpp

@@ -1277,6 +1277,8 @@ Assembler::asm_spill(Register rr, int d, bool pop, bool quad)
     (void) pop;
     (void) quad;
     NanoAssert(d);
+    // fixme: bug 556175 this code doesn't appear to handle
+    // values of d outside the 12-bit range.
     if (_config.arm_vfp && IsFpReg(rr)) {
         if (isS8(d >> 2)) {
             FSTD(rr, FP, d);

js/src/nanojit/NativeARM.h

@@ -65,7 +65,12 @@ namespace nanojit
 // only d0-d6 are actually used; we'll use d7 as s14-s15 for i2f/u2f/etc.
 #define NJ_VFP_MAX_REGISTERS            8
 #define NJ_MAX_REGISTERS                (11 + NJ_VFP_MAX_REGISTERS)
-#define NJ_MAX_STACK_ENTRY              4096
+
+// fixme: bug 556175: this cant be over 1024, because
+// the ARM backend cannot support more than 12-bit displacements
+// in a single load/store instruction, for spilling.  see asm_spill().
+#define NJ_MAX_STACK_ENTRY              1024
+
 #define NJ_MAX_PARAMETERS               16
 #define NJ_ALIGN_STACK                  8