зеркало из https://github.com/mozilla/gecko-dev.git
Bug 1752231 - Refactor binarySimd128 to allow VEX encoding. r=jseward
Changes: * Extends masm's operations with SimdConstants as an args, to be non-destructive * Refactor BaseAssembler rrip encoding helpers * Remove unused ripr helpers -- not going to store anything if the code * Add moveSimd128XXXIfNotAVX helpers Differential Revision: https://phabricator.services.mozilla.com/D137080
This commit is contained in:
Yury Delendik
Родитель
61333f12cc
Коммит
47ee064f19
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@ -22,6 +22,32 @@ function codegenTestX64_v128xv128_v128_avxhack(inputs, options = {}) {
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options);
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}
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}
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// (see codegenTestX64_v128xv128_v128_avxhack comment about AVX defect)
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// v128 OP const -> v128
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// inputs: [[complete-opname, const, expected-pattern], ...]
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function codegenTestX64_v128xLITERAL_v128_avxhack(inputs, options = {}) {
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for ( let [op, const_, expected] of inputs ) {
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codegenTestX64_adhoc(wrap(options, `
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(func (export "f") (param v128 v128) (result v128)
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(${op} (local.get 1) ${const_}))`),
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'f',
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expected,
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options);
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}
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}
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// (see codegenTestX64_v128xv128_v128_avxhack comment about AVX defect)
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// const OP v128 -> v128
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// inputs: [[complete-opname, const, expected-pattern], ...]
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function codegenTestX64_LITERALxv128_v128_avxhack(inputs, options = {}) {
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for ( let [op, const_, expected] of inputs ) {
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codegenTestX64_adhoc(wrap(options, `
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(func (export "f") (param v128 v128) (result v128)
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(${op} ${const_} (local.get 1)))`),
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'f',
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expected,
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options);
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}
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}
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// Utility function to test SIMD operations encoding, where the input argument
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// has the specified type (T).
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@ -174,3 +200,236 @@ codegenTestX64_adhoc(
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`
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66 0f 6f 0d ${RIPRADDR} movdqax ${RIPR}, %xmm1
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c4 e3 69 4c c3 10 vpblendvb %xmm1, %xmm3, %xmm2, %xmm0`);
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// Constant arguments that are folded into the instruction
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codegenTestX64_v128xLITERAL_v128_avxhack(
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[['i8x16.add', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 fc 05 ${RIPRADDR} vpaddbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.sub', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 f8 05 ${RIPRADDR} vpsubbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.add_sat_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 ec 05 ${RIPRADDR} vpaddsbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.add_sat_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 dc 05 ${RIPRADDR} vpaddusbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.sub_sat_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 e8 05 ${RIPRADDR} vpsubsbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.sub_sat_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 d8 05 ${RIPRADDR} vpsubusbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.min_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c4 e2 71 38 05 ${RIPRADDR} vpminsbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.min_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 da 05 ${RIPRADDR} vpminubx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.max_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c4 e2 71 3c 05 ${RIPRADDR} vpmaxsbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.max_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 de 05 ${RIPRADDR} vpmaxubx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.eq', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 74 05 ${RIPRADDR} vpcmpeqbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.ne', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)', `
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c5 f1 74 05 ${RIPRADDR} vpcmpeqbx ${RIPR}, %xmm1, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i8x16.gt_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 64 05 ${RIPRADDR} vpcmpgtbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.le_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)', `
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c5 f1 64 05 ${RIPRADDR} vpcmpgtbx ${RIPR}, %xmm1, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i8x16.narrow_i16x8_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 63 05 ${RIPRADDR} vpacksswbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.narrow_i16x8_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 67 05 ${RIPRADDR} vpackuswbx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.add', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 fd 05 ${RIPRADDR} vpaddwx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.sub', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 f9 05 ${RIPRADDR} vpsubwx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.mul', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 d5 05 ${RIPRADDR} vpmullwx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.add_sat_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 ed 05 ${RIPRADDR} vpaddswx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.add_sat_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 dd 05 ${RIPRADDR} vpadduswx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.sub_sat_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 e9 05 ${RIPRADDR} vpsubswx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.sub_sat_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 d9 05 ${RIPRADDR} vpsubuswx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.min_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 ea 05 ${RIPRADDR} vpminswx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.min_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c4 e2 71 3a 05 ${RIPRADDR} vpminuwx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.max_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 ee 05 ${RIPRADDR} vpmaxswx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.max_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c4 e2 71 3e 05 ${RIPRADDR} vpmaxuwx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.eq', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 75 05 ${RIPRADDR} vpcmpeqwx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.ne', '(v128.const i16x8 1 2 1 2 1 2 1 2)', `
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c5 f1 75 05 ${RIPRADDR} vpcmpeqwx ${RIPR}, %xmm1, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i16x8.gt_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 65 05 ${RIPRADDR} vpcmpgtwx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.le_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)', `
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c5 f1 65 05 ${RIPRADDR} vpcmpgtwx ${RIPR}, %xmm1, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i16x8.narrow_i32x4_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 6b 05 ${RIPRADDR} vpackssdwx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.narrow_i32x4_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c4 e2 71 2b 05 ${RIPRADDR} vpackusdwx ${RIPR}, %xmm1, %xmm0`],
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['i32x4.add', '(v128.const i32x4 1 2 1 2)',
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`c5 f1 fe 05 ${RIPRADDR} vpadddx ${RIPR}, %xmm1, %xmm0`],
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['i32x4.sub', '(v128.const i32x4 1 2 1 2)',
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`c5 f1 fa 05 ${RIPRADDR} vpsubdx ${RIPR}, %xmm1, %xmm0`],
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['i32x4.mul', '(v128.const i32x4 1 2 1 2)',
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`c4 e2 71 40 05 ${RIPRADDR} vpmulldx ${RIPR}, %xmm1, %xmm0`],
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['i32x4.min_s', '(v128.const i32x4 1 2 1 2)',
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`c4 e2 71 39 05 ${RIPRADDR} vpminsdx ${RIPR}, %xmm1, %xmm0`],
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['i32x4.min_u', '(v128.const i32x4 1 2 1 2)',
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`c4 e2 71 3b 05 ${RIPRADDR} vpminudx ${RIPR}, %xmm1, %xmm0`],
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['i32x4.max_s', '(v128.const i32x4 1 2 1 2)',
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`c4 e2 71 3d 05 ${RIPRADDR} vpmaxsdx ${RIPR}, %xmm1, %xmm0`],
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['i32x4.max_u', '(v128.const i32x4 1 2 1 2)',
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`c4 e2 71 3f 05 ${RIPRADDR} vpmaxudx ${RIPR}, %xmm1, %xmm0`],
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['i32x4.eq', '(v128.const i32x4 1 2 1 2)',
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`c5 f1 76 05 ${RIPRADDR} vpcmpeqdx ${RIPR}, %xmm1, %xmm0`],
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['i32x4.ne', '(v128.const i32x4 1 2 1 2)', `
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c5 f1 76 05 ${RIPRADDR} vpcmpeqdx ${RIPR}, %xmm1, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i32x4.gt_s', '(v128.const i32x4 1 2 1 2)',
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`c5 f1 66 05 ${RIPRADDR} vpcmpgtdx ${RIPR}, %xmm1, %xmm0`],
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['i32x4.le_s', '(v128.const i32x4 1 2 1 2)', `
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c5 f1 66 05 ${RIPRADDR} vpcmpgtdx ${RIPR}, %xmm1, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i32x4.dot_i16x8_s', '(v128.const i32x4 1 2 1 2)',
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`c5 f1 f5 05 ${RIPRADDR} vpmaddwdx ${RIPR}, %xmm1, %xmm0`],
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['i64x2.add', '(v128.const i64x2 1 2)',
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`c5 f1 d4 05 ${RIPRADDR} vpaddqx ${RIPR}, %xmm1, %xmm0`],
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['i64x2.sub', '(v128.const i64x2 1 2)',
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`c5 f1 fb 05 ${RIPRADDR} vpsubqx ${RIPR}, %xmm1, %xmm0`],
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['v128.and', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 db 05 ${RIPRADDR} vpandx ${RIPR}, %xmm1, %xmm0`],
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['v128.or', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 eb 05 ${RIPRADDR} vporx ${RIPR}, %xmm1, %xmm0`],
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['v128.xor', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 ef 05 ${RIPRADDR} vpxorx ${RIPR}, %xmm1, %xmm0`],
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['f32x4.add', '(v128.const f32x4 1 2 3 4)',
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`c5 f0 58 05 ${RIPRADDR} vaddpsx ${RIPR}, %xmm1, %xmm0`],
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['f32x4.sub', '(v128.const f32x4 1 2 3 4)',
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`c5 f0 5c 05 ${RIPRADDR} vsubpsx ${RIPR}, %xmm1, %xmm0`],
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['f32x4.mul', '(v128.const f32x4 1 2 3 4)',
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`c5 f0 59 05 ${RIPRADDR} vmulpsx ${RIPR}, %xmm1, %xmm0`],
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['f32x4.div', '(v128.const f32x4 1 2 3 4)',
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`c5 f0 5e 05 ${RIPRADDR} vdivpsx ${RIPR}, %xmm1, %xmm0`],
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['f64x2.add', '(v128.const f64x2 1 2)',
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`c5 f1 58 05 ${RIPRADDR} vaddpdx ${RIPR}, %xmm1, %xmm0`],
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['f64x2.sub', '(v128.const f64x2 1 2)',
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`c5 f1 5c 05 ${RIPRADDR} vsubpdx ${RIPR}, %xmm1, %xmm0`],
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['f64x2.mul', '(v128.const f64x2 1 2)',
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`c5 f1 59 05 ${RIPRADDR} vmulpdx ${RIPR}, %xmm1, %xmm0`],
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['f64x2.div', '(v128.const f64x2 1 2)',
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`c5 f1 5e 05 ${RIPRADDR} vdivpdx ${RIPR}, %xmm1, %xmm0`],
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['f32x4.eq', '(v128.const f32x4 1 2 3 4)',
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`c5 f0 c2 05 ${RIPRADDR} 00 vcmppsx \\$0x00, ${RIPR}, %xmm1, %xmm0`],
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['f32x4.ne', '(v128.const f32x4 1 2 3 4)',
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`c5 f0 c2 05 ${RIPRADDR} 04 vcmppsx \\$0x04, ${RIPR}, %xmm1, %xmm0`],
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['f32x4.lt', '(v128.const f32x4 1 2 3 4)',
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`c5 f0 c2 05 ${RIPRADDR} 01 vcmppsx \\$0x01, ${RIPR}, %xmm1, %xmm0`],
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['f32x4.le', '(v128.const f32x4 1 2 3 4)',
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`c5 f0 c2 05 ${RIPRADDR} 02 vcmppsx \\$0x02, ${RIPR}, %xmm1, %xmm0`],
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['f64x2.eq', '(v128.const f64x2 1 2)',
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`c5 f1 c2 05 ${RIPRADDR} 00 vcmppdx \\$0x00, ${RIPR}, %xmm1, %xmm0`],
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['f64x2.ne', '(v128.const f64x2 1 2)',
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`c5 f1 c2 05 ${RIPRADDR} 04 vcmppdx \\$0x04, ${RIPR}, %xmm1, %xmm0`],
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['f64x2.lt', '(v128.const f64x2 1 2)',
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`c5 f1 c2 05 ${RIPRADDR} 01 vcmppdx \\$0x01, ${RIPR}, %xmm1, %xmm0`],
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['f64x2.le', '(v128.const f64x2 1 2)',
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`c5 f1 c2 05 ${RIPRADDR} 02 vcmppdx \\$0x02, ${RIPR}, %xmm1, %xmm0`]]);
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// Commutative operations with constants on the lhs should generate the same
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// code as with the constant on the rhs.
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codegenTestX64_LITERALxv128_v128_avxhack(
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[['i8x16.add', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 fc 05 ${RIPRADDR} vpaddbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.add_sat_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 ec 05 ${RIPRADDR} vpaddsbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.add_sat_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 dc 05 ${RIPRADDR} vpaddusbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.min_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c4 e2 71 38 05 ${RIPRADDR} vpminsbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.min_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 da 05 ${RIPRADDR} vpminubx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.max_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c4 e2 71 3c 05 ${RIPRADDR} vpmaxsbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.max_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 de 05 ${RIPRADDR} vpmaxubx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.eq', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`c5 f1 74 05 ${RIPRADDR} vpcmpeqbx ${RIPR}, %xmm1, %xmm0`],
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['i8x16.ne', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)', `
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c5 f1 74 05 ${RIPRADDR} vpcmpeqbx ${RIPR}, %xmm1, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i16x8.add', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 fd 05 ${RIPRADDR} vpaddwx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.mul', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 d5 05 ${RIPRADDR} vpmullwx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.add_sat_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 ed 05 ${RIPRADDR} vpaddswx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.add_sat_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 dd 05 ${RIPRADDR} vpadduswx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.min_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 ea 05 ${RIPRADDR} vpminswx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.min_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c4 e2 71 3a 05 ${RIPRADDR} vpminuwx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.max_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`c5 f1 ee 05 ${RIPRADDR} vpmaxswx ${RIPR}, %xmm1, %xmm0`],
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['i16x8.max_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
|
||||
`c4 e2 71 3e 05 ${RIPRADDR} vpmaxuwx ${RIPR}, %xmm1, %xmm0`],
|
||||
['i16x8.eq', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
|
||||
`c5 f1 75 05 ${RIPRADDR} vpcmpeqwx ${RIPR}, %xmm1, %xmm0`],
|
||||
['i16x8.ne', '(v128.const i16x8 1 2 1 2 1 2 1 2)', `
|
||||
c5 f1 75 05 ${RIPRADDR} vpcmpeqwx ${RIPR}, %xmm1, %xmm0
|
||||
66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
|
||||
66 41 0f ef c7 pxor %xmm15, %xmm0`],
|
||||
|
||||
['i32x4.add', '(v128.const i32x4 1 2 1 2)',
|
||||
`c5 f1 fe 05 ${RIPRADDR} vpadddx ${RIPR}, %xmm1, %xmm0`],
|
||||
['i32x4.mul', '(v128.const i32x4 1 2 1 2)',
|
||||
`c4 e2 71 40 05 ${RIPRADDR} vpmulldx ${RIPR}, %xmm1, %xmm0`],
|
||||
['i32x4.min_s', '(v128.const i32x4 1 2 1 2)',
|
||||
`c4 e2 71 39 05 ${RIPRADDR} vpminsdx ${RIPR}, %xmm1, %xmm0`],
|
||||
['i32x4.min_u', '(v128.const i32x4 1 2 1 2)',
|
||||
`c4 e2 71 3b 05 ${RIPRADDR} vpminudx ${RIPR}, %xmm1, %xmm0`],
|
||||
['i32x4.max_s', '(v128.const i32x4 1 2 1 2)',
|
||||
`c4 e2 71 3d 05 ${RIPRADDR} vpmaxsdx ${RIPR}, %xmm1, %xmm0`],
|
||||
['i32x4.max_u', '(v128.const i32x4 1 2 1 2)',
|
||||
`c4 e2 71 3f 05 ${RIPRADDR} vpmaxudx ${RIPR}, %xmm1, %xmm0`],
|
||||
['i32x4.eq', '(v128.const i32x4 1 2 1 2)',
|
||||
`c5 f1 76 05 ${RIPRADDR} vpcmpeqdx ${RIPR}, %xmm1, %xmm0`],
|
||||
['i32x4.ne', '(v128.const i32x4 1 2 1 2)', `
|
||||
c5 f1 76 05 ${RIPRADDR} vpcmpeqdx ${RIPR}, %xmm1, %xmm0
|
||||
66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
|
||||
66 41 0f ef c7 pxor %xmm15, %xmm0`],
|
||||
['i32x4.dot_i16x8_s', '(v128.const i32x4 1 2 1 2)',
|
||||
`c5 f1 f5 05 ${RIPRADDR} vpmaddwdx ${RIPR}, %xmm1, %xmm0`],
|
||||
|
||||
['i64x2.add', '(v128.const i64x2 1 2)',
|
||||
`c5 f1 d4 05 ${RIPRADDR} vpaddqx ${RIPR}, %xmm1, %xmm0`],
|
||||
|
||||
['v128.and', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
|
||||
`c5 f1 db 05 ${RIPRADDR} vpandx ${RIPR}, %xmm1, %xmm0`],
|
||||
['v128.or', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
|
||||
`c5 f1 eb 05 ${RIPRADDR} vporx ${RIPR}, %xmm1, %xmm0`],
|
||||
['v128.xor', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
|
||||
`c5 f1 ef 05 ${RIPRADDR} vpxorx ${RIPR}, %xmm1, %xmm0`]]);
|
||||
|
|
|
|||
|
|
@ -2399,8 +2399,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void addInt8x16(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void addInt8x16(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void addInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void addInt16x8(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2408,8 +2408,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void addInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void addInt16x8(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void addInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void addInt32x4(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2417,8 +2417,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void addInt32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void addInt32x4(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void addInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void addInt64x2(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2426,8 +2426,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void addInt64x2(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void addInt64x2(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void addInt64x2(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
// Integer Subtract
|
||||
|
||||
|
|
@ -2437,8 +2437,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void subInt8x16(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void subInt8x16(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void subInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void subInt16x8(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2446,14 +2446,14 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void subInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void subInt16x8(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void subInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void subInt32x4(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void subInt32x4(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void subInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void subInt32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2461,8 +2461,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void subInt64x2(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void subInt64x2(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void subInt64x2(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void subInt64x2(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
|
@ -2475,8 +2475,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void mulInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void mulInt16x8(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void mulInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void mulInt32x4(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2484,8 +2484,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void mulInt32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void mulInt32x4(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void mulInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
// On x86_shared, it is required lhs == dest
|
||||
inline void mulInt64x2(FloatRegister lhs, FloatRegister rhs,
|
||||
|
|
@ -2601,8 +2601,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void addSatInt8x16(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void addSatInt8x16(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void addSatInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void unsignedAddSatInt8x16(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2610,9 +2610,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void unsignedAddSatInt8x16(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void unsignedAddSatInt8x16(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void unsignedAddSatInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void addSatInt16x8(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2620,8 +2619,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void addSatInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void addSatInt16x8(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void addSatInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void unsignedAddSatInt16x8(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2629,9 +2628,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void unsignedAddSatInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void unsignedAddSatInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void unsignedAddSatInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
// Saturating integer subtract
|
||||
|
||||
|
|
@ -2641,8 +2639,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void subSatInt8x16(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void subSatInt8x16(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void subSatInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void unsignedSubSatInt8x16(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2650,9 +2648,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void unsignedSubSatInt8x16(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void unsignedSubSatInt8x16(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void unsignedSubSatInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void subSatInt16x8(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2660,8 +2657,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void subSatInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void subSatInt16x8(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void subSatInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void unsignedSubSatInt16x8(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2669,9 +2666,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void unsignedSubSatInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void unsignedSubSatInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void unsignedSubSatInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
// Lane-wise integer minimum
|
||||
|
||||
|
|
@ -2681,8 +2677,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void minInt8x16(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void minInt8x16(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void minInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void unsignedMinInt8x16(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2690,8 +2686,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void unsignedMinInt8x16(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void unsignedMinInt8x16(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void unsignedMinInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void minInt16x8(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2699,8 +2695,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void minInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void minInt16x8(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void minInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void unsignedMinInt16x8(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2708,8 +2704,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void unsignedMinInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void unsignedMinInt16x8(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void unsignedMinInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void minInt32x4(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2717,8 +2713,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void minInt32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void minInt32x4(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void minInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void unsignedMinInt32x4(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2726,8 +2722,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void unsignedMinInt32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void unsignedMinInt32x4(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void unsignedMinInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
// Lane-wise integer maximum
|
||||
|
||||
|
|
@ -2737,8 +2733,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void maxInt8x16(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void maxInt8x16(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void maxInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void unsignedMaxInt8x16(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2746,8 +2742,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void unsignedMaxInt8x16(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void unsignedMaxInt8x16(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void unsignedMaxInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void maxInt16x8(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2755,8 +2751,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void maxInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void maxInt16x8(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void maxInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void unsignedMaxInt16x8(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2764,8 +2760,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void unsignedMaxInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void unsignedMaxInt16x8(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void unsignedMaxInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void maxInt32x4(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2773,8 +2769,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void maxInt32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void maxInt32x4(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void maxInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void unsignedMaxInt32x4(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2782,8 +2778,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void unsignedMaxInt32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void unsignedMaxInt32x4(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void unsignedMaxInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
// Lane-wise integer rounding average
|
||||
|
||||
|
|
@ -2963,8 +2959,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
FloatRegister dest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void bitwiseAndSimd128(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void bitwiseAndSimd128(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void bitwiseOrSimd128(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2973,8 +2969,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
FloatRegister dest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void bitwiseOrSimd128(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void bitwiseOrSimd128(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void bitwiseXorSimd128(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -2983,8 +2979,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
FloatRegister dest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void bitwiseXorSimd128(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void bitwiseXorSimd128(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void bitwiseNotSimd128(FloatRegister src, FloatRegister dest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -3072,8 +3068,9 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
// On x86_shared, limited to !=, ==, <=, >
|
||||
inline void compareInt8x16(Assembler::Condition cond, const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) DEFINED_ON(x86_shared);
|
||||
inline void compareInt8x16(Assembler::Condition cond, FloatRegister lhs,
|
||||
const SimdConstant& rhs, FloatRegister dest)
|
||||
DEFINED_ON(x86_shared);
|
||||
|
||||
// On arm64, use any integer comparison condition.
|
||||
inline void compareInt8x16(Assembler::Condition cond, FloatRegister lhs,
|
||||
|
|
@ -3089,18 +3086,20 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
DEFINED_ON(arm64);
|
||||
|
||||
// On x86_shared, limited to !=, ==, <=, >
|
||||
inline void compareInt16x8(Assembler::Condition cond, const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) DEFINED_ON(x86_shared);
|
||||
inline void compareInt16x8(Assembler::Condition cond, FloatRegister lhs,
|
||||
const SimdConstant& rhs, FloatRegister dest)
|
||||
DEFINED_ON(x86_shared);
|
||||
|
||||
// On x86_shared, limited to !=, ==, <=, >
|
||||
inline void compareInt32x4(Assembler::Condition cond, FloatRegister rhs,
|
||||
FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
// On arm64, use any integer comparison condition.
|
||||
inline void compareInt32x4(Assembler::Condition cond, const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) DEFINED_ON(x86_shared);
|
||||
inline void compareInt32x4(Assembler::Condition cond, FloatRegister lhs,
|
||||
const SimdConstant& rhs, FloatRegister dest)
|
||||
DEFINED_ON(x86_shared);
|
||||
|
||||
// On arm64, use any integer comparison condition.
|
||||
inline void compareInt32x4(Assembler::Condition cond, FloatRegister lhs,
|
||||
FloatRegister rhs, FloatRegister dest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -3126,8 +3125,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
// On x86_shared, limited to ==, !=, <, <=
|
||||
inline void compareFloat32x4(Assembler::Condition cond,
|
||||
const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
inline void compareFloat32x4(Assembler::Condition cond, FloatRegister lhs,
|
||||
const SimdConstant& rhs, FloatRegister dest)
|
||||
DEFINED_ON(x86_shared);
|
||||
|
||||
// On x86_shared, limited to ==, !=, <, <=
|
||||
|
|
@ -3141,8 +3140,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
// On x86_shared, limited to ==, !=, <, <=
|
||||
inline void compareFloat64x2(Assembler::Condition cond,
|
||||
const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
inline void compareFloat64x2(Assembler::Condition cond, FloatRegister lhs,
|
||||
const SimdConstant& rhs, FloatRegister dest)
|
||||
DEFINED_ON(x86_shared);
|
||||
|
||||
// On arm64, use any float-point comparison condition.
|
||||
|
|
@ -3237,8 +3236,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void addFloat32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void addFloat32x4(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void addFloat32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void addFloat64x2(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -3246,8 +3245,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void addFloat64x2(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void addFloat64x2(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void addFloat64x2(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
// Floating subtract
|
||||
|
||||
|
|
@ -3257,8 +3256,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void subFloat32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void subFloat32x4(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void subFloat32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void subFloat64x2(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -3266,8 +3265,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void subFloat64x2(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void subFloat64x2(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void subFloat64x2(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
// Floating division
|
||||
|
||||
|
|
@ -3277,8 +3276,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void divFloat32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void divFloat32x4(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void divFloat32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void divFloat64x2(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -3286,8 +3285,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void divFloat64x2(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void divFloat64x2(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void divFloat64x2(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
// Floating Multiply
|
||||
|
||||
|
|
@ -3297,8 +3296,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void mulFloat32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void mulFloat32x4(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void mulFloat32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void mulFloat64x2(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
|
@ -3306,8 +3305,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void mulFloat64x2(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void mulFloat64x2(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void mulFloat64x2(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
// Pairwise add
|
||||
|
||||
|
|
@ -3403,8 +3402,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void narrowInt16x8(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void narrowInt16x8(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void narrowInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void narrowInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
|
@ -3412,9 +3411,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void unsignedNarrowInt16x8(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void unsignedNarrowInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void unsignedNarrowInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void unsignedNarrowInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
|
@ -3422,8 +3420,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void narrowInt32x4(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void narrowInt32x4(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void narrowInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void narrowInt32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
|
@ -3431,9 +3429,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void unsignedNarrowInt32x4(FloatRegister rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared, arm64);
|
||||
|
||||
inline void unsignedNarrowInt32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void unsignedNarrowInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
inline void unsignedNarrowInt32x4(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
|
@ -3520,8 +3517,8 @@ class MacroAssembler : public MacroAssemblerSpecific {
|
|||
inline void widenDotInt16x8(FloatRegister lhs, FloatRegister rhs,
|
||||
FloatRegister dest) DEFINED_ON(arm64);
|
||||
|
||||
inline void widenDotInt16x8(const SimdConstant& rhs, FloatRegister lhsDest)
|
||||
DEFINED_ON(x86_shared);
|
||||
inline void widenDotInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) DEFINED_ON(x86_shared);
|
||||
|
||||
// Floating point rounding
|
||||
|
||||
|
|
|
|||
|
|
@ -1040,24 +1040,6 @@ class Assembler : public AssemblerX86Shared {
|
|||
CodeOffset loadRipRelativeFloat32x4(FloatRegister dest) {
|
||||
return CodeOffset(masm.vmovaps_ripr(dest.encoding()).offset());
|
||||
}
|
||||
CodeOffset storeRipRelativeInt32(Register dest) {
|
||||
return CodeOffset(masm.movl_rrip(dest.encoding()).offset());
|
||||
}
|
||||
CodeOffset storeRipRelativeInt64(Register dest) {
|
||||
return CodeOffset(masm.movq_rrip(dest.encoding()).offset());
|
||||
}
|
||||
CodeOffset storeRipRelativeDouble(FloatRegister dest) {
|
||||
return CodeOffset(masm.vmovsd_rrip(dest.encoding()).offset());
|
||||
}
|
||||
CodeOffset storeRipRelativeFloat32(FloatRegister dest) {
|
||||
return CodeOffset(masm.vmovss_rrip(dest.encoding()).offset());
|
||||
}
|
||||
CodeOffset storeRipRelativeInt32x4(FloatRegister dest) {
|
||||
return CodeOffset(masm.vmovdqa_rrip(dest.encoding()).offset());
|
||||
}
|
||||
CodeOffset storeRipRelativeFloat32x4(FloatRegister dest) {
|
||||
return CodeOffset(masm.vmovaps_rrip(dest.encoding()).offset());
|
||||
}
|
||||
CodeOffset leaRipRelative(Register dest) {
|
||||
return CodeOffset(masm.leaq_rip(dest.encoding()).offset());
|
||||
}
|
||||
|
|
|
|||
|
|
@ -901,286 +901,222 @@ class BaseAssemblerX64 : public BaseAssembler {
|
|||
}
|
||||
|
||||
[[nodiscard]] JmpSrc vmovsd_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, invalid_xmm,
|
||||
dst);
|
||||
return twoByteRipOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vmovss_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, invalid_xmm,
|
||||
dst);
|
||||
return twoByteRipOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vmovsd_rrip(XMMRegisterID src) {
|
||||
return twoByteRipOpSimd("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, invalid_xmm,
|
||||
src);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vmovss_rrip(XMMRegisterID src) {
|
||||
return twoByteRipOpSimd("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, invalid_xmm,
|
||||
src);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vmovdqa_rrip(XMMRegisterID src) {
|
||||
return twoByteRipOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, invalid_xmm,
|
||||
src);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vmovaps_rrip(XMMRegisterID src) {
|
||||
return twoByteRipOpSimd("vmovdqa", VEX_PS, OP2_MOVAPS_WsdVsd, invalid_xmm,
|
||||
src);
|
||||
}
|
||||
|
||||
[[nodiscard]] JmpSrc vmovaps_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, invalid_xmm,
|
||||
dst);
|
||||
return twoByteRipOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, dst);
|
||||
}
|
||||
|
||||
[[nodiscard]] JmpSrc vmovdqa_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
return twoByteRipOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, dst);
|
||||
}
|
||||
|
||||
[[nodiscard]] JmpSrc vpaddb_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddb", VEX_PD, OP2_PADDB_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpaddb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddb", VEX_PD, OP2_PADDB_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpaddw_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddw", VEX_PD, OP2_PADDW_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpaddw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddw", VEX_PD, OP2_PADDW_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpaddd_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddd", VEX_PD, OP2_PADDD_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpaddd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddd", VEX_PD, OP2_PADDD_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpaddq_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddq", VEX_PD, OP2_PADDQ_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpaddq_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddq", VEX_PD, OP2_PADDQ_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpsubb_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubb", VEX_PD, OP2_PSUBB_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpsubb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubb", VEX_PD, OP2_PSUBB_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpsubw_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubw", VEX_PD, OP2_PSUBW_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpsubw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubw", VEX_PD, OP2_PSUBW_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpsubd_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubd", VEX_PD, OP2_PSUBD_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpsubd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubd", VEX_PD, OP2_PSUBD_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpsubq_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubq", VEX_PD, OP2_PSUBQ_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpsubq_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubq", VEX_PD, OP2_PSUBQ_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpmullw_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpmullw", VEX_PD, OP2_PMULLW_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpmullw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpmullw", VEX_PD, OP2_PMULLW_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpmulld_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vpmulld_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return threeByteRipOpSimd("vpmulld", VEX_PD, OP3_PMULLD_VdqWdq, ESCAPE_38,
|
||||
invalid_xmm, dst);
|
||||
src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpaddsb_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddsb", VEX_PD, OP2_PADDSB_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpaddsb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddsb", VEX_PD, OP2_PADDSB_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpaddusb_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddusb", VEX_PD, OP2_PADDUSB_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpaddusb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddusb", VEX_PD, OP2_PADDUSB_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpaddsw_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddsw", VEX_PD, OP2_PADDSW_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpaddsw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddsw", VEX_PD, OP2_PADDSW_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpaddusw_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddusw", VEX_PD, OP2_PADDUSW_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpaddusw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpaddusw", VEX_PD, OP2_PADDUSW_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpsubsb_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubsb", VEX_PD, OP2_PSUBSB_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpsubsb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubsb", VEX_PD, OP2_PSUBSB_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpsubusb_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubusb", VEX_PD, OP2_PSUBUSB_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpsubusb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubusb", VEX_PD, OP2_PSUBUSB_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpsubsw_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubsw", VEX_PD, OP2_PSUBSW_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpsubsw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubsw", VEX_PD, OP2_PSUBSW_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpsubusw_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubusw", VEX_PD, OP2_PSUBUSW_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpsubusw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpsubusw", VEX_PD, OP2_PSUBUSW_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpminsb_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vpminsb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return threeByteRipOpSimd("vpminsb", VEX_PD, OP3_PMINSB_VdqWdq, ESCAPE_38,
|
||||
invalid_xmm, dst);
|
||||
src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpminub_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpminub", VEX_PD, OP2_PMINUB_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpminub_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpminub", VEX_PD, OP2_PMINUB_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpminsw_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpminsw", VEX_PD, OP2_PMINSW_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpminsw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpminsw", VEX_PD, OP2_PMINSW_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpminuw_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vpminuw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return threeByteRipOpSimd("vpminuw", VEX_PD, OP3_PMINUW_VdqWdq, ESCAPE_38,
|
||||
invalid_xmm, dst);
|
||||
src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpminsd_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vpminsd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return threeByteRipOpSimd("vpminsd", VEX_PD, OP3_PMINSD_VdqWdq, ESCAPE_38,
|
||||
invalid_xmm, dst);
|
||||
src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpminud_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vpminud_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return threeByteRipOpSimd("vpminud", VEX_PD, OP3_PMINUD_VdqWdq, ESCAPE_38,
|
||||
invalid_xmm, dst);
|
||||
src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpmaxsb_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vpmaxsb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return threeByteRipOpSimd("vpmaxsb", VEX_PD, OP3_PMAXSB_VdqWdq, ESCAPE_38,
|
||||
invalid_xmm, dst);
|
||||
src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpmaxub_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpmaxub", VEX_PD, OP2_PMAXUB_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpmaxub_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpmaxub", VEX_PD, OP2_PMAXUB_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpmaxsw_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpmaxsw", VEX_PD, OP2_PMAXSW_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpmaxsw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpmaxsw", VEX_PD, OP2_PMAXSW_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpmaxuw_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vpmaxuw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return threeByteRipOpSimd("vpmaxuw", VEX_PD, OP3_PMAXUW_VdqWdq, ESCAPE_38,
|
||||
invalid_xmm, dst);
|
||||
src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpmaxsd_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vpmaxsd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return threeByteRipOpSimd("vpmaxsd", VEX_PD, OP3_PMAXSD_VdqWdq, ESCAPE_38,
|
||||
invalid_xmm, dst);
|
||||
src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpmaxud_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vpmaxud_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return threeByteRipOpSimd("vpmaxud", VEX_PD, OP3_PMAXUD_VdqWdq, ESCAPE_38,
|
||||
invalid_xmm, dst);
|
||||
src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpand_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpand", VEX_PD, OP2_PANDDQ_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpand_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpand", VEX_PD, OP2_PANDDQ_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpxor_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpxor", VEX_PD, OP2_PXORDQ_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpxor_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpxor", VEX_PD, OP2_PXORDQ_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpor_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpor", VEX_PD, OP2_PORDQ_VdqWdq, invalid_xmm, dst);
|
||||
[[nodiscard]] JmpSrc vpor_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpor", VEX_PD, OP2_PORDQ_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vaddps_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vaddps", VEX_PS, OP2_ADDPS_VpsWps, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vaddps_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vaddps", VEX_PS, OP2_ADDPS_VpsWps, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vaddpd_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vaddpd", VEX_PD, OP2_ADDPD_VpdWpd, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vaddpd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vaddpd", VEX_PD, OP2_ADDPD_VpdWpd, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vsubps_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vsubps", VEX_PS, OP2_SUBPS_VpsWps, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vsubps_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vsubps", VEX_PS, OP2_SUBPS_VpsWps, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vsubpd_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vsubpd", VEX_PD, OP2_SUBPD_VpdWpd, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vsubpd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vsubpd", VEX_PD, OP2_SUBPD_VpdWpd, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vdivps_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vdivps", VEX_PS, OP2_DIVPS_VpsWps, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vdivps_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vdivps", VEX_PS, OP2_DIVPS_VpsWps, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vdivpd_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vdivpd", VEX_PD, OP2_DIVPD_VpdWpd, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vdivpd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vdivpd", VEX_PD, OP2_DIVPD_VpdWpd, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vmulps_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vmulps", VEX_PS, OP2_MULPS_VpsWps, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vmulps_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vmulps", VEX_PS, OP2_MULPS_VpsWps, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vmulpd_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vmulpd", VEX_PD, OP2_MULPD_VpdWpd, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vmulpd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vmulpd", VEX_PD, OP2_MULPD_VpdWpd, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpacksswb_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpacksswb", VEX_PD, OP2_PACKSSWB_VdqWdq,
|
||||
invalid_xmm, dst);
|
||||
[[nodiscard]] JmpSrc vpacksswb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpacksswb", VEX_PD, OP2_PACKSSWB_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpackuswb_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpackuswb", VEX_PD, OP2_PACKUSWB_VdqWdq,
|
||||
invalid_xmm, dst);
|
||||
[[nodiscard]] JmpSrc vpackuswb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpackuswb", VEX_PD, OP2_PACKUSWB_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpackssdw_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpackssdw", VEX_PD, OP2_PACKSSDW_VdqWdq,
|
||||
invalid_xmm, dst);
|
||||
[[nodiscard]] JmpSrc vpackssdw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpackssdw", VEX_PD, OP2_PACKSSDW_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpackusdw_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vpackusdw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return threeByteRipOpSimd("vpackusdw", VEX_PD, OP3_PACKUSDW_VdqWdq,
|
||||
ESCAPE_38, invalid_xmm, dst);
|
||||
ESCAPE_38, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vptest_ripr(XMMRegisterID lhs) {
|
||||
return threeByteRipOpSimd("vptest", VEX_PD, OP3_PTEST_VdVd, ESCAPE_38,
|
||||
invalid_xmm, lhs);
|
||||
return threeByteRipOpSimd("vptest", VEX_PD, OP3_PTEST_VdVd, ESCAPE_38, lhs);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpshufb_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vpshufb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return threeByteRipOpSimd("vpshufb", VEX_PD, OP3_PSHUFB_VdqWdq, ESCAPE_38,
|
||||
invalid_xmm, dst);
|
||||
src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpmaddwd_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpmaddwd", VEX_PD, OP2_PMADDWD_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpmaddwd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpmaddwd", VEX_PD, OP2_PMADDWD_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpcmpeqb_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpcmpeqb", VEX_PD, OP2_PCMPEQB_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpcmpeqb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpcmpeqb", VEX_PD, OP2_PCMPEQB_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpcmpgtb_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpcmpgtb", VEX_PD, OP2_PCMPGTB_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpcmpgtb_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpcmpgtb", VEX_PD, OP2_PCMPGTB_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpcmpeqw_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpcmpeqw", VEX_PD, OP2_PCMPEQW_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpcmpeqw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpcmpeqw", VEX_PD, OP2_PCMPEQW_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpcmpgtw_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpcmpgtw", VEX_PD, OP2_PCMPGTW_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpcmpgtw_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpcmpgtw", VEX_PD, OP2_PCMPGTW_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpcmpeqd_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpcmpeqd", VEX_PD, OP2_PCMPEQD_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpcmpeqd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpcmpeqd", VEX_PD, OP2_PCMPEQD_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vpcmpgtd_ripr(XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpcmpgtd", VEX_PD, OP2_PCMPGTD_VdqWdq, invalid_xmm,
|
||||
dst);
|
||||
[[nodiscard]] JmpSrc vpcmpgtd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpSimd("vpcmpgtd", VEX_PD, OP2_PCMPGTD_VdqWdq, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vcmpeqps_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vcmpeqps_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpImmSimd("vcmpps", VEX_PS, OP2_CMPPS_VpsWps,
|
||||
X86Encoding::ConditionCmp_EQ, invalid_xmm, dst);
|
||||
X86Encoding::ConditionCmp_EQ, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vcmpneqps_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vcmpneqps_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpImmSimd("vcmpps", VEX_PS, OP2_CMPPS_VpsWps,
|
||||
X86Encoding::ConditionCmp_NEQ, invalid_xmm, dst);
|
||||
X86Encoding::ConditionCmp_NEQ, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vcmpltps_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vcmpltps_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpImmSimd("vcmpps", VEX_PS, OP2_CMPPS_VpsWps,
|
||||
X86Encoding::ConditionCmp_LT, invalid_xmm, dst);
|
||||
X86Encoding::ConditionCmp_LT, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vcmpleps_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vcmpleps_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpImmSimd("vcmpps", VEX_PS, OP2_CMPPS_VpsWps,
|
||||
X86Encoding::ConditionCmp_LE, invalid_xmm, dst);
|
||||
X86Encoding::ConditionCmp_LE, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vcmpeqpd_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vcmpeqpd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpImmSimd("vcmppd", VEX_PD, OP2_CMPPD_VpdWpd,
|
||||
X86Encoding::ConditionCmp_EQ, invalid_xmm, dst);
|
||||
X86Encoding::ConditionCmp_EQ, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vcmpneqpd_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vcmpneqpd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpImmSimd("vcmppd", VEX_PD, OP2_CMPPD_VpdWpd,
|
||||
X86Encoding::ConditionCmp_NEQ, invalid_xmm, dst);
|
||||
X86Encoding::ConditionCmp_NEQ, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vcmpltpd_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vcmpltpd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpImmSimd("vcmppd", VEX_PD, OP2_CMPPD_VpdWpd,
|
||||
X86Encoding::ConditionCmp_LT, invalid_xmm, dst);
|
||||
X86Encoding::ConditionCmp_LT, src, dst);
|
||||
}
|
||||
[[nodiscard]] JmpSrc vcmplepd_ripr(XMMRegisterID dst) {
|
||||
[[nodiscard]] JmpSrc vcmplepd_ripr(XMMRegisterID src, XMMRegisterID dst) {
|
||||
return twoByteRipOpImmSimd("vcmppd", VEX_PD, OP2_CMPPD_VpdWpd,
|
||||
X86Encoding::ConditionCmp_LE, invalid_xmm, dst);
|
||||
X86Encoding::ConditionCmp_LE, src, dst);
|
||||
}
|
||||
|
||||
// BMI instructions:
|
||||
|
|
@ -1221,18 +1157,33 @@ class BaseAssemblerX64 : public BaseAssembler {
|
|||
private:
|
||||
[[nodiscard]] JmpSrc twoByteRipOpSimd(const char* name, VexOperandType ty,
|
||||
TwoByteOpcodeID opcode,
|
||||
XMMRegisterID src0, XMMRegisterID dst) {
|
||||
MOZ_ASSERT(src0 == invalid_xmm);
|
||||
XMMRegisterID reg) {
|
||||
MOZ_ASSERT(!IsXMMReversedOperands(opcode));
|
||||
m_formatter.legacySSEPrefix(ty);
|
||||
m_formatter.twoByteRipOp(opcode, 0, dst);
|
||||
m_formatter.twoByteRipOp(opcode, 0, reg);
|
||||
JmpSrc label(m_formatter.size());
|
||||
if (IsXMMReversedOperands(opcode)) {
|
||||
spew("%-11s%s, " MEM_o32r "", legacySSEOpName(name), XMMRegName(dst),
|
||||
ADDR_o32r(label.offset()));
|
||||
} else {
|
||||
spew("%-11s " MEM_o32r ", %s", legacySSEOpName(name),
|
||||
ADDR_o32r(label.offset()), XMMRegName(reg));
|
||||
return label;
|
||||
}
|
||||
|
||||
[[nodiscard]] JmpSrc twoByteRipOpSimd(const char* name, VexOperandType ty,
|
||||
TwoByteOpcodeID opcode,
|
||||
XMMRegisterID src0, XMMRegisterID dst) {
|
||||
MOZ_ASSERT(src0 != invalid_xmm && !IsXMMReversedOperands(opcode));
|
||||
if (useLegacySSEEncoding(src0, dst)) {
|
||||
m_formatter.legacySSEPrefix(ty);
|
||||
m_formatter.twoByteRipOp(opcode, 0, dst);
|
||||
JmpSrc label(m_formatter.size());
|
||||
spew("%-11s" MEM_o32r ", %s", legacySSEOpName(name),
|
||||
ADDR_o32r(label.offset()), XMMRegName(dst));
|
||||
return label;
|
||||
}
|
||||
|
||||
m_formatter.twoByteRipOpVex(ty, opcode, 0, src0, dst);
|
||||
JmpSrc label(m_formatter.size());
|
||||
spew("%-11s, " MEM_o32r ", %s, %s", name, ADDR_o32r(label.offset()),
|
||||
XMMRegName(src0), XMMRegName(dst));
|
||||
return label;
|
||||
}
|
||||
|
||||
|
|
@ -1240,18 +1191,24 @@ class BaseAssemblerX64 : public BaseAssembler {
|
|||
TwoByteOpcodeID opcode, uint32_t imm,
|
||||
XMMRegisterID src0,
|
||||
XMMRegisterID dst) {
|
||||
MOZ_ASSERT(src0 == invalid_xmm);
|
||||
m_formatter.legacySSEPrefix(ty);
|
||||
m_formatter.twoByteRipOp(opcode, 0, dst);
|
||||
m_formatter.immediate8u(imm);
|
||||
JmpSrc label(m_formatter.size(), /* bytes trailing the patch field = */ 1);
|
||||
if (IsXMMReversedOperands(opcode)) {
|
||||
spew("%-11s$0x%x, %s, " MEM_o32r "", legacySSEOpName(name), imm,
|
||||
XMMRegName(dst), ADDR_o32r(label.offset()));
|
||||
} else {
|
||||
MOZ_ASSERT(src0 != invalid_xmm && !IsXMMReversedOperands(opcode));
|
||||
if (useLegacySSEEncoding(src0, dst)) {
|
||||
m_formatter.legacySSEPrefix(ty);
|
||||
m_formatter.twoByteRipOp(opcode, 0, dst);
|
||||
m_formatter.immediate8u(imm);
|
||||
JmpSrc label(m_formatter.size(),
|
||||
/* bytes trailing the patch field = */ 1);
|
||||
spew("%-11s$0x%x, " MEM_o32r ", %s", legacySSEOpName(name), imm,
|
||||
ADDR_o32r(label.offset()), XMMRegName(dst));
|
||||
return label;
|
||||
}
|
||||
|
||||
m_formatter.twoByteRipOpVex(ty, opcode, 0, src0, dst);
|
||||
m_formatter.immediate8u(imm);
|
||||
JmpSrc label(m_formatter.size(),
|
||||
/* bytes trailing the patch field = */ 1);
|
||||
spew("%-11s$0x%x, " MEM_o32r ", %s, %s", name, imm,
|
||||
ADDR_o32r(label.offset()), XMMRegName(src0), XMMRegName(dst));
|
||||
return label;
|
||||
}
|
||||
|
||||
|
|
@ -1318,9 +1275,7 @@ class BaseAssemblerX64 : public BaseAssembler {
|
|||
[[nodiscard]] JmpSrc threeByteRipOpSimd(const char* name, VexOperandType ty,
|
||||
ThreeByteOpcodeID opcode,
|
||||
ThreeByteEscape escape,
|
||||
XMMRegisterID src0,
|
||||
XMMRegisterID dst) {
|
||||
MOZ_ASSERT(src0 == invalid_xmm);
|
||||
m_formatter.legacySSEPrefix(ty);
|
||||
m_formatter.threeByteRipOp(opcode, escape, 0, dst);
|
||||
JmpSrc label(m_formatter.size());
|
||||
|
|
@ -1329,6 +1284,28 @@ class BaseAssemblerX64 : public BaseAssembler {
|
|||
return label;
|
||||
}
|
||||
|
||||
[[nodiscard]] JmpSrc threeByteRipOpSimd(const char* name, VexOperandType ty,
|
||||
ThreeByteOpcodeID opcode,
|
||||
ThreeByteEscape escape,
|
||||
XMMRegisterID src0,
|
||||
XMMRegisterID dst) {
|
||||
MOZ_ASSERT(src0 != invalid_xmm);
|
||||
if (useLegacySSEEncoding(src0, dst)) {
|
||||
m_formatter.legacySSEPrefix(ty);
|
||||
m_formatter.threeByteRipOp(opcode, escape, 0, dst);
|
||||
JmpSrc label(m_formatter.size());
|
||||
spew("%-11s" MEM_o32r ", %s", legacySSEOpName(name),
|
||||
ADDR_o32r(label.offset()), XMMRegName(dst));
|
||||
return label;
|
||||
}
|
||||
|
||||
m_formatter.threeByteRipOpVex(ty, opcode, escape, 0, src0, dst);
|
||||
JmpSrc label(m_formatter.size());
|
||||
spew("%-11s" MEM_o32r ", %s, %s", name, ADDR_o32r(label.offset()),
|
||||
XMMRegName(src0), XMMRegName(dst));
|
||||
return label;
|
||||
}
|
||||
|
||||
void threeByteOpImmSimdInt64(const char* name, VexOperandType ty,
|
||||
ThreeByteOpcodeID opcode, ThreeByteEscape escape,
|
||||
uint32_t imm, XMMRegisterID src,
|
||||
|
|
|
|||
|
|
@ -64,6 +64,18 @@ void MacroAssemblerX64::vpRiprOpSimd128(
|
|||
propagateOOM(val->uses.append(j));
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpRiprOpSimd128(
|
||||
const SimdConstant& v, FloatRegister src, FloatRegister dest,
|
||||
JmpSrc (X86Encoding::BaseAssemblerX64::*op)(
|
||||
X86Encoding::XMMRegisterID srcId, X86Encoding::XMMRegisterID destId)) {
|
||||
SimdData* val = getSimdData(v);
|
||||
if (!val) {
|
||||
return;
|
||||
}
|
||||
JmpSrc j = (masm.*op)(src.encoding(), dest.encoding());
|
||||
propagateOOM(val->uses.append(j));
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::loadConstantSimd128Int(const SimdConstant& v,
|
||||
FloatRegister dest) {
|
||||
if (maybeInlineSimd128Int(v, dest)) {
|
||||
|
|
@ -80,314 +92,320 @@ void MacroAssemblerX64::loadConstantSimd128Float(const SimdConstant& v,
|
|||
vpRiprOpSimd128(v, dest, &X86Encoding::BaseAssemblerX64::vmovaps_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpaddbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpaddb_ripr);
|
||||
void MacroAssemblerX64::vpaddbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpaddb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpaddwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpaddw_ripr);
|
||||
void MacroAssemblerX64::vpaddwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpaddw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpadddSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpaddd_ripr);
|
||||
void MacroAssemblerX64::vpadddSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpaddd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpaddqSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpaddq_ripr);
|
||||
void MacroAssemblerX64::vpaddqSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpaddq_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpsubbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpsubb_ripr);
|
||||
void MacroAssemblerX64::vpsubbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpsubb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpsubwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpsubw_ripr);
|
||||
void MacroAssemblerX64::vpsubwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpsubw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpsubdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpsubd_ripr);
|
||||
void MacroAssemblerX64::vpsubdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpsubd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpsubqSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpsubq_ripr);
|
||||
void MacroAssemblerX64::vpsubqSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpsubq_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpmullwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpmullw_ripr);
|
||||
void MacroAssemblerX64::vpmullwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpmullw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpmulldSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpmulld_ripr);
|
||||
void MacroAssemblerX64::vpmulldSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpmulld_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpaddsbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpaddsb_ripr);
|
||||
void MacroAssemblerX64::vpaddsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpaddsb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpaddusbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpaddusb_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpaddusb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpaddswSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpaddsw_ripr);
|
||||
void MacroAssemblerX64::vpaddswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpaddsw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpadduswSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpaddusw_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpaddusw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpsubsbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpsubsb_ripr);
|
||||
void MacroAssemblerX64::vpsubsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpsubsb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpsubusbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpsubusb_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpsubusb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpsubswSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpsubsw_ripr);
|
||||
void MacroAssemblerX64::vpsubswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpsubsw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpsubuswSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpsubusw_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpsubusw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpminsbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpminsb_ripr);
|
||||
void MacroAssemblerX64::vpminsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpminsb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpminubSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpminub_ripr);
|
||||
void MacroAssemblerX64::vpminubSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpminub_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpminswSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpminsw_ripr);
|
||||
void MacroAssemblerX64::vpminswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpminsw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpminuwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpminuw_ripr);
|
||||
void MacroAssemblerX64::vpminuwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpminuw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpminsdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpminsd_ripr);
|
||||
void MacroAssemblerX64::vpminsdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpminsd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpminudSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpminud_ripr);
|
||||
void MacroAssemblerX64::vpminudSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpminud_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpmaxsbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpmaxsb_ripr);
|
||||
void MacroAssemblerX64::vpmaxsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpmaxsb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpmaxubSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpmaxub_ripr);
|
||||
void MacroAssemblerX64::vpmaxubSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpmaxub_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpmaxswSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpmaxsw_ripr);
|
||||
void MacroAssemblerX64::vpmaxswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpmaxsw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpmaxuwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpmaxuw_ripr);
|
||||
void MacroAssemblerX64::vpmaxuwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpmaxuw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpmaxsdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpmaxsd_ripr);
|
||||
void MacroAssemblerX64::vpmaxsdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpmaxsd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpmaxudSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpmaxud_ripr);
|
||||
void MacroAssemblerX64::vpmaxudSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpmaxud_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpandSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpand_ripr);
|
||||
void MacroAssemblerX64::vpandSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpand_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpxorSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpxor_ripr);
|
||||
void MacroAssemblerX64::vpxorSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpxor_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vporSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpor_ripr);
|
||||
void MacroAssemblerX64::vporSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpor_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vaddpsSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vaddps_ripr);
|
||||
void MacroAssemblerX64::vaddpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vaddps_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vaddpdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vaddpd_ripr);
|
||||
void MacroAssemblerX64::vaddpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vaddpd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vsubpsSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vsubps_ripr);
|
||||
void MacroAssemblerX64::vsubpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vsubps_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vsubpdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vsubpd_ripr);
|
||||
void MacroAssemblerX64::vsubpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vsubpd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vdivpsSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vdivps_ripr);
|
||||
void MacroAssemblerX64::vdivpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vdivps_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vdivpdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vdivpd_ripr);
|
||||
void MacroAssemblerX64::vdivpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vdivpd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vmulpsSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vmulps_ripr);
|
||||
void MacroAssemblerX64::vmulpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vmulps_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vmulpdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vmulpd_ripr);
|
||||
void MacroAssemblerX64::vmulpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vmulpd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpacksswbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpacksswb_ripr);
|
||||
FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpacksswb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpackuswbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpackuswb_ripr);
|
||||
FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpackuswb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpackssdwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpackssdw_ripr);
|
||||
FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpackssdw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpackusdwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpackusdw_ripr);
|
||||
FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpackusdw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpshufbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpshufb_ripr);
|
||||
void MacroAssemblerX64::vpshufbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpshufb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vptestSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vptest_ripr);
|
||||
FloatRegister lhs) {
|
||||
vpRiprOpSimd128(v, lhs, &X86Encoding::BaseAssemblerX64::vptest_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpmaddwdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpRiprOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX64::vpmaddwd_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpmaddwd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpcmpeqbSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vpcmpeqb_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpcmpeqb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpcmpgtbSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vpcmpgtb_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpcmpgtb_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpcmpeqwSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vpcmpeqw_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpcmpeqw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpcmpgtwSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vpcmpgtw_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpcmpgtw_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpcmpeqdSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vpcmpeqd_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpcmpeqd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vpcmpgtdSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vpcmpgtd_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vpcmpgtd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vcmpeqpsSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vcmpeqps_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vcmpeqps_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vcmpneqpsSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vcmpneqps_ripr);
|
||||
FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vcmpneqps_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vcmpltpsSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vcmpltps_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vcmpltps_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vcmplepsSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vcmpleps_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vcmpleps_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vcmpeqpdSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vcmpeqpd_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vcmpeqpd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vcmpneqpdSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vcmpneqpd_ripr);
|
||||
FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vcmpneqpd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vcmpltpdSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vcmpltpd_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vcmpltpd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::vcmplepdSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpRiprOpSimd128(v, src, &X86Encoding::BaseAssemblerX64::vcmplepd_ripr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vcmplepd_ripr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX64::bindOffsets(
|
||||
|
|
|
|||
|
|
@ -72,6 +72,12 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared {
|
|||
JmpSrc (X86Encoding::BaseAssemblerX64::*op)(
|
||||
X86Encoding::XMMRegisterID id));
|
||||
|
||||
void vpRiprOpSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest,
|
||||
JmpSrc (X86Encoding::BaseAssemblerX64::*op)(
|
||||
X86Encoding::XMMRegisterID srcId,
|
||||
X86Encoding::XMMRegisterID destId));
|
||||
|
||||
public:
|
||||
using MacroAssemblerX86Shared::load32;
|
||||
using MacroAssemblerX86Shared::store16;
|
||||
|
|
@ -971,68 +977,129 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared {
|
|||
|
||||
void loadConstantSimd128Int(const SimdConstant& v, FloatRegister dest);
|
||||
void loadConstantSimd128Float(const SimdConstant& v, FloatRegister dest);
|
||||
void vpaddbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpaddwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpadddSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpaddqSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubqSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmullwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmulldSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpaddsbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpaddusbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpaddswSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpadduswSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubsbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubusbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubswSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubuswSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpminsbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpminubSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpminswSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpminuwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpminsdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpminudSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmaxsbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmaxubSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmaxswSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmaxuwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmaxsdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmaxudSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpandSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpxorSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vporSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vaddpsSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vaddpdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vsubpsSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vsubpdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vdivpsSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vdivpdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vmulpsSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vmulpdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpacksswbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpackuswbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpackssdwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpackusdwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpshufbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vptestSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpmaddwdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpcmpeqbSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpcmpgtbSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpcmpeqwSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpcmpgtwSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpcmpeqdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpcmpgtdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmpeqpsSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmpneqpsSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmpltpsSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmplepsSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmpeqpdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmpneqpdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmpltpdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmplepdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpaddbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpaddwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpadddSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpaddqSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubqSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmullwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmulldSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpaddsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpaddusbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpaddswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpadduswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubusbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubuswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpminsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpminubSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpminswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpminuwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpminsdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpminudSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmaxsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmaxubSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmaxswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmaxuwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmaxsdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmaxudSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpandSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpxorSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vporSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vaddpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vaddpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vsubpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vsubpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vdivpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vdivpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vmulpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vmulpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpacksswbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpackuswbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpackssdwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpackusdwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpshufbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vptestSimd128(const SimdConstant& v, FloatRegister lhs);
|
||||
void vpmaddwdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpcmpeqbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpcmpgtbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpcmpeqwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpcmpgtwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpcmpeqdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpcmpgtdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmpeqpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmpneqpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmpltpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmplepsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmpeqpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmpneqpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmpltpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmplepdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
|
||||
void loadWasmPinnedRegsFromTls() {
|
||||
loadPtr(Address(WasmTlsReg, offsetof(wasm::TlsData, memoryBase)), HeapReg);
|
||||
|
|
|
|||
|
|
@ -2724,33 +2724,33 @@ class AssemblerX86Shared : public AssemblerShared {
|
|||
void vcmpordps(const Operand& rhs, FloatRegister lhs, FloatRegister dest) {
|
||||
vcmpps(X86Encoding::ConditionCmp_ORD, rhs, lhs, dest);
|
||||
}
|
||||
void vcmppd(uint8_t order, Operand rhs, FloatRegister srcDest) {
|
||||
void vcmppd(uint8_t order, Operand rhs, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
switch (rhs.kind()) {
|
||||
case Operand::FPREG:
|
||||
masm.vcmppd_rr(order, rhs.fpu(), srcDest.encoding(),
|
||||
srcDest.encoding());
|
||||
masm.vcmppd_rr(order, rhs.fpu(), lhs.encoding(), dest.encoding());
|
||||
break;
|
||||
default:
|
||||
MOZ_CRASH("NYI");
|
||||
}
|
||||
}
|
||||
void vcmpeqpd(const Operand& rhs, FloatRegister srcDest) {
|
||||
vcmppd(X86Encoding::ConditionCmp_EQ, rhs, srcDest);
|
||||
void vcmpeqpd(const Operand& rhs, FloatRegister lhs, FloatRegister dest) {
|
||||
vcmppd(X86Encoding::ConditionCmp_EQ, rhs, lhs, dest);
|
||||
}
|
||||
void vcmpltpd(const Operand& rhs, FloatRegister srcDest) {
|
||||
vcmppd(X86Encoding::ConditionCmp_LT, rhs, srcDest);
|
||||
void vcmpltpd(const Operand& rhs, FloatRegister lhs, FloatRegister dest) {
|
||||
vcmppd(X86Encoding::ConditionCmp_LT, rhs, lhs, dest);
|
||||
}
|
||||
void vcmplepd(const Operand& rhs, FloatRegister srcDest) {
|
||||
vcmppd(X86Encoding::ConditionCmp_LE, rhs, srcDest);
|
||||
void vcmplepd(const Operand& rhs, FloatRegister lhs, FloatRegister dest) {
|
||||
vcmppd(X86Encoding::ConditionCmp_LE, rhs, lhs, dest);
|
||||
}
|
||||
void vcmpneqpd(const Operand& rhs, FloatRegister srcDest) {
|
||||
vcmppd(X86Encoding::ConditionCmp_NEQ, rhs, srcDest);
|
||||
void vcmpneqpd(const Operand& rhs, FloatRegister lhs, FloatRegister dest) {
|
||||
vcmppd(X86Encoding::ConditionCmp_NEQ, rhs, lhs, dest);
|
||||
}
|
||||
void vcmpordpd(const Operand& rhs, FloatRegister srcDest) {
|
||||
vcmppd(X86Encoding::ConditionCmp_ORD, rhs, srcDest);
|
||||
void vcmpordpd(const Operand& rhs, FloatRegister lhs, FloatRegister dest) {
|
||||
vcmppd(X86Encoding::ConditionCmp_ORD, rhs, lhs, dest);
|
||||
}
|
||||
void vcmpunordpd(const Operand& rhs, FloatRegister srcDest) {
|
||||
vcmppd(X86Encoding::ConditionCmp_UNORD, rhs, srcDest);
|
||||
void vcmpunordpd(const Operand& rhs, FloatRegister lhs, FloatRegister dest) {
|
||||
vcmppd(X86Encoding::ConditionCmp_UNORD, rhs, lhs, dest);
|
||||
}
|
||||
void vrcpps(const Operand& src, FloatRegister dest) {
|
||||
MOZ_ASSERT(HasSSE2());
|
||||
|
|
|
|||
|
|
@ -5710,6 +5710,27 @@ class BaseAssembler : public GenericAssembler {
|
|||
memoryModRM(address, reg);
|
||||
}
|
||||
|
||||
void threeByteRipOpVex(VexOperandType ty, ThreeByteOpcodeID opcode,
|
||||
ThreeByteEscape escape, int ripOffset,
|
||||
XMMRegisterID src0, int reg) {
|
||||
int r = (reg >> 3), x = 0, b = 0;
|
||||
int m = 0;
|
||||
switch (escape) {
|
||||
case ESCAPE_38:
|
||||
m = 2;
|
||||
break;
|
||||
case ESCAPE_3A:
|
||||
m = 3;
|
||||
break;
|
||||
default:
|
||||
MOZ_CRASH("unexpected escape");
|
||||
}
|
||||
int w = 0, v = src0, l = 0;
|
||||
threeOpVex(ty, r, x, b, m, w, v, l, opcode);
|
||||
putModRm(ModRmMemoryNoDisp, noBase, reg);
|
||||
m_buffer.putIntUnchecked(ripOffset);
|
||||
}
|
||||
|
||||
void vblendvOpVex(VexOperandType ty, ThreeByteOpcodeID opcode,
|
||||
ThreeByteEscape escape, XMMRegisterID mask, RegisterID rm,
|
||||
XMMRegisterID src0, int reg) {
|
||||
|
|
|
|||
|
|
@ -2711,209 +2711,208 @@ void CodeGenerator::visitWasmBinarySimd128(LWasmBinarySimd128* ins) {
|
|||
void CodeGenerator::visitWasmBinarySimd128WithConstant(
|
||||
LWasmBinarySimd128WithConstant* ins) {
|
||||
#ifdef ENABLE_WASM_SIMD
|
||||
FloatRegister lhsDest = ToFloatRegister(ins->lhsDest());
|
||||
FloatRegister lhs = ToFloatRegister(ins->lhsDest());
|
||||
const SimdConstant& rhs = ins->rhs();
|
||||
|
||||
MOZ_ASSERT(ToFloatRegister(ins->output()) == lhsDest);
|
||||
FloatRegister dest = ToFloatRegister(ins->output());
|
||||
|
||||
switch (ins->simdOp()) {
|
||||
case wasm::SimdOp::I8x16Add:
|
||||
masm.addInt8x16(rhs, lhsDest);
|
||||
masm.addInt8x16(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8Add:
|
||||
masm.addInt16x8(rhs, lhsDest);
|
||||
masm.addInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I32x4Add:
|
||||
masm.addInt32x4(rhs, lhsDest);
|
||||
masm.addInt32x4(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I64x2Add:
|
||||
masm.addInt64x2(rhs, lhsDest);
|
||||
masm.addInt64x2(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16Sub:
|
||||
masm.subInt8x16(rhs, lhsDest);
|
||||
masm.subInt8x16(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8Sub:
|
||||
masm.subInt16x8(rhs, lhsDest);
|
||||
masm.subInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I32x4Sub:
|
||||
masm.subInt32x4(rhs, lhsDest);
|
||||
masm.subInt32x4(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I64x2Sub:
|
||||
masm.subInt64x2(rhs, lhsDest);
|
||||
masm.subInt64x2(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8Mul:
|
||||
masm.mulInt16x8(rhs, lhsDest);
|
||||
masm.mulInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I32x4Mul:
|
||||
masm.mulInt32x4(rhs, lhsDest);
|
||||
masm.mulInt32x4(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16AddSatS:
|
||||
masm.addSatInt8x16(rhs, lhsDest);
|
||||
masm.addSatInt8x16(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16AddSatU:
|
||||
masm.unsignedAddSatInt8x16(rhs, lhsDest);
|
||||
masm.unsignedAddSatInt8x16(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8AddSatS:
|
||||
masm.addSatInt16x8(rhs, lhsDest);
|
||||
masm.addSatInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8AddSatU:
|
||||
masm.unsignedAddSatInt16x8(rhs, lhsDest);
|
||||
masm.unsignedAddSatInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16SubSatS:
|
||||
masm.subSatInt8x16(rhs, lhsDest);
|
||||
masm.subSatInt8x16(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16SubSatU:
|
||||
masm.unsignedSubSatInt8x16(rhs, lhsDest);
|
||||
masm.unsignedSubSatInt8x16(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8SubSatS:
|
||||
masm.subSatInt16x8(rhs, lhsDest);
|
||||
masm.subSatInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8SubSatU:
|
||||
masm.unsignedSubSatInt16x8(rhs, lhsDest);
|
||||
masm.unsignedSubSatInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16MinS:
|
||||
masm.minInt8x16(rhs, lhsDest);
|
||||
masm.minInt8x16(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16MinU:
|
||||
masm.unsignedMinInt8x16(rhs, lhsDest);
|
||||
masm.unsignedMinInt8x16(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8MinS:
|
||||
masm.minInt16x8(rhs, lhsDest);
|
||||
masm.minInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8MinU:
|
||||
masm.unsignedMinInt16x8(rhs, lhsDest);
|
||||
masm.unsignedMinInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I32x4MinS:
|
||||
masm.minInt32x4(rhs, lhsDest);
|
||||
masm.minInt32x4(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I32x4MinU:
|
||||
masm.unsignedMinInt32x4(rhs, lhsDest);
|
||||
masm.unsignedMinInt32x4(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16MaxS:
|
||||
masm.maxInt8x16(rhs, lhsDest);
|
||||
masm.maxInt8x16(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16MaxU:
|
||||
masm.unsignedMaxInt8x16(rhs, lhsDest);
|
||||
masm.unsignedMaxInt8x16(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8MaxS:
|
||||
masm.maxInt16x8(rhs, lhsDest);
|
||||
masm.maxInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8MaxU:
|
||||
masm.unsignedMaxInt16x8(rhs, lhsDest);
|
||||
masm.unsignedMaxInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I32x4MaxS:
|
||||
masm.maxInt32x4(rhs, lhsDest);
|
||||
masm.maxInt32x4(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I32x4MaxU:
|
||||
masm.unsignedMaxInt32x4(rhs, lhsDest);
|
||||
masm.unsignedMaxInt32x4(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::V128And:
|
||||
masm.bitwiseAndSimd128(rhs, lhsDest);
|
||||
masm.bitwiseAndSimd128(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::V128Or:
|
||||
masm.bitwiseOrSimd128(rhs, lhsDest);
|
||||
masm.bitwiseOrSimd128(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::V128Xor:
|
||||
masm.bitwiseXorSimd128(rhs, lhsDest);
|
||||
masm.bitwiseXorSimd128(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16Eq:
|
||||
masm.compareInt8x16(Assembler::Equal, rhs, lhsDest);
|
||||
masm.compareInt8x16(Assembler::Equal, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16Ne:
|
||||
masm.compareInt8x16(Assembler::NotEqual, rhs, lhsDest);
|
||||
masm.compareInt8x16(Assembler::NotEqual, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16GtS:
|
||||
masm.compareInt8x16(Assembler::GreaterThan, rhs, lhsDest);
|
||||
masm.compareInt8x16(Assembler::GreaterThan, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16LeS:
|
||||
masm.compareInt8x16(Assembler::LessThanOrEqual, rhs, lhsDest);
|
||||
masm.compareInt8x16(Assembler::LessThanOrEqual, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8Eq:
|
||||
masm.compareInt16x8(Assembler::Equal, rhs, lhsDest);
|
||||
masm.compareInt16x8(Assembler::Equal, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8Ne:
|
||||
masm.compareInt16x8(Assembler::NotEqual, rhs, lhsDest);
|
||||
masm.compareInt16x8(Assembler::NotEqual, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8GtS:
|
||||
masm.compareInt16x8(Assembler::GreaterThan, rhs, lhsDest);
|
||||
masm.compareInt16x8(Assembler::GreaterThan, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8LeS:
|
||||
masm.compareInt16x8(Assembler::LessThanOrEqual, rhs, lhsDest);
|
||||
masm.compareInt16x8(Assembler::LessThanOrEqual, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I32x4Eq:
|
||||
masm.compareInt32x4(Assembler::Equal, rhs, lhsDest);
|
||||
masm.compareInt32x4(Assembler::Equal, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I32x4Ne:
|
||||
masm.compareInt32x4(Assembler::NotEqual, rhs, lhsDest);
|
||||
masm.compareInt32x4(Assembler::NotEqual, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I32x4GtS:
|
||||
masm.compareInt32x4(Assembler::GreaterThan, rhs, lhsDest);
|
||||
masm.compareInt32x4(Assembler::GreaterThan, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I32x4LeS:
|
||||
masm.compareInt32x4(Assembler::LessThanOrEqual, rhs, lhsDest);
|
||||
masm.compareInt32x4(Assembler::LessThanOrEqual, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F32x4Eq:
|
||||
masm.compareFloat32x4(Assembler::Equal, rhs, lhsDest);
|
||||
masm.compareFloat32x4(Assembler::Equal, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F32x4Ne:
|
||||
masm.compareFloat32x4(Assembler::NotEqual, rhs, lhsDest);
|
||||
masm.compareFloat32x4(Assembler::NotEqual, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F32x4Lt:
|
||||
masm.compareFloat32x4(Assembler::LessThan, rhs, lhsDest);
|
||||
masm.compareFloat32x4(Assembler::LessThan, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F32x4Le:
|
||||
masm.compareFloat32x4(Assembler::LessThanOrEqual, rhs, lhsDest);
|
||||
masm.compareFloat32x4(Assembler::LessThanOrEqual, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F64x2Eq:
|
||||
masm.compareFloat64x2(Assembler::Equal, rhs, lhsDest);
|
||||
masm.compareFloat64x2(Assembler::Equal, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F64x2Ne:
|
||||
masm.compareFloat64x2(Assembler::NotEqual, rhs, lhsDest);
|
||||
masm.compareFloat64x2(Assembler::NotEqual, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F64x2Lt:
|
||||
masm.compareFloat64x2(Assembler::LessThan, rhs, lhsDest);
|
||||
masm.compareFloat64x2(Assembler::LessThan, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F64x2Le:
|
||||
masm.compareFloat64x2(Assembler::LessThanOrEqual, rhs, lhsDest);
|
||||
masm.compareFloat64x2(Assembler::LessThanOrEqual, lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I32x4DotI16x8S:
|
||||
masm.widenDotInt16x8(rhs, lhsDest);
|
||||
masm.widenDotInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F32x4Add:
|
||||
masm.addFloat32x4(rhs, lhsDest);
|
||||
masm.addFloat32x4(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F64x2Add:
|
||||
masm.addFloat64x2(rhs, lhsDest);
|
||||
masm.addFloat64x2(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F32x4Sub:
|
||||
masm.subFloat32x4(rhs, lhsDest);
|
||||
masm.subFloat32x4(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F64x2Sub:
|
||||
masm.subFloat64x2(rhs, lhsDest);
|
||||
masm.subFloat64x2(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F32x4Div:
|
||||
masm.divFloat32x4(rhs, lhsDest);
|
||||
masm.divFloat32x4(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F64x2Div:
|
||||
masm.divFloat64x2(rhs, lhsDest);
|
||||
masm.divFloat64x2(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F32x4Mul:
|
||||
masm.mulFloat32x4(rhs, lhsDest);
|
||||
masm.mulFloat32x4(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::F64x2Mul:
|
||||
masm.mulFloat64x2(rhs, lhsDest);
|
||||
masm.mulFloat64x2(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16NarrowI16x8S:
|
||||
masm.narrowInt16x8(rhs, lhsDest);
|
||||
masm.narrowInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I8x16NarrowI16x8U:
|
||||
masm.unsignedNarrowInt16x8(rhs, lhsDest);
|
||||
masm.unsignedNarrowInt16x8(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8NarrowI32x4S:
|
||||
masm.narrowInt32x4(rhs, lhsDest);
|
||||
masm.narrowInt32x4(lhs, rhs, dest);
|
||||
break;
|
||||
case wasm::SimdOp::I16x8NarrowI32x4U:
|
||||
masm.unsignedNarrowInt32x4(rhs, lhsDest);
|
||||
masm.unsignedNarrowInt32x4(lhs, rhs, dest);
|
||||
break;
|
||||
default:
|
||||
MOZ_CRASH("Binary SimdOp with constant not implemented");
|
||||
|
|
|
|||
|
|
@ -1159,13 +1159,21 @@ void LIRGenerator::visitWasmBinarySimd128WithConstant(
|
|||
MOZ_ASSERT(lhs->type() == MIRType::Simd128);
|
||||
MOZ_ASSERT(ins->type() == MIRType::Simd128);
|
||||
|
||||
// Always beneficial to reuse the lhs register here, see discussion in
|
||||
// visitWasmBinarySimd128() and also code in specializeForConstantRhs().
|
||||
|
||||
LAllocation lhsDestAlloc = useRegisterAtStart(lhs);
|
||||
auto* lir =
|
||||
new (alloc()) LWasmBinarySimd128WithConstant(lhsDestAlloc, ins->rhs());
|
||||
defineReuseInput(lir, ins, LWasmBinarySimd128WithConstant::LhsDest);
|
||||
if (isThreeOpAllowed()) {
|
||||
// The non-destructive versions of instructions will be available
|
||||
// when AVX is enabled.
|
||||
LAllocation lhsAlloc = useRegisterAtStart(lhs);
|
||||
auto* lir =
|
||||
new (alloc()) LWasmBinarySimd128WithConstant(lhsAlloc, ins->rhs());
|
||||
define(lir, ins);
|
||||
} else {
|
||||
// Always beneficial to reuse the lhs register here, see discussion in
|
||||
// visitWasmBinarySimd128() and also code in specializeForConstantRhs().
|
||||
LAllocation lhsDestAlloc = useRegisterAtStart(lhs);
|
||||
auto* lir =
|
||||
new (alloc()) LWasmBinarySimd128WithConstant(lhsDestAlloc, ins->rhs());
|
||||
defineReuseInput(lir, ins, LWasmBinarySimd128WithConstant::LhsDest);
|
||||
}
|
||||
#else
|
||||
MOZ_CRASH("No SIMD");
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -89,7 +89,9 @@ void MacroAssemblerX86Shared::extractLaneFloat32x4(FloatRegister input,
|
|||
moveHighPairToLowPairFloat32(input, output);
|
||||
} else {
|
||||
uint32_t mask = MacroAssembler::ComputeShuffleMask(lane);
|
||||
shuffleFloat32(mask, input, output.asSimd128());
|
||||
FloatRegister dest = output.asSimd128();
|
||||
input = moveSimd128FloatIfNotAVX(input, dest);
|
||||
vshufps(mask, input, input, dest);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -210,15 +212,15 @@ void MacroAssemblerX86Shared::shuffleInt8x16(FloatRegister lhs,
|
|||
for (unsigned i = 0; i < 16; i++) {
|
||||
idx[i] = lanes[i] >= 16 ? lanes[i] - 16 : -1;
|
||||
}
|
||||
moveSimd128Int(rhs, scratch);
|
||||
asMasm().vpshufbSimd128(SimdConstant::CreateX16(idx), scratch);
|
||||
rhs = moveSimd128IntIfNotAVX(rhs, scratch);
|
||||
asMasm().vpshufbSimd128(SimdConstant::CreateX16(idx), rhs, scratch);
|
||||
|
||||
// Set output = lanes from lhs.
|
||||
for (unsigned i = 0; i < 16; i++) {
|
||||
idx[i] = lanes[i] < 16 ? lanes[i] : -1;
|
||||
}
|
||||
moveSimd128Int(lhs, output);
|
||||
asMasm().vpshufbSimd128(SimdConstant::CreateX16(idx), output);
|
||||
lhs = moveSimd128IntIfNotAVX(lhs, output);
|
||||
asMasm().vpshufbSimd128(SimdConstant::CreateX16(idx), lhs, output);
|
||||
|
||||
// Combine.
|
||||
vpor(scratch, output, output);
|
||||
|
|
@ -255,7 +257,7 @@ void MacroAssemblerX86Shared::compareInt8x16(FloatRegister lhs, Operand rhs,
|
|||
}
|
||||
case Assembler::Condition::NotEqual:
|
||||
vpcmpeqb(rhs, lhs, output);
|
||||
asMasm().bitwiseXorSimd128(allOnes, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::Condition::GreaterThanOrEqual: {
|
||||
ScratchSimd128Scope scratch(asMasm());
|
||||
|
|
@ -274,12 +276,12 @@ void MacroAssemblerX86Shared::compareInt8x16(FloatRegister lhs, Operand rhs,
|
|||
case Assembler::Condition::LessThanOrEqual:
|
||||
// lhs <= rhs is equivalent to !(rhs < lhs), which we compute here.
|
||||
vpcmpgtb(rhs, lhs, output);
|
||||
asMasm().bitwiseXorSimd128(allOnes, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::Above:
|
||||
vpmaxub(rhs, lhs, output);
|
||||
vpcmpeqb(rhs, output, output);
|
||||
asMasm().bitwiseXorSimd128(allOnes, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::BelowOrEqual:
|
||||
vpmaxub(rhs, lhs, output);
|
||||
|
|
@ -288,7 +290,7 @@ void MacroAssemblerX86Shared::compareInt8x16(FloatRegister lhs, Operand rhs,
|
|||
case Assembler::Below:
|
||||
vpminub(rhs, lhs, output);
|
||||
vpcmpeqb(rhs, output, output);
|
||||
asMasm().bitwiseXorSimd128(allOnes, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::AboveOrEqual:
|
||||
vpminub(rhs, lhs, output);
|
||||
|
|
@ -300,29 +302,30 @@ void MacroAssemblerX86Shared::compareInt8x16(FloatRegister lhs, Operand rhs,
|
|||
}
|
||||
|
||||
void MacroAssemblerX86Shared::compareInt8x16(Assembler::Condition cond,
|
||||
FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
FloatRegister dest) {
|
||||
bool complement = false;
|
||||
switch (cond) {
|
||||
case Assembler::Condition::NotEqual:
|
||||
complement = true;
|
||||
[[fallthrough]];
|
||||
case Assembler::Condition::Equal:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpcmpeqb,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpcmpeqb,
|
||||
&MacroAssembler::vpcmpeqbSimd128);
|
||||
break;
|
||||
case Assembler::Condition::LessThanOrEqual:
|
||||
complement = true;
|
||||
[[fallthrough]];
|
||||
case Assembler::Condition::GreaterThan:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpcmpgtb,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpcmpgtb,
|
||||
&MacroAssembler::vpcmpgtbSimd128);
|
||||
break;
|
||||
default:
|
||||
MOZ_CRASH("unexpected condition op");
|
||||
}
|
||||
if (complement) {
|
||||
asMasm().bitwiseXorSimd128(SimdConstant::SplatX16(-1), lhsDest);
|
||||
asMasm().bitwiseXorSimd128(dest, SimdConstant::SplatX16(-1), dest);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -354,7 +357,7 @@ void MacroAssemblerX86Shared::compareInt16x8(FloatRegister lhs, Operand rhs,
|
|||
}
|
||||
case Assembler::Condition::NotEqual:
|
||||
vpcmpeqw(rhs, lhs, output);
|
||||
asMasm().bitwiseXorSimd128(allOnes, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::Condition::GreaterThanOrEqual: {
|
||||
ScratchSimd128Scope scratch(asMasm());
|
||||
|
|
@ -373,12 +376,12 @@ void MacroAssemblerX86Shared::compareInt16x8(FloatRegister lhs, Operand rhs,
|
|||
case Assembler::Condition::LessThanOrEqual:
|
||||
// lhs <= rhs is equivalent to !(rhs < lhs), which we compute here.
|
||||
vpcmpgtw(rhs, lhs, output);
|
||||
asMasm().bitwiseXorSimd128(allOnes, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::Above:
|
||||
vpmaxuw(rhs, lhs, output);
|
||||
vpcmpeqw(rhs, output, output);
|
||||
asMasm().bitwiseXorSimd128(allOnes, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::BelowOrEqual:
|
||||
vpmaxuw(rhs, lhs, output);
|
||||
|
|
@ -387,7 +390,7 @@ void MacroAssemblerX86Shared::compareInt16x8(FloatRegister lhs, Operand rhs,
|
|||
case Assembler::Below:
|
||||
vpminuw(rhs, lhs, output);
|
||||
vpcmpeqw(rhs, output, output);
|
||||
asMasm().bitwiseXorSimd128(allOnes, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::AboveOrEqual:
|
||||
vpminuw(rhs, lhs, lhs);
|
||||
|
|
@ -399,29 +402,30 @@ void MacroAssemblerX86Shared::compareInt16x8(FloatRegister lhs, Operand rhs,
|
|||
}
|
||||
|
||||
void MacroAssemblerX86Shared::compareInt16x8(Assembler::Condition cond,
|
||||
FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
FloatRegister dest) {
|
||||
bool complement = false;
|
||||
switch (cond) {
|
||||
case Assembler::Condition::NotEqual:
|
||||
complement = true;
|
||||
[[fallthrough]];
|
||||
case Assembler::Condition::Equal:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpcmpeqw,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpcmpeqw,
|
||||
&MacroAssembler::vpcmpeqwSimd128);
|
||||
break;
|
||||
case Assembler::Condition::LessThanOrEqual:
|
||||
complement = true;
|
||||
[[fallthrough]];
|
||||
case Assembler::Condition::GreaterThan:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpcmpgtw,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpcmpgtw,
|
||||
&MacroAssembler::vpcmpgtwSimd128);
|
||||
break;
|
||||
default:
|
||||
MOZ_CRASH("unexpected condition op");
|
||||
}
|
||||
if (complement) {
|
||||
asMasm().bitwiseXorSimd128(SimdConstant::SplatX16(-1), lhsDest);
|
||||
asMasm().bitwiseXorSimd128(dest, SimdConstant::SplatX16(-1), dest);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -452,7 +456,7 @@ void MacroAssemblerX86Shared::compareInt32x4(FloatRegister lhs, Operand rhs,
|
|||
}
|
||||
case Assembler::Condition::NotEqual:
|
||||
vpcmpeqd(rhs, lhs, output);
|
||||
asMasm().bitwiseXorSimd128(allOnes, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::Condition::GreaterThanOrEqual: {
|
||||
ScratchSimd128Scope scratch(asMasm());
|
||||
|
|
@ -471,7 +475,7 @@ void MacroAssemblerX86Shared::compareInt32x4(FloatRegister lhs, Operand rhs,
|
|||
case Assembler::Condition::LessThanOrEqual:
|
||||
// lhs <= rhs is equivalent to !(rhs < lhs), which we compute here.
|
||||
vpcmpgtd(rhs, lhs, output);
|
||||
asMasm().bitwiseXorSimd128(allOnes, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::Above:
|
||||
if (rhs.kind() == Operand::FPREG && ToSimdFloatRegister(rhs) == output) {
|
||||
|
|
@ -481,7 +485,7 @@ void MacroAssemblerX86Shared::compareInt32x4(FloatRegister lhs, Operand rhs,
|
|||
vpmaxud(rhs, lhs, output);
|
||||
vpcmpeqd(rhs, output, output);
|
||||
}
|
||||
asMasm().bitwiseXorSimd128(allOnes, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::BelowOrEqual:
|
||||
if (rhs.kind() == Operand::FPREG && ToSimdFloatRegister(rhs) == output) {
|
||||
|
|
@ -500,7 +504,7 @@ void MacroAssemblerX86Shared::compareInt32x4(FloatRegister lhs, Operand rhs,
|
|||
vpminud(rhs, lhs, output);
|
||||
vpcmpeqd(rhs, output, output);
|
||||
}
|
||||
asMasm().bitwiseXorSimd128(allOnes, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::AboveOrEqual:
|
||||
if (rhs.kind() == Operand::FPREG && ToSimdFloatRegister(rhs) == output) {
|
||||
|
|
@ -517,29 +521,30 @@ void MacroAssemblerX86Shared::compareInt32x4(FloatRegister lhs, Operand rhs,
|
|||
}
|
||||
|
||||
void MacroAssemblerX86Shared::compareInt32x4(Assembler::Condition cond,
|
||||
FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
FloatRegister dest) {
|
||||
bool complement = false;
|
||||
switch (cond) {
|
||||
case Assembler::Condition::NotEqual:
|
||||
complement = true;
|
||||
[[fallthrough]];
|
||||
case Assembler::Condition::Equal:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpcmpeqd,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpcmpeqd,
|
||||
&MacroAssembler::vpcmpeqdSimd128);
|
||||
break;
|
||||
case Assembler::Condition::LessThanOrEqual:
|
||||
complement = true;
|
||||
[[fallthrough]];
|
||||
case Assembler::Condition::GreaterThan:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpcmpgtd,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpcmpgtd,
|
||||
&MacroAssembler::vpcmpgtdSimd128);
|
||||
break;
|
||||
default:
|
||||
MOZ_CRASH("unexpected condition op");
|
||||
}
|
||||
if (complement) {
|
||||
asMasm().bitwiseXorSimd128(SimdConstant::SplatX16(-1), lhsDest);
|
||||
asMasm().bitwiseXorSimd128(dest, SimdConstant::SplatX16(-1), dest);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -549,11 +554,11 @@ void MacroAssemblerX86Shared::compareForEqualityInt64x2(
|
|||
static const SimdConstant allOnes = SimdConstant::SplatX4(-1);
|
||||
switch (cond) {
|
||||
case Assembler::Condition::Equal:
|
||||
vpcmpeqq(rhs, lhs, lhs);
|
||||
vpcmpeqq(rhs, lhs, output);
|
||||
break;
|
||||
case Assembler::Condition::NotEqual:
|
||||
vpcmpeqq(rhs, lhs, lhs);
|
||||
asMasm().bitwiseXorSimd128(allOnes, lhs);
|
||||
vpcmpeqq(rhs, lhs, output);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
default:
|
||||
MOZ_CRASH("unexpected condition op");
|
||||
|
|
@ -604,7 +609,7 @@ void MacroAssemblerX86Shared::compareForOrderingInt64x2(
|
|||
vandpd(temp2, output, output);
|
||||
vpor(Operand(temp1), output, output);
|
||||
vpshufd(MacroAssembler::ComputeShuffleMask(1, 1, 3, 3), output, output);
|
||||
asMasm().bitwiseXorSimd128(allOnes, lhs);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
case Assembler::Condition::LessThanOrEqual:
|
||||
vmovdqa(rhs, temp1);
|
||||
|
|
@ -616,7 +621,7 @@ void MacroAssemblerX86Shared::compareForOrderingInt64x2(
|
|||
vpcmpgtd(rhs, output, output);
|
||||
vpor(Operand(temp1), output, output);
|
||||
vpshufd(MacroAssembler::ComputeShuffleMask(1, 1, 3, 3), output, output);
|
||||
asMasm().bitwiseXorSimd128(allOnes, lhs);
|
||||
asMasm().bitwiseXorSimd128(output, allOnes, output);
|
||||
break;
|
||||
default:
|
||||
MOZ_CRASH("unexpected condition op");
|
||||
|
|
@ -665,23 +670,24 @@ void MacroAssemblerX86Shared::compareFloat32x4(FloatRegister lhs, Operand rhs,
|
|||
}
|
||||
|
||||
void MacroAssemblerX86Shared::compareFloat32x4(Assembler::Condition cond,
|
||||
FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
FloatRegister dest) {
|
||||
switch (cond) {
|
||||
case Assembler::Condition::Equal:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vcmpeqps,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vcmpeqps,
|
||||
&MacroAssembler::vcmpeqpsSimd128);
|
||||
break;
|
||||
case Assembler::Condition::LessThan:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vcmpltps,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vcmpltps,
|
||||
&MacroAssembler::vcmpltpsSimd128);
|
||||
break;
|
||||
case Assembler::Condition::LessThanOrEqual:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vcmpleps,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vcmpleps,
|
||||
&MacroAssembler::vcmplepsSimd128);
|
||||
break;
|
||||
case Assembler::Condition::NotEqual:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vcmpneqps,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vcmpneqps,
|
||||
&MacroAssembler::vcmpneqpsSimd128);
|
||||
break;
|
||||
default:
|
||||
|
|
@ -708,16 +714,16 @@ void MacroAssemblerX86Shared::compareFloat64x2(FloatRegister lhs, Operand rhs,
|
|||
|
||||
switch (cond) {
|
||||
case Assembler::Condition::Equal:
|
||||
vcmpeqpd(rhs, output);
|
||||
vcmpeqpd(rhs, output, output);
|
||||
break;
|
||||
case Assembler::Condition::LessThan:
|
||||
vcmpltpd(rhs, output);
|
||||
vcmpltpd(rhs, output, output);
|
||||
break;
|
||||
case Assembler::Condition::LessThanOrEqual:
|
||||
vcmplepd(rhs, output);
|
||||
vcmplepd(rhs, output, output);
|
||||
break;
|
||||
case Assembler::Condition::NotEqual:
|
||||
vcmpneqpd(rhs, output);
|
||||
vcmpneqpd(rhs, output, output);
|
||||
break;
|
||||
case Assembler::Condition::GreaterThanOrEqual:
|
||||
case Assembler::Condition::GreaterThan:
|
||||
|
|
@ -730,23 +736,24 @@ void MacroAssemblerX86Shared::compareFloat64x2(FloatRegister lhs, Operand rhs,
|
|||
}
|
||||
|
||||
void MacroAssemblerX86Shared::compareFloat64x2(Assembler::Condition cond,
|
||||
FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
FloatRegister dest) {
|
||||
switch (cond) {
|
||||
case Assembler::Condition::Equal:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vcmpeqpd,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vcmpeqpd,
|
||||
&MacroAssembler::vcmpeqpdSimd128);
|
||||
break;
|
||||
case Assembler::Condition::LessThan:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vcmpltpd,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vcmpltpd,
|
||||
&MacroAssembler::vcmpltpdSimd128);
|
||||
break;
|
||||
case Assembler::Condition::LessThanOrEqual:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vcmplepd,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vcmplepd,
|
||||
&MacroAssembler::vcmplepdSimd128);
|
||||
break;
|
||||
case Assembler::Condition::NotEqual:
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vcmpneqpd,
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vcmpneqpd,
|
||||
&MacroAssembler::vcmpneqpdSimd128);
|
||||
break;
|
||||
default:
|
||||
|
|
@ -791,7 +798,7 @@ void MacroAssemblerX86Shared::compareFloat64x2(Assembler::Condition cond,
|
|||
// fast path should be fine modulo the QNaN bits, but it's not obvious this is
|
||||
// much of an advantage.
|
||||
|
||||
void MacroAssemblerX86Shared::minMaxFloat32x4(bool isMin, FloatRegister lhs_,
|
||||
void MacroAssemblerX86Shared::minMaxFloat32x4(bool isMin, FloatRegister lhs,
|
||||
Operand rhs, FloatRegister temp1,
|
||||
FloatRegister temp2,
|
||||
FloatRegister output) {
|
||||
|
|
@ -800,7 +807,7 @@ void MacroAssemblerX86Shared::minMaxFloat32x4(bool isMin, FloatRegister lhs_,
|
|||
SimdConstant quietBits(SimdConstant::SplatX4(int32_t(0x00400000)));
|
||||
|
||||
/* clang-format off */ /* leave my comments alone */
|
||||
FloatRegister lhs = reusedInputSimd128FloatIfNotOther(lhs_, scratch, output);
|
||||
lhs = moveSimd128FloatIfNotAVXOrOther(lhs, scratch, output);
|
||||
if (isMin) {
|
||||
vmovaps(lhs, output); // compute
|
||||
vminps(rhs, output, output); // min lhs, rhs
|
||||
|
|
@ -826,7 +833,7 @@ void MacroAssemblerX86Shared::minMaxFloat32x4(bool isMin, FloatRegister lhs_,
|
|||
|
||||
vmovaps(temp1, temp2); // clear NaN lanes of result
|
||||
vpandn(output, temp2, temp2); // result now in temp2
|
||||
asMasm().vpandSimd128(quietBits, temp1); // setup QNaN bits in NaN lanes
|
||||
asMasm().vpandSimd128(quietBits, temp1, temp1); // setup QNaN bits in NaN lanes
|
||||
vorps(temp1, temp2, temp2); // and OR into result
|
||||
vmovaps(lhs, temp1); // find NaN lanes
|
||||
vcmpunordps(Operand(temp1), temp1, temp1); // in lhs
|
||||
|
|
@ -844,7 +851,7 @@ void MacroAssemblerX86Shared::minMaxFloat32x4(bool isMin, FloatRegister lhs_,
|
|||
}
|
||||
|
||||
// Exactly as above.
|
||||
void MacroAssemblerX86Shared::minMaxFloat64x2(bool isMin, FloatRegister lhs_,
|
||||
void MacroAssemblerX86Shared::minMaxFloat64x2(bool isMin, FloatRegister lhs,
|
||||
Operand rhs, FloatRegister temp1,
|
||||
FloatRegister temp2,
|
||||
FloatRegister output) {
|
||||
|
|
@ -853,7 +860,7 @@ void MacroAssemblerX86Shared::minMaxFloat64x2(bool isMin, FloatRegister lhs_,
|
|||
SimdConstant quietBits(SimdConstant::SplatX2(int64_t(0x0008000000000000ull)));
|
||||
|
||||
/* clang-format off */ /* leave my comments alone */
|
||||
FloatRegister lhs = reusedInputSimd128FloatIfNotOther(lhs_, scratch, output);
|
||||
lhs = moveSimd128FloatIfNotAVXOrOther(lhs, scratch, output);
|
||||
if (isMin) {
|
||||
vmovapd(lhs, output); // compute
|
||||
vminpd(rhs, output, output); // min lhs, rhs
|
||||
|
|
@ -868,7 +875,7 @@ void MacroAssemblerX86Shared::minMaxFloat64x2(bool isMin, FloatRegister lhs_,
|
|||
vandpd(temp1, output, output); // fix max(-0, 0) with AND
|
||||
}
|
||||
vmovapd(lhs, temp1); // compute
|
||||
vcmpunordpd(rhs, temp1); // lhs UNORD rhs
|
||||
vcmpunordpd(rhs, temp1, temp1); // lhs UNORD rhs
|
||||
vptest(temp1, temp1); // check if any unordered
|
||||
j(Assembler::Equal, &l); // and exit if not
|
||||
|
||||
|
|
@ -879,15 +886,15 @@ void MacroAssemblerX86Shared::minMaxFloat64x2(bool isMin, FloatRegister lhs_,
|
|||
|
||||
vmovapd(temp1, temp2); // clear NaN lanes of result
|
||||
vpandn(output, temp2, temp2); // result now in temp2
|
||||
asMasm().vpandSimd128(quietBits, temp1); // setup QNaN bits in NaN lanes
|
||||
asMasm().vpandSimd128(quietBits, temp1, temp1); // setup QNaN bits in NaN lanes
|
||||
vorpd(temp1, temp2, temp2); // and OR into result
|
||||
vmovapd(lhs, temp1); // find NaN lanes
|
||||
vcmpunordpd(Operand(temp1), temp1); // in lhs
|
||||
vcmpunordpd(Operand(temp1), temp1, temp1); // in lhs
|
||||
vmovapd(temp1, output); // (and save them for later)
|
||||
vandpd(lhs, temp1, temp1); // and extract the NaNs
|
||||
vorpd(temp1, temp2, temp2); // and add to the result
|
||||
vmovapd(rhs, temp1); // find NaN lanes
|
||||
vcmpunordpd(Operand(temp1), temp1); // in rhs
|
||||
vcmpunordpd(Operand(temp1), temp1, temp1); // in rhs
|
||||
vpandn(temp1, output, output); // except if they were in lhs
|
||||
vandpd(rhs, output, output); // and extract the NaNs
|
||||
vorpd(temp2, output, output); // and add to the result
|
||||
|
|
@ -969,8 +976,8 @@ void MacroAssemblerX86Shared::packedLeftShiftByScalarInt8x16(
|
|||
asMasm().addInt8x16(dest, dest);
|
||||
}
|
||||
} else {
|
||||
asMasm().bitwiseAndSimd128(SimdConstant::SplatX16(0xFF >> count.value),
|
||||
dest);
|
||||
asMasm().bitwiseAndSimd128(
|
||||
dest, SimdConstant::SplatX16(0xFF >> count.value), dest);
|
||||
vpsllw(count, dest, dest);
|
||||
}
|
||||
}
|
||||
|
|
@ -1004,9 +1011,9 @@ void MacroAssemblerX86Shared::packedUnsignedRightShiftByScalarInt8x16(
|
|||
void MacroAssemblerX86Shared::packedUnsignedRightShiftByScalarInt8x16(
|
||||
Imm32 count, FloatRegister src, FloatRegister dest) {
|
||||
MOZ_ASSERT(count.value <= 7);
|
||||
asMasm().moveSimd128(src, dest);
|
||||
src = asMasm().moveSimd128IntIfNotAVX(src, dest);
|
||||
asMasm().bitwiseAndSimd128(
|
||||
SimdConstant::SplatX16((0xFF << count.value) & 0xFF), dest);
|
||||
src, SimdConstant::SplatX16((0xFF << count.value) & 0xFF), dest);
|
||||
vpsrlw(count, dest, dest);
|
||||
}
|
||||
|
||||
|
|
@ -1110,10 +1117,10 @@ void MacroAssemblerX86Shared::selectSimd128(FloatRegister mask,
|
|||
void MacroAssemblerX86Shared::unsignedConvertInt32x4ToFloat32x4(
|
||||
FloatRegister src, FloatRegister dest) {
|
||||
ScratchSimd128Scope scratch(asMasm());
|
||||
asMasm().moveSimd128Int(src, dest);
|
||||
src = asMasm().moveSimd128IntIfNotAVX(src, dest);
|
||||
vpxor(Operand(scratch), scratch, scratch); // extract low bits
|
||||
vpblendw(0x55, dest, scratch, scratch); // into scratch
|
||||
vpsubd(Operand(scratch), dest, dest); // and high bits into dest
|
||||
vpblendw(0x55, src, scratch, scratch); // into scratch
|
||||
vpsubd(Operand(scratch), src, dest); // and high bits into dest
|
||||
vcvtdq2ps(scratch, scratch); // convert low bits
|
||||
vpsrld(Imm32(1), dest, dest); // get high into unsigned range
|
||||
vcvtdq2ps(dest, dest); // convert
|
||||
|
|
@ -1249,11 +1256,11 @@ void MacroAssemblerX86Shared::truncSatFloat64x2ToInt32x4(FloatRegister src,
|
|||
ScratchSimd128Scope scratch(asMasm());
|
||||
|
||||
vmovapd(src, scratch);
|
||||
vcmpeqpd(Operand(scratch), scratch);
|
||||
asMasm().moveSimd128Float(src, dest);
|
||||
vcmpeqpd(Operand(scratch), scratch, scratch);
|
||||
src = asMasm().moveSimd128FloatIfNotAVX(src, dest);
|
||||
asMasm().loadConstantSimd128Float(SimdConstant::SplatX2(2147483647.0), temp);
|
||||
vandpd(Operand(temp), scratch, scratch);
|
||||
vminpd(Operand(scratch), dest, dest);
|
||||
vminpd(Operand(scratch), src, dest);
|
||||
vcvttpd2dq(dest, dest);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1419,8 +1419,8 @@ void MacroAssembler::interleaveLowInt8x16(FloatRegister lhs, FloatRegister rhs,
|
|||
|
||||
void MacroAssembler::permuteInt8x16(const uint8_t lanes[16], FloatRegister src,
|
||||
FloatRegister dest) {
|
||||
moveSimd128Int(src, dest);
|
||||
vpshufbSimd128(SimdConstant::CreateX16((const int8_t*)lanes), dest);
|
||||
src = moveSimd128IntIfNotAVX(src, dest);
|
||||
vpshufbSimd128(SimdConstant::CreateX16((const int8_t*)lanes), src, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::permuteLowInt16x8(const uint16_t lanes[4],
|
||||
|
|
@ -1475,15 +1475,15 @@ void MacroAssembler::reverseInt16x8(FloatRegister src, FloatRegister dest) {
|
|||
}
|
||||
|
||||
void MacroAssembler::reverseInt32x4(FloatRegister src, FloatRegister dest) {
|
||||
moveSimd128Int(src, dest);
|
||||
src = moveSimd128IntIfNotAVX(src, dest);
|
||||
int8_t lanes[] = {3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12};
|
||||
vpshufbSimd128(SimdConstant::CreateX16((const int8_t*)lanes), dest);
|
||||
vpshufbSimd128(SimdConstant::CreateX16((const int8_t*)lanes), src, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::reverseInt64x2(FloatRegister src, FloatRegister dest) {
|
||||
moveSimd128Int(src, dest);
|
||||
src = moveSimd128IntIfNotAVX(src, dest);
|
||||
int8_t lanes[] = {7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8};
|
||||
vpshufbSimd128(SimdConstant::CreateX16((const int8_t*)lanes), dest);
|
||||
vpshufbSimd128(SimdConstant::CreateX16((const int8_t*)lanes), src, dest);
|
||||
}
|
||||
|
||||
// All lanes true
|
||||
|
|
@ -1574,9 +1574,9 @@ void MacroAssembler::bitmaskInt64x2(FloatRegister src, Register dest) {
|
|||
|
||||
void MacroAssembler::swizzleInt8x16(FloatRegister rhs, FloatRegister lhsDest) {
|
||||
ScratchSimd128Scope scratch(*this);
|
||||
moveSimd128Int(rhs, scratch);
|
||||
rhs = moveSimd128IntIfNotAVX(rhs, scratch);
|
||||
// Set high bit to 1 for values > 15 via adding with saturation.
|
||||
vpaddusbSimd128(SimdConstant::SplatX16(0x70), scratch);
|
||||
vpaddusbSimd128(SimdConstant::SplatX16(0x70), rhs, scratch);
|
||||
vpshufb(scratch, lhsDest, lhsDest); // permute
|
||||
}
|
||||
|
||||
|
|
@ -1591,9 +1591,9 @@ void MacroAssembler::addInt8x16(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpaddb(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::addInt8x16(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpaddb,
|
||||
void MacroAssembler::addInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpaddb,
|
||||
&MacroAssembler::vpaddbSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1601,9 +1601,9 @@ void MacroAssembler::addInt16x8(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpaddw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::addInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpaddw,
|
||||
void MacroAssembler::addInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpaddw,
|
||||
&MacroAssembler::vpaddwSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1616,9 +1616,9 @@ void MacroAssembler::addInt32x4(FloatRegister lhs, FloatRegister rhs,
|
|||
vpaddd(Operand(rhs), lhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::addInt32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpaddd,
|
||||
void MacroAssembler::addInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpaddd,
|
||||
&MacroAssembler::vpadddSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1626,9 +1626,9 @@ void MacroAssembler::addInt64x2(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpaddq(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::addInt64x2(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpaddq,
|
||||
void MacroAssembler::addInt64x2(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpaddq,
|
||||
&MacroAssembler::vpaddqSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1638,9 +1638,9 @@ void MacroAssembler::subInt8x16(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpsubb(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::subInt8x16(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpsubb,
|
||||
void MacroAssembler::subInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpsubb,
|
||||
&MacroAssembler::vpsubbSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1648,9 +1648,9 @@ void MacroAssembler::subInt16x8(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpsubw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::subInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpsubw,
|
||||
void MacroAssembler::subInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpsubw,
|
||||
&MacroAssembler::vpsubwSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1663,9 +1663,9 @@ void MacroAssembler::subInt32x4(FloatRegister lhs, FloatRegister rhs,
|
|||
vpsubd(Operand(rhs), lhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::subInt32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpsubd,
|
||||
void MacroAssembler::subInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpsubd,
|
||||
&MacroAssembler::vpsubdSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1673,9 +1673,9 @@ void MacroAssembler::subInt64x2(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpsubq(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::subInt64x2(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpsubq,
|
||||
void MacroAssembler::subInt64x2(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpsubq,
|
||||
&MacroAssembler::vpsubqSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1685,9 +1685,9 @@ void MacroAssembler::mulInt16x8(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpmullw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::mulInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpmullw,
|
||||
void MacroAssembler::mulInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpmullw,
|
||||
&MacroAssembler::vpmullwSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1700,9 +1700,9 @@ void MacroAssembler::mulInt32x4(FloatRegister lhs, FloatRegister rhs,
|
|||
vpmulld(Operand(rhs), lhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::mulInt32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpmulld,
|
||||
void MacroAssembler::mulInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpmulld,
|
||||
&MacroAssembler::vpmulldSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1839,7 +1839,7 @@ void MacroAssembler::q15MulrSatInt16x8(FloatRegister rhs,
|
|||
ScratchSimd128Scope scratch(*this);
|
||||
vpmulhrsw(Operand(rhs), lhsDest, lhsDest);
|
||||
vmovdqa(lhsDest, scratch);
|
||||
vpcmpeqwSimd128(SimdConstant::SplatX8(0x8000), scratch);
|
||||
vpcmpeqwSimd128(SimdConstant::SplatX8(0x8000), scratch, scratch);
|
||||
vpxor(scratch, lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
|
|
@ -1891,9 +1891,9 @@ void MacroAssembler::addSatInt8x16(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpaddsb(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::addSatInt8x16(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpaddsb,
|
||||
void MacroAssembler::addSatInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpaddsb,
|
||||
&MacroAssembler::vpaddsbSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1902,9 +1902,10 @@ void MacroAssembler::unsignedAddSatInt8x16(FloatRegister rhs,
|
|||
vpaddusb(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::unsignedAddSatInt8x16(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpaddusb,
|
||||
void MacroAssembler::unsignedAddSatInt8x16(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpaddusb,
|
||||
&MacroAssembler::vpaddusbSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1912,9 +1913,9 @@ void MacroAssembler::addSatInt16x8(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpaddsw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::addSatInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpaddsw,
|
||||
void MacroAssembler::addSatInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpaddsw,
|
||||
&MacroAssembler::vpaddswSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1923,9 +1924,10 @@ void MacroAssembler::unsignedAddSatInt16x8(FloatRegister rhs,
|
|||
vpaddusw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::unsignedAddSatInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpaddusw,
|
||||
void MacroAssembler::unsignedAddSatInt16x8(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpaddusw,
|
||||
&MacroAssembler::vpadduswSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1935,9 +1937,9 @@ void MacroAssembler::subSatInt8x16(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpsubsb(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::subSatInt8x16(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpsubsb,
|
||||
void MacroAssembler::subSatInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpsubsb,
|
||||
&MacroAssembler::vpsubsbSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1946,9 +1948,10 @@ void MacroAssembler::unsignedSubSatInt8x16(FloatRegister rhs,
|
|||
vpsubusb(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::unsignedSubSatInt8x16(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpsubusb,
|
||||
void MacroAssembler::unsignedSubSatInt8x16(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpsubusb,
|
||||
&MacroAssembler::vpsubusbSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1956,9 +1959,9 @@ void MacroAssembler::subSatInt16x8(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpsubsw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::subSatInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpsubsw,
|
||||
void MacroAssembler::subSatInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpsubsw,
|
||||
&MacroAssembler::vpsubswSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1967,9 +1970,10 @@ void MacroAssembler::unsignedSubSatInt16x8(FloatRegister rhs,
|
|||
vpsubusw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::unsignedSubSatInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpsubusw,
|
||||
void MacroAssembler::unsignedSubSatInt16x8(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpsubusw,
|
||||
&MacroAssembler::vpsubuswSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1979,9 +1983,9 @@ void MacroAssembler::minInt8x16(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpminsb(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::minInt8x16(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpminsb,
|
||||
void MacroAssembler::minInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpminsb,
|
||||
&MacroAssembler::vpminsbSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -1990,9 +1994,10 @@ void MacroAssembler::unsignedMinInt8x16(FloatRegister rhs,
|
|||
vpminub(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::unsignedMinInt8x16(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpminub,
|
||||
void MacroAssembler::unsignedMinInt8x16(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpminub,
|
||||
&MacroAssembler::vpminubSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2000,9 +2005,9 @@ void MacroAssembler::minInt16x8(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpminsw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::minInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpminsw,
|
||||
void MacroAssembler::minInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpminsw,
|
||||
&MacroAssembler::vpminswSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2011,9 +2016,10 @@ void MacroAssembler::unsignedMinInt16x8(FloatRegister rhs,
|
|||
vpminuw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::unsignedMinInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpminuw,
|
||||
void MacroAssembler::unsignedMinInt16x8(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpminuw,
|
||||
&MacroAssembler::vpminuwSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2021,9 +2027,9 @@ void MacroAssembler::minInt32x4(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpminsd(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::minInt32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpminsd,
|
||||
void MacroAssembler::minInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpminsd,
|
||||
&MacroAssembler::vpminsdSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2032,9 +2038,10 @@ void MacroAssembler::unsignedMinInt32x4(FloatRegister rhs,
|
|||
vpminud(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::unsignedMinInt32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpminud,
|
||||
void MacroAssembler::unsignedMinInt32x4(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpminud,
|
||||
&MacroAssembler::vpminudSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2044,9 +2051,9 @@ void MacroAssembler::maxInt8x16(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpmaxsb(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::maxInt8x16(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpmaxsb,
|
||||
void MacroAssembler::maxInt8x16(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpmaxsb,
|
||||
&MacroAssembler::vpmaxsbSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2055,9 +2062,10 @@ void MacroAssembler::unsignedMaxInt8x16(FloatRegister rhs,
|
|||
vpmaxub(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::unsignedMaxInt8x16(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpmaxub,
|
||||
void MacroAssembler::unsignedMaxInt8x16(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpmaxub,
|
||||
&MacroAssembler::vpmaxubSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2065,9 +2073,9 @@ void MacroAssembler::maxInt16x8(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpmaxsw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::maxInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpmaxsw,
|
||||
void MacroAssembler::maxInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpmaxsw,
|
||||
&MacroAssembler::vpmaxswSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2076,9 +2084,10 @@ void MacroAssembler::unsignedMaxInt16x8(FloatRegister rhs,
|
|||
vpmaxuw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::unsignedMaxInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpmaxuw,
|
||||
void MacroAssembler::unsignedMaxInt16x8(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpmaxuw,
|
||||
&MacroAssembler::vpmaxuwSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2086,9 +2095,9 @@ void MacroAssembler::maxInt32x4(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpmaxsd(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::maxInt32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpmaxsd,
|
||||
void MacroAssembler::maxInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpmaxsd,
|
||||
&MacroAssembler::vpmaxsdSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2097,9 +2106,10 @@ void MacroAssembler::unsignedMaxInt32x4(FloatRegister rhs,
|
|||
vpmaxud(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::unsignedMaxInt32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpmaxud,
|
||||
void MacroAssembler::unsignedMaxInt32x4(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpmaxud,
|
||||
&MacroAssembler::vpmaxudSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2317,9 +2327,10 @@ void MacroAssembler::bitwiseAndSimd128(FloatRegister lhs, FloatRegister rhs,
|
|||
vpand(Operand(rhs), lhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::bitwiseAndSimd128(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpand,
|
||||
void MacroAssembler::bitwiseAndSimd128(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpand,
|
||||
&MacroAssembler::vpandSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2333,9 +2344,10 @@ void MacroAssembler::bitwiseOrSimd128(FloatRegister lhs, FloatRegister rhs,
|
|||
vpor(Operand(rhs), lhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::bitwiseOrSimd128(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpor,
|
||||
void MacroAssembler::bitwiseOrSimd128(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpor,
|
||||
&MacroAssembler::vporSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2349,15 +2361,16 @@ void MacroAssembler::bitwiseXorSimd128(FloatRegister lhs, FloatRegister rhs,
|
|||
vpxor(Operand(rhs), lhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::bitwiseXorSimd128(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpxor,
|
||||
void MacroAssembler::bitwiseXorSimd128(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpxor,
|
||||
&MacroAssembler::vpxorSimd128);
|
||||
}
|
||||
|
||||
void MacroAssembler::bitwiseNotSimd128(FloatRegister src, FloatRegister dest) {
|
||||
moveSimd128(src, dest);
|
||||
bitwiseXorSimd128(SimdConstant::SplatX16(-1), dest);
|
||||
src = moveSimd128IntIfNotAVX(src, dest);
|
||||
bitwiseXorSimd128(src, SimdConstant::SplatX16(-1), dest);
|
||||
}
|
||||
|
||||
// Bitwise and-not
|
||||
|
|
@ -2397,11 +2410,11 @@ void MacroAssembler::compareInt8x16(Assembler::Condition cond,
|
|||
}
|
||||
|
||||
void MacroAssembler::compareInt8x16(Assembler::Condition cond,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
MOZ_ASSERT(cond != Assembler::Condition::LessThan &&
|
||||
cond != Assembler::Condition::GreaterThanOrEqual);
|
||||
MacroAssemblerX86Shared::compareInt8x16(cond, rhs, lhsDest);
|
||||
MacroAssemblerX86Shared::compareInt8x16(cond, lhs, rhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::compareInt16x8(Assembler::Condition cond,
|
||||
|
|
@ -2410,11 +2423,11 @@ void MacroAssembler::compareInt16x8(Assembler::Condition cond,
|
|||
}
|
||||
|
||||
void MacroAssembler::compareInt16x8(Assembler::Condition cond,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
MOZ_ASSERT(cond != Assembler::Condition::LessThan &&
|
||||
cond != Assembler::Condition::GreaterThanOrEqual);
|
||||
MacroAssemblerX86Shared::compareInt16x8(cond, rhs, lhsDest);
|
||||
MacroAssemblerX86Shared::compareInt16x8(cond, lhs, rhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::compareInt32x4(Assembler::Condition cond,
|
||||
|
|
@ -2429,11 +2442,11 @@ void MacroAssembler::compareInt32x4(Assembler::Condition cond,
|
|||
}
|
||||
|
||||
void MacroAssembler::compareInt32x4(Assembler::Condition cond,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
MOZ_ASSERT(cond != Assembler::Condition::LessThan &&
|
||||
cond != Assembler::Condition::GreaterThanOrEqual);
|
||||
MacroAssemblerX86Shared::compareInt32x4(cond, rhs, lhsDest);
|
||||
MacroAssemblerX86Shared::compareInt32x4(cond, lhs, rhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::compareForEqualityInt64x2(Assembler::Condition cond,
|
||||
|
|
@ -2477,11 +2490,12 @@ void MacroAssembler::compareFloat32x4(Assembler::Condition cond,
|
|||
}
|
||||
|
||||
void MacroAssembler::compareFloat32x4(Assembler::Condition cond,
|
||||
FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
FloatRegister dest) {
|
||||
MOZ_ASSERT(cond != Assembler::Condition::GreaterThan &&
|
||||
cond != Assembler::Condition::GreaterThanOrEqual);
|
||||
MacroAssemblerX86Shared::compareFloat32x4(cond, rhs, lhsDest);
|
||||
MacroAssemblerX86Shared::compareFloat32x4(cond, lhs, rhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::compareFloat64x2(Assembler::Condition cond,
|
||||
|
|
@ -2503,11 +2517,12 @@ void MacroAssembler::compareFloat64x2(Assembler::Condition cond,
|
|||
}
|
||||
|
||||
void MacroAssembler::compareFloat64x2(Assembler::Condition cond,
|
||||
FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
FloatRegister dest) {
|
||||
MOZ_ASSERT(cond != Assembler::Condition::GreaterThan &&
|
||||
cond != Assembler::Condition::GreaterThanOrEqual);
|
||||
MacroAssemblerX86Shared::compareFloat64x2(cond, rhs, lhsDest);
|
||||
MacroAssemblerX86Shared::compareFloat64x2(cond, lhs, rhs, dest);
|
||||
}
|
||||
|
||||
// Load. See comments above regarding integer operation.
|
||||
|
|
@ -2542,25 +2557,26 @@ void MacroAssembler::storeUnalignedSimd128(FloatRegister src,
|
|||
// Floating point negation
|
||||
|
||||
void MacroAssembler::negFloat32x4(FloatRegister src, FloatRegister dest) {
|
||||
moveSimd128(src, dest);
|
||||
bitwiseXorSimd128(SimdConstant::SplatX4(-0.f), dest);
|
||||
src = moveSimd128FloatIfNotAVX(src, dest);
|
||||
bitwiseXorSimd128(src, SimdConstant::SplatX4(-0.f), dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::negFloat64x2(FloatRegister src, FloatRegister dest) {
|
||||
moveSimd128(src, dest);
|
||||
bitwiseXorSimd128(SimdConstant::SplatX2(-0.0), dest);
|
||||
src = moveSimd128FloatIfNotAVX(src, dest);
|
||||
bitwiseXorSimd128(src, SimdConstant::SplatX2(-0.0), dest);
|
||||
}
|
||||
|
||||
// Floating point absolute value
|
||||
|
||||
void MacroAssembler::absFloat32x4(FloatRegister src, FloatRegister dest) {
|
||||
moveSimd128(src, dest);
|
||||
bitwiseAndSimd128(SimdConstant::SplatX4(0x7FFFFFFF), dest);
|
||||
src = moveSimd128FloatIfNotAVX(src, dest);
|
||||
bitwiseAndSimd128(src, SimdConstant::SplatX4(0x7FFFFFFF), dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::absFloat64x2(FloatRegister src, FloatRegister dest) {
|
||||
moveSimd128(src, dest);
|
||||
bitwiseAndSimd128(SimdConstant::SplatX2(int64_t(0x7FFFFFFFFFFFFFFFll)), dest);
|
||||
src = moveSimd128FloatIfNotAVX(src, dest);
|
||||
bitwiseAndSimd128(src, SimdConstant::SplatX2(int64_t(0x7FFFFFFFFFFFFFFFll)),
|
||||
dest);
|
||||
}
|
||||
|
||||
// NaN-propagating minimum
|
||||
|
|
@ -2631,9 +2647,9 @@ void MacroAssembler::widenDotInt16x8(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpmaddwd(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::widenDotInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpmaddwd,
|
||||
void MacroAssembler::widenDotInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpmaddwd,
|
||||
&MacroAssembler::vpmaddwdSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2682,9 +2698,9 @@ void MacroAssembler::addFloat32x4(FloatRegister lhs, FloatRegister rhs,
|
|||
vaddps(Operand(rhs), lhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::addFloat32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vaddps,
|
||||
void MacroAssembler::addFloat32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vaddps,
|
||||
&MacroAssembler::vaddpsSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2692,9 +2708,9 @@ void MacroAssembler::addFloat64x2(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vaddpd(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::addFloat64x2(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vaddpd,
|
||||
void MacroAssembler::addFloat64x2(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vaddpd,
|
||||
&MacroAssembler::vaddpdSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2709,9 +2725,9 @@ void MacroAssembler::subFloat32x4(FloatRegister lhs, FloatRegister rhs,
|
|||
vsubps(Operand(rhs), lhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::subFloat32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vsubps,
|
||||
void MacroAssembler::subFloat32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vsubps,
|
||||
&MacroAssembler::vsubpsSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2719,9 +2735,9 @@ void MacroAssembler::subFloat64x2(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
AssemblerX86Shared::vsubpd(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::subFloat64x2(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vsubpd,
|
||||
void MacroAssembler::subFloat64x2(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vsubpd,
|
||||
&MacroAssembler::vsubpdSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2736,9 +2752,9 @@ void MacroAssembler::divFloat32x4(FloatRegister lhs, FloatRegister rhs,
|
|||
vdivps(Operand(rhs), lhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::divFloat32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vdivps,
|
||||
void MacroAssembler::divFloat32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vdivps,
|
||||
&MacroAssembler::vdivpsSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2746,9 +2762,9 @@ void MacroAssembler::divFloat64x2(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vdivpd(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::divFloat64x2(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vdivpd,
|
||||
void MacroAssembler::divFloat64x2(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vdivpd,
|
||||
&MacroAssembler::vdivpdSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2763,9 +2779,9 @@ void MacroAssembler::mulFloat32x4(FloatRegister lhs, FloatRegister rhs,
|
|||
vmulps(Operand(rhs), lhs, dest);
|
||||
}
|
||||
|
||||
void MacroAssembler::mulFloat32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vmulps,
|
||||
void MacroAssembler::mulFloat32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vmulps,
|
||||
&MacroAssembler::vmulpsSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2773,9 +2789,9 @@ void MacroAssembler::mulFloat64x2(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vmulpd(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::mulFloat64x2(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vmulpd,
|
||||
void MacroAssembler::mulFloat64x2(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vmulpd,
|
||||
&MacroAssembler::vmulpdSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2915,9 +2931,9 @@ void MacroAssembler::narrowInt16x8(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpacksswb(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::narrowInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpacksswb,
|
||||
void MacroAssembler::narrowInt16x8(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpacksswb,
|
||||
&MacroAssembler::vpacksswbSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2926,9 +2942,10 @@ void MacroAssembler::unsignedNarrowInt16x8(FloatRegister rhs,
|
|||
vpackuswb(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::unsignedNarrowInt16x8(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpackuswb,
|
||||
void MacroAssembler::unsignedNarrowInt16x8(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpackuswb,
|
||||
&MacroAssembler::vpackuswbSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2936,9 +2953,9 @@ void MacroAssembler::narrowInt32x4(FloatRegister rhs, FloatRegister lhsDest) {
|
|||
vpackssdw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::narrowInt32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpackssdw,
|
||||
void MacroAssembler::narrowInt32x4(FloatRegister lhs, const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpackssdw,
|
||||
&MacroAssembler::vpackssdwSimd128);
|
||||
}
|
||||
|
||||
|
|
@ -2947,9 +2964,10 @@ void MacroAssembler::unsignedNarrowInt32x4(FloatRegister rhs,
|
|||
vpackusdw(Operand(rhs), lhsDest, lhsDest);
|
||||
}
|
||||
|
||||
void MacroAssembler::unsignedNarrowInt32x4(const SimdConstant& rhs,
|
||||
FloatRegister lhsDest) {
|
||||
binarySimd128(rhs, lhsDest, &MacroAssembler::vpackusdw,
|
||||
void MacroAssembler::unsignedNarrowInt32x4(FloatRegister lhs,
|
||||
const SimdConstant& rhs,
|
||||
FloatRegister dest) {
|
||||
binarySimd128(lhs, rhs, dest, &MacroAssembler::vpackusdw,
|
||||
&MacroAssembler::vpackusdwSimd128);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -168,6 +168,19 @@ void MacroAssemblerX86Shared::binarySimd128(
|
|||
}
|
||||
}
|
||||
|
||||
void MacroAssemblerX86Shared::binarySimd128(
|
||||
FloatRegister lhs, const SimdConstant& rhs, FloatRegister dest,
|
||||
void (MacroAssembler::*regOp)(const Operand&, FloatRegister, FloatRegister),
|
||||
void (MacroAssembler::*constOp)(const SimdConstant&, FloatRegister,
|
||||
FloatRegister)) {
|
||||
ScratchSimd128Scope scratch(asMasm());
|
||||
if (maybeInlineSimd128Int(rhs, scratch)) {
|
||||
(asMasm().*regOp)(Operand(scratch), lhs, dest);
|
||||
} else {
|
||||
(asMasm().*constOp)(rhs, lhs, dest);
|
||||
}
|
||||
}
|
||||
|
||||
void MacroAssemblerX86Shared::binarySimd128(
|
||||
const SimdConstant& rhs, FloatRegister lhs,
|
||||
void (MacroAssembler::*regOp)(const Operand&, FloatRegister),
|
||||
|
|
|
|||
|
|
@ -401,6 +401,12 @@ class MacroAssemblerX86Shared : public Assembler {
|
|||
FloatRegister),
|
||||
void (MacroAssembler::*constOp)(const SimdConstant&,
|
||||
FloatRegister));
|
||||
void binarySimd128(
|
||||
FloatRegister lhs, const SimdConstant& rhs, FloatRegister dest,
|
||||
void (MacroAssembler::*regOp)(const Operand&, FloatRegister,
|
||||
FloatRegister),
|
||||
void (MacroAssembler::*constOp)(const SimdConstant&, FloatRegister,
|
||||
FloatRegister));
|
||||
void binarySimd128(const SimdConstant& rhs, FloatRegister lhsDest,
|
||||
void (MacroAssembler::*regOp)(const Operand&,
|
||||
FloatRegister),
|
||||
|
|
@ -457,16 +463,16 @@ class MacroAssemblerX86Shared : public Assembler {
|
|||
|
||||
void compareInt8x16(FloatRegister lhs, Operand rhs, Assembler::Condition cond,
|
||||
FloatRegister output);
|
||||
void compareInt8x16(Assembler::Condition cond, const SimdConstant& rhs,
|
||||
FloatRegister lhsDest);
|
||||
void compareInt8x16(Assembler::Condition cond, FloatRegister lhs,
|
||||
const SimdConstant& rhs, FloatRegister dest);
|
||||
void compareInt16x8(FloatRegister lhs, Operand rhs, Assembler::Condition cond,
|
||||
FloatRegister output);
|
||||
void compareInt16x8(Assembler::Condition cond, const SimdConstant& rhs,
|
||||
FloatRegister lhsDest);
|
||||
void compareInt16x8(Assembler::Condition cond, FloatRegister lhs,
|
||||
const SimdConstant& rhs, FloatRegister dest);
|
||||
void compareInt32x4(FloatRegister lhs, Operand rhs, Assembler::Condition cond,
|
||||
FloatRegister output);
|
||||
void compareInt32x4(Assembler::Condition cond, const SimdConstant& rhs,
|
||||
FloatRegister lhsDest);
|
||||
void compareInt32x4(Assembler::Condition cond, FloatRegister lhs,
|
||||
const SimdConstant& rhs, FloatRegister dest);
|
||||
void compareForEqualityInt64x2(FloatRegister lhs, Operand rhs,
|
||||
Assembler::Condition cond,
|
||||
FloatRegister output);
|
||||
|
|
@ -475,12 +481,12 @@ class MacroAssemblerX86Shared : public Assembler {
|
|||
FloatRegister temp2, FloatRegister output);
|
||||
void compareFloat32x4(FloatRegister lhs, Operand rhs,
|
||||
Assembler::Condition cond, FloatRegister output);
|
||||
void compareFloat32x4(Assembler::Condition cond, const SimdConstant& rhs,
|
||||
FloatRegister lhsDest);
|
||||
void compareFloat32x4(Assembler::Condition cond, FloatRegister lhs,
|
||||
const SimdConstant& rhs, FloatRegister dest);
|
||||
void compareFloat64x2(FloatRegister lhs, Operand rhs,
|
||||
Assembler::Condition cond, FloatRegister output);
|
||||
void compareFloat64x2(Assembler::Condition cond, const SimdConstant& rhs,
|
||||
FloatRegister lhsDest);
|
||||
void compareFloat64x2(Assembler::Condition cond, FloatRegister lhs,
|
||||
const SimdConstant& rhs, FloatRegister dest);
|
||||
|
||||
void minMaxFloat32x4(bool isMin, FloatRegister lhs, Operand rhs,
|
||||
FloatRegister temp1, FloatRegister temp2,
|
||||
|
|
@ -573,7 +579,7 @@ class MacroAssemblerX86Shared : public Assembler {
|
|||
vmovdqa(src, dest);
|
||||
}
|
||||
}
|
||||
FloatRegister reusedInputInt32x4(FloatRegister src, FloatRegister dest) {
|
||||
FloatRegister moveSimd128IntIfNotAVX(FloatRegister src, FloatRegister dest) {
|
||||
MOZ_ASSERT(src.isSimd128() && dest.isSimd128());
|
||||
if (HasAVX()) {
|
||||
return src;
|
||||
|
|
@ -639,7 +645,8 @@ class MacroAssemblerX86Shared : public Assembler {
|
|||
vmovaps(src, dest);
|
||||
}
|
||||
}
|
||||
FloatRegister reusedInputSimd128Float(FloatRegister src, FloatRegister dest) {
|
||||
FloatRegister moveSimd128FloatIfNotAVX(FloatRegister src,
|
||||
FloatRegister dest) {
|
||||
MOZ_ASSERT(src.isSimd128() && dest.isSimd128());
|
||||
if (HasAVX()) {
|
||||
return src;
|
||||
|
|
@ -647,9 +654,9 @@ class MacroAssemblerX86Shared : public Assembler {
|
|||
moveSimd128Float(src, dest);
|
||||
return dest;
|
||||
}
|
||||
FloatRegister reusedInputSimd128FloatIfNotOther(FloatRegister src,
|
||||
FloatRegister dest,
|
||||
FloatRegister other) {
|
||||
FloatRegister moveSimd128FloatIfNotAVXOrOther(FloatRegister src,
|
||||
FloatRegister dest,
|
||||
FloatRegister other) {
|
||||
MOZ_ASSERT(src.isSimd128() && dest.isSimd128());
|
||||
if (HasAVX() && src != other) {
|
||||
return src;
|
||||
|
|
@ -657,6 +664,7 @@ class MacroAssemblerX86Shared : public Assembler {
|
|||
moveSimd128Float(src, dest);
|
||||
return dest;
|
||||
}
|
||||
|
||||
void loadUnalignedSimd128(const Operand& src, FloatRegister dest) {
|
||||
vmovups(src, dest);
|
||||
}
|
||||
|
|
@ -680,16 +688,6 @@ class MacroAssemblerX86Shared : public Assembler {
|
|||
void moveHighPairToLowPairFloat32(FloatRegister src, FloatRegister dest) {
|
||||
vmovhlps(src, dest, dest);
|
||||
}
|
||||
void shuffleFloat32(uint32_t mask, FloatRegister src, FloatRegister dest) {
|
||||
// The shuffle instruction on x86 is such that it moves 2 words from
|
||||
// the dest and 2 words from the src operands. To simplify things, just
|
||||
// clobber the output with the input and apply the instruction
|
||||
// afterwards.
|
||||
// Note: this is useAtStart-safe because src isn't read afterwards.
|
||||
FloatRegister srcCopy = reusedInputSimd128Float(src, dest);
|
||||
vshufps(mask, srcCopy, srcCopy, dest);
|
||||
}
|
||||
|
||||
void moveFloatAsDouble(Register src, FloatRegister dest) {
|
||||
vmovd(src, dest);
|
||||
vcvtss2sd(dest, dest, dest);
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ void MacroAssemblerX86::loadConstantSimd128Float(const SimdConstant& v,
|
|||
}
|
||||
|
||||
void MacroAssemblerX86::vpPatchOpSimd128(
|
||||
const SimdConstant& v, FloatRegister reg,
|
||||
const SimdConstant& v, FloatRegister src, FloatRegister dest,
|
||||
void (X86Encoding::BaseAssemblerX86::*op)(
|
||||
const void* address, X86Encoding::XMMRegisterID srcId,
|
||||
X86Encoding::XMMRegisterID destId)) {
|
||||
|
|
@ -87,12 +87,12 @@ void MacroAssemblerX86::vpPatchOpSimd128(
|
|||
if (!val) {
|
||||
return;
|
||||
}
|
||||
(masm.*op)(nullptr, reg.encoding(), reg.encoding());
|
||||
(masm.*op)(nullptr, src.encoding(), dest.encoding());
|
||||
propagateOOM(val->uses.append(CodeOffset(masm.size())));
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpPatchOpSimd128(
|
||||
const SimdConstant& v, FloatRegister reg,
|
||||
const SimdConstant& v, FloatRegister src, FloatRegister dest,
|
||||
size_t (X86Encoding::BaseAssemblerX86::*op)(
|
||||
const void* address, X86Encoding::XMMRegisterID srcId,
|
||||
X86Encoding::XMMRegisterID destId)) {
|
||||
|
|
@ -101,318 +101,324 @@ void MacroAssemblerX86::vpPatchOpSimd128(
|
|||
return;
|
||||
}
|
||||
size_t patchOffsetFromEnd =
|
||||
(masm.*op)(nullptr, reg.encoding(), reg.encoding());
|
||||
(masm.*op)(nullptr, src.encoding(), dest.encoding());
|
||||
propagateOOM(val->uses.append(CodeOffset(masm.size() - patchOffsetFromEnd)));
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpaddbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpaddb_mr);
|
||||
void MacroAssemblerX86::vpaddbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpaddb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpaddwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpaddw_mr);
|
||||
void MacroAssemblerX86::vpaddwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpaddw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpadddSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpaddd_mr);
|
||||
void MacroAssemblerX86::vpadddSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpaddd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpaddqSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpaddq_mr);
|
||||
void MacroAssemblerX86::vpaddqSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpaddq_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpsubbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpsubb_mr);
|
||||
void MacroAssemblerX86::vpsubbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpsubb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpsubwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpsubw_mr);
|
||||
void MacroAssemblerX86::vpsubwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpsubw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpsubdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpsubd_mr);
|
||||
void MacroAssemblerX86::vpsubdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpsubd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpsubqSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpsubq_mr);
|
||||
void MacroAssemblerX86::vpsubqSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpsubq_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpmullwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpmullw_mr);
|
||||
void MacroAssemblerX86::vpmullwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpmullw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpmulldSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpmulld_mr);
|
||||
void MacroAssemblerX86::vpmulldSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpmulld_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpaddsbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpaddsb_mr);
|
||||
void MacroAssemblerX86::vpaddsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpaddsb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpaddusbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpaddusb_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpaddusb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpaddswSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpaddsw_mr);
|
||||
void MacroAssemblerX86::vpaddswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpaddsw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpadduswSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpaddusw_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpaddusw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpsubsbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpsubsb_mr);
|
||||
void MacroAssemblerX86::vpsubsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpsubsb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpsubusbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpsubusb_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpsubusb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpsubswSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpsubsw_mr);
|
||||
void MacroAssemblerX86::vpsubswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpsubsw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpsubuswSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpsubusw_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpsubusw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpminsbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpminsb_mr);
|
||||
void MacroAssemblerX86::vpminsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpminsb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpminubSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpminub_mr);
|
||||
void MacroAssemblerX86::vpminubSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpminub_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpminswSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpminsw_mr);
|
||||
void MacroAssemblerX86::vpminswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpminsw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpminuwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpminuw_mr);
|
||||
void MacroAssemblerX86::vpminuwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpminuw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpminsdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpminsd_mr);
|
||||
void MacroAssemblerX86::vpminsdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpminsd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpminudSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpminud_mr);
|
||||
void MacroAssemblerX86::vpminudSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpminud_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpmaxsbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpmaxsb_mr);
|
||||
void MacroAssemblerX86::vpmaxsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpmaxsb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpmaxubSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpmaxub_mr);
|
||||
void MacroAssemblerX86::vpmaxubSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpmaxub_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpmaxswSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpmaxsw_mr);
|
||||
void MacroAssemblerX86::vpmaxswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpmaxsw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpmaxuwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpmaxuw_mr);
|
||||
void MacroAssemblerX86::vpmaxuwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpmaxuw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpmaxsdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpmaxsd_mr);
|
||||
void MacroAssemblerX86::vpmaxsdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpmaxsd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpmaxudSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpmaxud_mr);
|
||||
void MacroAssemblerX86::vpmaxudSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpmaxud_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpandSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpand_mr);
|
||||
void MacroAssemblerX86::vpandSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpand_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpxorSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpxor_mr);
|
||||
void MacroAssemblerX86::vpxorSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpxor_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vporSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpor_mr);
|
||||
void MacroAssemblerX86::vporSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpor_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vaddpsSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vaddps_mr);
|
||||
void MacroAssemblerX86::vaddpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vaddps_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vaddpdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vaddpd_mr);
|
||||
void MacroAssemblerX86::vaddpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vaddpd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vsubpsSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vsubps_mr);
|
||||
void MacroAssemblerX86::vsubpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vsubps_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vsubpdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vsubpd_mr);
|
||||
void MacroAssemblerX86::vsubpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vsubpd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vdivpsSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vdivps_mr);
|
||||
void MacroAssemblerX86::vdivpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vdivps_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vdivpdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vdivpd_mr);
|
||||
void MacroAssemblerX86::vdivpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vdivpd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vmulpsSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vmulps_mr);
|
||||
void MacroAssemblerX86::vmulpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vmulps_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vmulpdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vmulpd_mr);
|
||||
void MacroAssemblerX86::vmulpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vmulpd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpacksswbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpacksswb_mr);
|
||||
FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpacksswb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpackuswbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpackuswb_mr);
|
||||
FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpackuswb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpackssdwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpackssdw_mr);
|
||||
FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpackssdw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpackusdwSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpackusdw_mr);
|
||||
FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpackusdw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpshufbSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpshufb_mr);
|
||||
void MacroAssemblerX86::vpshufbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpshufb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vptestSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vptest_mr);
|
||||
FloatRegister lhs) {
|
||||
vpPatchOpSimd128(v, lhs, &X86Encoding::BaseAssemblerX86::vptest_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpmaddwdSimd128(const SimdConstant& v,
|
||||
FloatRegister srcDest) {
|
||||
vpPatchOpSimd128(v, srcDest, &X86Encoding::BaseAssemblerX86::vpmaddwd_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpmaddwd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpcmpeqbSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vpcmpeqb_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpcmpeqb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpcmpgtbSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vpcmpgtb_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpcmpgtb_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpcmpeqwSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vpcmpeqw_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpcmpeqw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpcmpgtwSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vpcmpgtw_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpcmpgtw_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpcmpeqdSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vpcmpeqd_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpcmpeqd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vpcmpgtdSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vpcmpgtd_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vpcmpgtd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vcmpeqpsSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vcmpeqps_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vcmpeqps_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vcmpneqpsSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vcmpneqps_mr);
|
||||
FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vcmpneqps_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vcmpltpsSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vcmpltps_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vcmpltps_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vcmplepsSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vcmpleps_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vcmpleps_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vcmpeqpdSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vcmpeqpd_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vcmpeqpd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vcmpneqpdSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vcmpneqpd_mr);
|
||||
FloatRegister lhs,
|
||||
FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vcmpneqpd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vcmpltpdSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vcmpltpd_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vcmpltpd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::vcmplepdSimd128(const SimdConstant& v,
|
||||
FloatRegister src) {
|
||||
vpPatchOpSimd128(v, src, &X86Encoding::BaseAssemblerX86::vcmplepd_mr);
|
||||
FloatRegister lhs, FloatRegister dest) {
|
||||
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vcmplepd_mr);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86::finish() {
|
||||
|
|
|
|||
|
|
@ -70,12 +70,30 @@ class MacroAssemblerX86 : public MacroAssemblerX86Shared {
|
|||
void setupABICall(uint32_t args);
|
||||
|
||||
void vpPatchOpSimd128(const SimdConstant& v, FloatRegister reg,
|
||||
void (X86Encoding::BaseAssemblerX86::*op)(
|
||||
const void* address,
|
||||
X86Encoding::XMMRegisterID srcId,
|
||||
X86Encoding::XMMRegisterID destId)) {
|
||||
vpPatchOpSimd128(v, reg, reg, op);
|
||||
}
|
||||
|
||||
void vpPatchOpSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest,
|
||||
void (X86Encoding::BaseAssemblerX86::*op)(
|
||||
const void* address,
|
||||
X86Encoding::XMMRegisterID srcId,
|
||||
X86Encoding::XMMRegisterID destId));
|
||||
|
||||
void vpPatchOpSimd128(const SimdConstant& v, FloatRegister reg,
|
||||
size_t (X86Encoding::BaseAssemblerX86::*op)(
|
||||
const void* address,
|
||||
X86Encoding::XMMRegisterID srcId,
|
||||
X86Encoding::XMMRegisterID destId)) {
|
||||
vpPatchOpSimd128(v, reg, reg, op);
|
||||
}
|
||||
|
||||
void vpPatchOpSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest,
|
||||
size_t (X86Encoding::BaseAssemblerX86::*op)(
|
||||
const void* address,
|
||||
X86Encoding::XMMRegisterID srcId,
|
||||
|
|
@ -922,68 +940,129 @@ class MacroAssemblerX86 : public MacroAssemblerX86Shared {
|
|||
|
||||
void loadConstantSimd128Int(const SimdConstant& v, FloatRegister dest);
|
||||
void loadConstantSimd128Float(const SimdConstant& v, FloatRegister dest);
|
||||
void vpaddbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpaddwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpadddSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpaddqSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubqSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmullwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmulldSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpaddsbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpaddusbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpaddswSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpadduswSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubsbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubusbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubswSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpsubuswSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpminsbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpminubSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpminswSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpminuwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpminsdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpminudSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmaxsbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmaxubSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmaxswSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmaxuwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmaxsdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpmaxudSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpandSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpxorSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vporSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vaddpsSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vaddpdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vsubpsSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vsubpdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vdivpsSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vdivpdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vmulpsSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vmulpdSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpacksswbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpackuswbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpackssdwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpackusdwSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vpshufbSimd128(const SimdConstant& v, FloatRegister srcDest);
|
||||
void vptestSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpmaddwdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpcmpeqbSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpcmpgtbSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpcmpeqwSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpcmpgtwSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpcmpeqdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpcmpgtdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmpeqpsSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmpneqpsSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmpltpsSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmplepsSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmpeqpdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmpneqpdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmpltpdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vcmplepdSimd128(const SimdConstant& v, FloatRegister src);
|
||||
void vpaddbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpaddwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpadddSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpaddqSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubqSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmullwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmulldSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpaddsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpaddusbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpaddswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpadduswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubusbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpsubuswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpminsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpminubSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpminswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpminuwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpminsdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpminudSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmaxsbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmaxubSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmaxswSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmaxuwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmaxsdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpmaxudSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpandSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpxorSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vporSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vaddpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vaddpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vsubpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vsubpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vdivpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vdivpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vmulpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vmulpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpacksswbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpackuswbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpackssdwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpackusdwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpshufbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vptestSimd128(const SimdConstant& v, FloatRegister lhs);
|
||||
void vpmaddwdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpcmpeqbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpcmpgtbSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpcmpeqwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpcmpgtwSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpcmpeqdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vpcmpgtdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmpeqpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmpneqpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmpltpsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmplepsSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmpeqpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmpneqpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmpltpdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
void vcmplepdSimd128(const SimdConstant& v, FloatRegister lhs,
|
||||
FloatRegister dest);
|
||||
|
||||
Condition testInt32Truthy(bool truthy, const ValueOperand& operand) {
|
||||
test32(operand.payloadReg(), operand.payloadReg());
|
||||
|
|
|
|||
Загрузка…
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