Bug 1289054 - Part 5: Implement the 64bit variant of Add and Sub on arm, r=bbouvier

js/src/jit/MacroAssembler.h

@@ -755,7 +755,7 @@ class MacroAssembler : public MacroAssemblerSpecific
 
     inline void add64(Register64 src, Register64 dest) PER_ARCH;
     inline void add64(Imm32 imm, Register64 dest) PER_ARCH;
-    inline void add64(Imm64 imm, Register64 dest) DEFINED_ON(x86, x64);
+    inline void add64(Imm64 imm, Register64 dest) DEFINED_ON(x86, x64, arm);
     inline void add64(const Operand& src, Register64 dest) DEFINED_ON(x64);
 
     inline void addFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
@@ -773,8 +773,8 @@ class MacroAssembler : public MacroAssemblerSpecific
     inline void subPtr(ImmWord imm, Register dest) DEFINED_ON(x64);
     inline void subPtr(const Address& addr, Register dest) DEFINED_ON(mips_shared, arm, arm64, x86, x64);
 
-    inline void sub64(Register64 src, Register64 dest) DEFINED_ON(x86, x64);
-    inline void sub64(Imm64 imm, Register64 dest) DEFINED_ON(x86, x64);
+    inline void sub64(Register64 src, Register64 dest) DEFINED_ON(x86, x64, arm);
+    inline void sub64(Imm64 imm, Register64 dest) DEFINED_ON(x86, x64, arm);
     inline void sub64(const Operand& src, Register64 dest) DEFINED_ON(x64);
 
     inline void subFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;

js/src/jit/arm/CodeGenerator-arm.cpp

@@ -292,6 +292,22 @@ CodeGeneratorARM::visitAddI(LAddI* ins)
         bailoutIf(Assembler::Overflow, ins->snapshot());
 }
 
+void
+CodeGeneratorARM::visitAddI64(LAddI64* lir)
+{
+    const LInt64Allocation lhs = lir->getInt64Operand(LAddI64::Lhs);
+    const LInt64Allocation rhs = lir->getInt64Operand(LAddI64::Rhs);
+
+    MOZ_ASSERT(ToOutRegister64(lir) == ToRegister64(lhs));
+
+    if (IsConstant(rhs)) {
+        masm.add64(Imm64(ToInt64(rhs)), ToRegister64(lhs));
+        return;
+    }
+
+    masm.add64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
+}
+
 void
 CodeGeneratorARM::visitSubI(LSubI* ins)
 {
@@ -310,6 +326,22 @@ CodeGeneratorARM::visitSubI(LSubI* ins)
         bailoutIf(Assembler::Overflow, ins->snapshot());
 }
 
+void
+CodeGeneratorARM::visitSubI64(LSubI64* lir)
+{
+    const LInt64Allocation lhs = lir->getInt64Operand(LSubI64::Lhs);
+    const LInt64Allocation rhs = lir->getInt64Operand(LSubI64::Rhs);
+
+    MOZ_ASSERT(ToOutRegister64(lir) == ToRegister64(lhs));
+
+    if (IsConstant(rhs)) {
+        masm.sub64(Imm64(ToInt64(rhs)), ToRegister64(lhs));
+        return;
+    }
+
+    masm.sub64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
+}
+
 void
 CodeGeneratorARM::visitMulI(LMulI* ins)
 {

js/src/jit/arm/CodeGenerator-arm.h

@@ -159,6 +159,8 @@ class CodeGeneratorARM : public CodeGeneratorShared
 
     virtual void visitWrapInt64ToInt32(LWrapInt64ToInt32* lir);
     virtual void visitExtendInt32ToInt64(LExtendInt32ToInt64* lir);
+    virtual void visitAddI64(LAddI64* lir);
+    virtual void visitSubI64(LSubI64* lir);
 
     // Out of line visitors.
     void visitOutOfLineBailout(OutOfLineBailout* ool);

js/src/jit/arm/Lowering-arm.cpp

@@ -196,7 +196,10 @@ void
 LIRGeneratorARM::lowerForALUInt64(LInstructionHelper<INT64_PIECES, 2 * INT64_PIECES, 0>* ins,
                                   MDefinition* mir, MDefinition* lhs, MDefinition* rhs)
 {
-    MOZ_CRASH("NYI");
+    ins->setInt64Operand(0, useInt64RegisterAtStart(lhs));
+    ins->setInt64Operand(INT64_PIECES,
+                         lhs != rhs ? useInt64OrConstant(rhs) : useInt64OrConstantAtStart(rhs));
+    defineInt64ReuseInput(ins, mir, 0);
 }
 
 void

js/src/jit/arm/MacroAssembler-arm-inl.h

@@ -255,6 +255,13 @@ MacroAssembler::add64(Imm32 imm, Register64 dest)
     ma_adc(Imm32(0), dest.high, LeaveCC);
 }
 
+void
+MacroAssembler::add64(Imm64 imm, Register64 dest)
+{
+    ma_add(imm.low(), dest.low, SetCC);
+    ma_adc(imm.hi(), dest.high, LeaveCC);
+}
+
 void
 MacroAssembler::addDouble(FloatRegister src, FloatRegister dest)
 {
@@ -316,6 +323,20 @@ MacroAssembler::subPtr(const Address& addr, Register dest)
     ma_sub(scratch, dest);
 }
 
+void
+MacroAssembler::sub64(Register64 src, Register64 dest)
+{
+    ma_sub(src.low, dest.low, SetCC);
+    ma_sbc(src.high, dest.high, LeaveCC);
+}
+
+void
+MacroAssembler::sub64(Imm64 imm, Register64 dest)
+{
+    ma_sub(imm.low(), dest.low, SetCC);
+    ma_sbc(imm.hi(), dest.high, LeaveCC);
+}
+
 void
 MacroAssembler::subDouble(FloatRegister src, FloatRegister dest)
 {

js/src/jit/arm/Simulator-arm.cpp

@@ -3092,6 +3092,11 @@ Simulator::decodeType01(SimInstruction* instr)
             }
             break;
           case OpSbc:
+            alu_out = rn_val - shifter_operand - (getCarry() == 0 ? 1 : 0);
+            set_register(rd, alu_out);
+            if (instr->hasS())
+                MOZ_CRASH();
+            break;
           case OpRsc:
             MOZ_CRASH();
             break;