Bug 544422 - [Nanojit] Implement asm_f2i on sparc. r=stejohns

--HG--
extra : convert_revision : 4849b094bea2e2ff58c86ca09ef4a8f652777594

js/src/nanojit/NativeSparc.cpp

@@ -959,8 +959,14 @@ namespace nanojit
         SETHI(0x43300000, G1);
     }
 
-    void Assembler::asm_f2i(LInsp) {
-        NanoAssertMsg(0, "NJ_F2I_SUPPORTED not yet supported for this architecture");
+    void Assembler::asm_f2i(LInsp ins) {
+        LIns *lhs = ins->oprnd1();
+        Register rr = prepareResultReg(ins, GpRegs);
+        Register ra = findRegFor(lhs, FpRegs);
+        int d = findMemFor(ins);
+        LDSW32(FP, d, rr);
+        STF32(ra, d, FP);
+        FDTOI(ra, ra);
     }
 
     void Assembler::asm_nongp_copy(Register r, Register s)

js/src/nanojit/NativeSparc.h

@@ -75,7 +75,7 @@ namespace nanojit
 #define NJ_MAX_PARAMETERS               1
 #define NJ_JTBL_SUPPORTED               0
 #define NJ_EXPANDED_LOADSTORE_SUPPORTED 0
-#define NJ_F2I_SUPPORTED                0
+#define NJ_F2I_SUPPORTED                1
 
     const int NJ_ALIGN_STACK = 16;
 
@@ -485,6 +485,12 @@ namespace nanojit
     asm_output("fmuld %s, %s, %s", gpn(rs1+32), gpn(rs2+32), gpn(rd+32)); \
     } while (0)
 
+#define FDTOI(rs2, rd) \
+    do { \
+    Format_3_8(2, rd, 0x34, 0, 0xd2, rs2); \
+    asm_output("fdtoi %s, %s", gpn(rs2+32), gpn(rd+32)); \
+    } while (0)
+
 #define FDIVD(rs1, rs2, rd) \
     do { \
     Format_3_8(2, rd, 0x34, rs1, 0x4e, rs2); \
@@ -886,6 +892,14 @@ namespace nanojit
       SET32(imm32, L0); \
     }
 
+#define STF32(rd, imm32, rs1) \
+    if(isIMM13(imm32+4)) { \
+      STFI(rd, imm32, rs1); \
+    } else { \
+      STF(rd, L0, rs1); \
+      SET32(imm32, L0); \
+    }
+
 #define LDDF32(rs1, imm32, rd) \
     if(isIMM13(imm32+4)) { \
       LDFI(rs1, imm32+4, rd+1); \