зеркало из https://github.com/mozilla/gecko-dev.git
[arm] fix up ARM floating point comparisons; fixes ARM trace-test (relanding)
This commit is contained in:
Vladimir Vukicevic
Родитель
937e5d9cec
Коммит
56155f4e54
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@ -66,6 +66,13 @@ const Register Assembler::argRegs[] = { R0, R1, R2, R3 };
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const Register Assembler::retRegs[] = { R0, R1 };
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const Register Assembler::savedRegs[] = { R4, R5, R6, R7, R8, R9, R10 };
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const char *ccName(ConditionCode cc)
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{
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const char *ccNames[] = { "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt", "gt", "le", "al", "nv" };
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return ccNames[(int)cc];
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}
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void
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Assembler::nInit(AvmCore*)
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{
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@ -1039,63 +1046,6 @@ Assembler::asm_fcmp(LInsp ins)
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Register ra = findRegFor(lhs, FpRegs);
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Register rb = findRegFor(rhs, FpRegs);
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// We can't uniquely identify fge/fle via a single bit
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// pattern (since equality and lt/gt are separate bits);
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// so convert to the single-bit variant.
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if (op == LIR_fge) {
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Register temp = ra;
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ra = rb;
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rb = temp;
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op = LIR_flt;
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} else if (op == LIR_fle) {
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Register temp = ra;
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ra = rb;
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rb = temp;
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op = LIR_fgt;
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}
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// There is no way to test for an unordered result using
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// the conditional form of an instruction; the encoding (C=1 V=1)
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// ends up having overlaps with a few other tests. So, test for
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// the explicit mask.
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uint8_t mask = 0x0;
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// NZCV
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// for a valid ordered result, V is always 0 from VFP
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if (op == LIR_feq)
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// ZC // cond EQ (both equal and "not less than"
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mask = 0x6;
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else if (op == LIR_flt)
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// N // cond MI
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mask = 0x8;
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else if (op == LIR_fgt)
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// C // cond CS
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mask = 0x2;
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else
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NanoAssert(0);
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/*
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// these were converted into gt and lt above.
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if (op == LIR_fle)
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// NZ // cond LE
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mask = 0xC;
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else if (op == LIR_fge)
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// ZC // cond fail?
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mask = 0x6;
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*/
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// TODO XXX could do this as fcmpd; fmstat; tstvs rX, #0 the tstvs
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// would reset the status bits if V (NaN flag) is set, but that
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// doesn't work for NE. For NE could teqvs rX, #1. rX needs to
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// be any register that has lsb == 0, such as sp/fp/pc.
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// Test explicily with the full mask; if V is set, test will fail.
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// Assumption is that this will be followed up by a BEQ/BNE
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CMPi(Scratch, mask);
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// grab just the condition fields
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SHRi(Scratch, 28);
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MRS(Scratch);
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// do the comparison and get results loaded in ARM status register
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FMSTAT();
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FCMPD(ra, rb);
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}
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@ -1120,10 +1070,28 @@ Assembler::asm_branch(bool branchOnFalse, LInsp cond, NIns* targ, bool isfar)
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if (condop >= LIR_feq && condop <= LIR_fge)
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{
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if (branchOnFalse)
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JNE(targ);
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else
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JE(targ);
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ConditionCode cc = NV;
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if (branchOnFalse) {
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switch (condop) {
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case LIR_feq: cc = NE; break;
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case LIR_flt: cc = PL; break;
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case LIR_fgt: cc = LE; break;
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case LIR_fle: cc = HI; break;
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case LIR_fge: cc = LT; break;
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}
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} else {
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switch (condop) {
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case LIR_feq: cc = EQ; break;
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case LIR_flt: cc = MI; break;
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case LIR_fgt: cc = GT; break;
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case LIR_fle: cc = LS; break;
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case LIR_fge: cc = GE; break;
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}
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}
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B_cond(cc, targ);
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asm_output("b(%d) 0x%08x", cc, (unsigned int) targ);
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NIns *at = _nIns;
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asm_fcmp(cond);
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@ -1240,7 +1208,14 @@ Assembler::asm_fcond(LInsp ins)
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// only want certain regs
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Register r = prepResultReg(ins, AllowableFlagRegs);
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SETE(r);
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switch (ins->opcode()) {
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case LIR_feq: SET(r,EQ,NE); break;
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case LIR_flt: SET(r,MI,PL); break;
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case LIR_fgt: SET(r,GT,LE); break;
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case LIR_fle: SET(r,LS,HI); break;
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case LIR_fge: SET(r,GE,LT); break;
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}
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asm_fcmp(ins);
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}
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@ -156,6 +156,7 @@ typedef enum {
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NV = 0xF // NeVer
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} ConditionCode;
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const char *ccName(ConditionCode cc);
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typedef int RegisterMask;
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typedef struct _FragInfo {
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@ -692,23 +693,26 @@ typedef enum {
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// MOV(EQ) _r, #1
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// EOR(NE) _r, _r
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#define SET(_r,_cond,_opp) \
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#define SET(_r,_cond,_opp) do { \
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underrunProtect(8); \
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*(--_nIns) = (NIns)( (_opp<<28) | (1<<21) | ((_r)<<16) | ((_r)<<12) | (_r) ); \
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*(--_nIns) = (NIns)( (_cond<<28) | (0x3A<<20) | ((_r)<<12) | (1) );
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*(--_nIns) = (NIns)( (_cond<<28) | (0x3A<<20) | ((_r)<<12) | (1) ); \
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asm_output("mov%s %s, #1", ccName(_cond), gpn(r), gpn(r)); \
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asm_output("eor%s %s, %s", ccName(_opp), gpn(r), gpn(r)); \
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} while (0)
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#define SETE(r) do {SET(r,EQ,NE); asm_output("sete %s",gpn(r)); } while(0)
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#define SETL(r) do {SET(r,LT,GE); asm_output("setl %s",gpn(r)); } while(0)
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#define SETLE(r) do {SET(r,LE,GT); asm_output("setle %s",gpn(r)); } while(0)
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#define SETG(r) do {SET(r,GT,LE); asm_output("setg %s",gpn(r)); } while(0)
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#define SETGE(r) do {SET(r,GE,LT); asm_output("setge %s",gpn(r)); } while(0)
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#define SETB(r) do {SET(r,CC,CS); asm_output("setb %s",gpn(r)); } while(0)
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#define SETBE(r) do {SET(r,LS,HI); asm_output("setb %s",gpn(r)); } while(0)
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#define SETAE(r) do {SET(r,CS,CC); asm_output("setae %s",gpn(r)); } while(0)
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#define SETA(r) do {SET(r,HI,LS); asm_output("seta %s",gpn(r)); } while(0)
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#define SETO(r) do {SET(r,VS,LS); asm_output("seto %s",gpn(r)); } while(0)
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#define SETC(r) do {SET(r,CS,LS); asm_output("setc %s",gpn(r)); } while(0)
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#define SETE(r) SET(r,EQ,NE)
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#define SETL(r) SET(r,LT,GE)
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#define SETLE(r) SET(r,LE,GT)
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#define SETG(r) SET(r,GT,LE)
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#define SETGE(r) SET(r,GE,LT)
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#define SETB(r) SET(r,CC,CS)
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#define SETBE(r) SET(r,LS,HI)
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#define SETAE(r) SET(r,CS,CC)
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#define SETA(r) SET(r,HI,LS)
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#define SETO(r) SET(r,VS,LS)
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#define SETC(r) SET(r,CS,LS)
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// This zero-extends a reg that has been set using one of the SET macros,
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// but is a NOOP on ARM/Thumb
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