Bug 1708743 - Enable more AVX tests. r=lth

To enable AVX2 for test:
* makes isAVXPresent cross-platform
* ignore codegen tests (produced code with AVX2 is different)
* fix shuffle tests: make ALIGNR three-address
* fix copysign tests

Differential Revision: https://phabricator.services.mozilla.com/D134113
This commit is contained in:
Yury Delendik 2021-12-17 20:12:03 +00:00
Родитель 8ea4f707f7
Коммит 5b35493461
14 изменённых файлов: 62 добавлений и 36 удалений

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@ -4031,13 +4031,15 @@ static bool DisplayName(JSContext* cx, unsigned argc, Value* vp) {
return true;
}
#if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86)
static bool IsAvxPresent(JSContext* cx, unsigned argc, Value* vp) {
CallArgs args = CallArgsFromVp(argc, vp);
#if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86)
args.rval().setBoolean(jit::Assembler::HasAVX());
#else
args.rval().setBoolean(false);
#endif
return true;
}
#endif
class ShellAllocationMetadataBuilder : public AllocationMetadataBuilder {
public:
@ -8228,11 +8230,9 @@ gc::ZealModeHelpText),
" Returns whether the given value is a nested function in an asm.js module that has been\n"
" both compile- and link-time validated."),
#if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86)
JS_FN_HELP("isAvxPresent", IsAvxPresent, 0, 0,
"isAvxPresent(fn)",
" Returns whether AVX is present and enabled."),
#endif
JS_FN_HELP("wasmIsSupported", WasmIsSupported, 0, 0,
"wasmIsSupported()",

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@ -1 +1 @@
|jit-test| test-also=--wasm-compiler=optimizing; test-also=--wasm-compiler=baseline; test-also=--test-wasm-await-tier2; test-also=--disable-wasm-huge-memory; skip-variant-if: --disable-wasm-huge-memory, !wasmHugeMemorySupported(); include:wasm.js
|jit-test| test-also=--wasm-compiler=optimizing; test-also=--wasm-compiler=baseline; test-also=--test-wasm-await-tier2; test-also=--disable-wasm-huge-memory; skip-variant-if: --disable-wasm-huge-memory, !wasmHugeMemorySupported(); test-also=--wasm-compiler=optimizing --enable-avx; skip-variant-if: --wasm-compiler=optimizing --enable-avx, !isAvxPresent(); include:wasm.js

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@ -1,4 +1,4 @@
// |jit-test| skip-if: !wasmSimdEnabled() || !hasDisassembler() || wasmCompileMode() != "ion" || !getBuildConfiguration().x86 || getBuildConfiguration().simulator; include:codegen-x86-test.js
// |jit-test| skip-if: !wasmSimdEnabled() || !hasDisassembler() || wasmCompileMode() != "ion" || !getBuildConfiguration().x86 || getBuildConfiguration().simulator || isAvxPresent(); include:codegen-x86-test.js
codegenTestX86_v128xLITERAL_v128(
[['f32x4.eq', '(v128.const f32x4 1 2 3 4)',

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@ -1,4 +1,4 @@
// |jit-test| skip-if: !wasmSimdEnabled() || !hasDisassembler() || wasmCompileMode() != "ion" || !getBuildConfiguration().x64 || getBuildConfiguration().simulator; include:codegen-x64-test.js
// |jit-test| skip-if: !wasmSimdEnabled() || !hasDisassembler() || wasmCompileMode() != "ion" || !getBuildConfiguration().x64 || getBuildConfiguration().simulator || isAvxPresent(); include:codegen-x64-test.js
// Test that there are no extraneous moves or fixups for SIMD bitselect
// operations. See README-codegen.md for general information about this type of

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@ -1,4 +1,4 @@
// |jit-test| skip-if: !wasmSimdEnabled() || !hasDisassembler() || wasmCompileMode() != "ion" || !getBuildConfiguration().x64 || getBuildConfiguration().simulator; include:codegen-x64-test.js
// |jit-test| skip-if: !wasmSimdEnabled() || !hasDisassembler() || wasmCompileMode() != "ion" || !getBuildConfiguration().x64 || getBuildConfiguration().simulator || isAvxPresent(); include:codegen-x64-test.js
// Test that there are no extraneous moves for various SIMD conversion
// operations. See README-codegen.md for general information about this type of

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@ -1 +1 @@
|jit-test| test-also=--no-wasm-simd; test-also=--wasm-compiler=baseline; test-also=--wasm-compiler=optimizing; include:wasm.js
|jit-test| test-also=--no-wasm-simd; test-also=--wasm-compiler=baseline; test-also=--wasm-compiler=optimizing; test-also=--wasm-compiler=optimizing --enable-avx; skip-variant-if: --wasm-compiler=optimizing --enable-avx, !isAvxPresent(); include:wasm.js

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@ -1,4 +1,4 @@
// |jit-test| skip-if: !wasmSimdEnabled() || !hasDisassembler() || wasmCompileMode() != "ion" || !getBuildConfiguration().x64 || getBuildConfiguration().simulator; include:codegen-x64-test.js
// |jit-test| skip-if: !wasmSimdEnabled() || !hasDisassembler() || wasmCompileMode() != "ion" || !getBuildConfiguration().x64 || getBuildConfiguration().simulator || isAvxPresent(); include:codegen-x64-test.js
// This checks that we emit a REX prefix that includes the SIB index when
// appropriate.

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@ -1,4 +1,4 @@
// |jit-test| skip-if: !wasmSimdEnabled() || !hasDisassembler() || wasmCompileMode() != "ion" || !getBuildConfiguration().x64 || getBuildConfiguration().simulator; include:codegen-x64-test.js
// |jit-test| skip-if: !wasmSimdEnabled() || !hasDisassembler() || wasmCompileMode() != "ion" || !getBuildConfiguration().x64 || getBuildConfiguration().simulator || isAvxPresent(); include:codegen-x64-test.js
// Test that there are no extraneous moves or fixups for SIMD shuffle
// operations. See README-codegen.md for general information about this type of

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@ -1,4 +1,4 @@
// |jit-test| skip-if: !wasmSimdEnabled() || !hasDisassembler() || wasmCompileMode() != "ion" || !getBuildConfiguration().x64 || getBuildConfiguration().simulator; include:codegen-x64-test.js
// |jit-test| skip-if: !wasmSimdEnabled() || !hasDisassembler() || wasmCompileMode() != "ion" || !getBuildConfiguration().x64 || getBuildConfiguration().simulator || isAvxPresent(); include:codegen-x64-test.js
// Test that there are no extraneous moves or other instructions for splat and
// other splat-like operations that can reuse its input for its output and/or

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@ -3727,11 +3727,12 @@ class AssemblerX86Shared : public AssemblerShared {
MOZ_CRASH("unexpected operand kind");
}
}
void vpalignr(const Operand& src, FloatRegister dest, uint8_t shift) {
void vpalignr(const Operand& src1, FloatRegister src0, FloatRegister dest,
uint8_t shift) {
MOZ_ASSERT(HasSSE3());
switch (src.kind()) {
switch (src1.kind()) {
case Operand::FPREG:
masm.vpalignr_irr(shift, src.fpu(), dest.encoding());
masm.vpalignr_irr(shift, src1.fpu(), src0.encoding(), dest.encoding());
break;
default:
MOZ_CRASH("unexpected operand kind");

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@ -4204,10 +4204,11 @@ class BaseAssembler : public GenericAssembler {
base, index, scale, invalid_xmm, dst);
}
void vpalignr_irr(unsigned imm, XMMRegisterID src, XMMRegisterID dst) {
void vpalignr_irr(unsigned imm, XMMRegisterID src1, XMMRegisterID src0,
XMMRegisterID dst) {
MOZ_ASSERT(imm < 32);
threeByteOpImmSimd("vpalignr", VEX_PD, OP3_PALIGNR_VdqWdqIb, ESCAPE_3A, imm,
src, invalid_xmm, dst);
src1, src0, dst);
}
void vpunpcklbw_rr(XMMRegisterID src1, XMMRegisterID src0,

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@ -88,7 +88,7 @@ void MacroAssemblerX86Shared::extractLaneFloat64x2(FloatRegister input,
moveDouble(input, output);
}
} else {
vpalignr(Operand(input), output, 8);
vpalignr(Operand(input), output, output, 8);
}
}
@ -907,7 +907,7 @@ void MacroAssemblerX86Shared::packedShiftByScalarInt8x16(
vmovd(count, scratch);
// High bytes
vpalignr(Operand(in), xtmp, 8);
vpalignr(Operand(in), xtmp, xtmp, 8);
(this->*extend)(Operand(xtmp), xtmp);
(this->*shift)(scratch, xtmp, xtmp);

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@ -1441,7 +1441,7 @@ void MacroAssembler::permuteInt32x4(const uint32_t lanes[4], FloatRegister src,
void MacroAssembler::concatAndRightShiftSimd128(FloatRegister rhs,
FloatRegister lhsDest,
uint32_t shift) {
vpalignr(Operand(rhs), lhsDest, shift);
vpalignr(Operand(rhs), lhsDest, lhsDest, shift);
}
void MacroAssembler::leftShiftSimd128(Imm32 count, FloatRegister src,
@ -2902,7 +2902,7 @@ void MacroAssembler::widenLowInt8x16(FloatRegister src, FloatRegister dest) {
}
void MacroAssembler::widenHighInt8x16(FloatRegister src, FloatRegister dest) {
vpalignr(Operand(src), dest, 8);
vpalignr(Operand(src), dest, dest, 8);
vpmovsxbw(Operand(dest), dest);
}
@ -2913,7 +2913,7 @@ void MacroAssembler::unsignedWidenLowInt8x16(FloatRegister src,
void MacroAssembler::unsignedWidenHighInt8x16(FloatRegister src,
FloatRegister dest) {
vpalignr(Operand(src), dest, 8);
vpalignr(Operand(src), dest, dest, 8);
vpmovzxbw(Operand(dest), dest);
}
@ -2922,7 +2922,7 @@ void MacroAssembler::widenLowInt16x8(FloatRegister src, FloatRegister dest) {
}
void MacroAssembler::widenHighInt16x8(FloatRegister src, FloatRegister dest) {
vpalignr(Operand(src), dest, 8);
vpalignr(Operand(src), dest, dest, 8);
vpmovsxwd(Operand(dest), dest);
}
@ -2933,7 +2933,7 @@ void MacroAssembler::unsignedWidenLowInt16x8(FloatRegister src,
void MacroAssembler::unsignedWidenHighInt16x8(FloatRegister src,
FloatRegister dest) {
vpalignr(Operand(src), dest, 8);
vpalignr(Operand(src), dest, dest, 8);
vpmovzxwd(Operand(dest), dest);
}

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@ -2073,13 +2073,25 @@ void MacroAssembler::copySignDouble(FloatRegister lhs, FloatRegister rhs,
FloatRegister output) {
ScratchDoubleScope scratch(*this);
double clearSignMask = mozilla::BitwiseCast<double>(INT64_MAX);
loadConstantDouble(clearSignMask, scratch);
vandpd(scratch, lhs, output);
// TODO Support AVX2
if (rhs == output) {
MOZ_ASSERT(lhs != rhs);
double keepSignMask = mozilla::BitwiseCast<double>(INT64_MIN);
loadConstantDouble(keepSignMask, scratch);
vandpd(scratch, rhs, output);
double keepSignMask = mozilla::BitwiseCast<double>(INT64_MIN);
loadConstantDouble(keepSignMask, scratch);
vandpd(rhs, scratch, scratch);
double clearSignMask = mozilla::BitwiseCast<double>(INT64_MAX);
loadConstantDouble(clearSignMask, scratch);
vandpd(lhs, scratch, scratch);
} else {
double clearSignMask = mozilla::BitwiseCast<double>(INT64_MAX);
loadConstantDouble(clearSignMask, scratch);
vandpd(scratch, lhs, output);
double keepSignMask = mozilla::BitwiseCast<double>(INT64_MIN);
loadConstantDouble(keepSignMask, scratch);
vandpd(rhs, scratch, scratch);
}
vorpd(scratch, output, output);
}
@ -2088,13 +2100,25 @@ void MacroAssembler::copySignFloat32(FloatRegister lhs, FloatRegister rhs,
FloatRegister output) {
ScratchFloat32Scope scratch(*this);
float clearSignMask = mozilla::BitwiseCast<float>(INT32_MAX);
loadConstantFloat32(clearSignMask, scratch);
vandps(scratch, lhs, output);
// TODO Support AVX2
if (rhs == output) {
MOZ_ASSERT(lhs != rhs);
float keepSignMask = mozilla::BitwiseCast<float>(INT32_MIN);
loadConstantFloat32(keepSignMask, scratch);
vandps(scratch, output, output);
float keepSignMask = mozilla::BitwiseCast<float>(INT32_MIN);
loadConstantFloat32(keepSignMask, scratch);
vandps(rhs, scratch, scratch);
float clearSignMask = mozilla::BitwiseCast<float>(INT32_MAX);
loadConstantFloat32(clearSignMask, scratch);
vandps(lhs, scratch, scratch);
} else {
float clearSignMask = mozilla::BitwiseCast<float>(INT32_MAX);
loadConstantFloat32(clearSignMask, scratch);
vandps(scratch, lhs, output);
float keepSignMask = mozilla::BitwiseCast<float>(INT32_MIN);
loadConstantFloat32(keepSignMask, scratch);
vandps(rhs, scratch, scratch);
}
vorps(scratch, output, output);
}