зеркало из https://github.com/mozilla/gecko-dev.git
Backout 48b58294a6d5 (bug 829352) for breaking the Android build on a CLOSED TREE
This commit is contained in:
Родитель
2d3b564a8f
Коммит
5c1ccd273f
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@ -502,18 +502,10 @@ public:
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#if WTF_CPU_X86_64
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void addq_rr(RegisterID src, RegisterID dst)
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{
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spew("addq %s, %s",
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nameIReg(8,src), nameIReg(8,dst));
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FIXME_INSN_PRINTING;
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m_formatter.oneByteOp64(OP_ADD_EvGv, src, dst);
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}
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void addq_mr(int offset, RegisterID base, RegisterID dst)
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{
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spew("addq %s0x%x(%s), %s",
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PRETTY_PRINT_OFFSET(offset), nameIReg(8,base), nameIReg(8,dst));
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m_formatter.oneByteOp64(OP_ADD_GvEv, dst, base, offset);
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}
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void addq_ir(int imm, RegisterID dst)
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{
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spew("addq $0x%x, %s", imm, nameIReg(8,dst));
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@ -808,18 +800,10 @@ public:
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#if WTF_CPU_X86_64
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void subq_rr(RegisterID src, RegisterID dst)
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{
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spew("subq %s, %s",
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nameIReg(8,src), nameIReg(8,dst));
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FIXME_INSN_PRINTING;
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m_formatter.oneByteOp64(OP_SUB_EvGv, src, dst);
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}
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void subq_mr(int offset, RegisterID base, RegisterID dst)
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{
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spew("subq %s0x%x(%s), %s",
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PRETTY_PRINT_OFFSET(offset), nameIReg(8,base), nameIReg(8,dst));
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m_formatter.oneByteOp64(OP_SUB_GvEv, dst, base, offset);
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}
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void subq_ir(int imm, RegisterID dst)
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{
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spew("subq $0x%x, %s", imm, nameIReg(8,dst));
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@ -1482,13 +1482,6 @@ MacroAssemblerARMCompat::addPtr(Register src, Register dest)
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ma_add(src, dest);
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}
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void
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MacroAssemblerARMCompat::addPtr(const Address &src, Register dest)
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{
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load32(src, ScratchRegister);
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ma_add(ScratchRegister, dest, SetCond);
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}
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void
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MacroAssemblerARMCompat::and32(Imm32 imm, const Address &dest)
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{
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@ -1505,24 +1498,12 @@ MacroAssemblerARMCompat::or32(Imm32 imm, const Address &dest)
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store32(ScratchRegister, dest);
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}
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void
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MacroAssemblerARMCompat::xorPtr(Imm32 imm, Register dest)
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{
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ma_eor(imm, dest);
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}
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void
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MacroAssemblerARMCompat::orPtr(Imm32 imm, Register dest)
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{
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ma_orr(imm, dest);
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}
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void
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MacroAssemblerARMCompat::andPtr(Imm32 imm, Register dest)
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{
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ma_andr(imm, dest);
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}
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void
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MacroAssemblerARMCompat::move32(const Imm32 &imm, const Register &dest)
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{
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@ -1952,13 +1933,6 @@ MacroAssemblerARMCompat::subPtr(Imm32 imm, const Register dest)
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ma_sub(imm, dest);
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}
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void
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MacroAssemblerARMCompat::subPtr(const Address &addr, const Register dest)
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{
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loadPtr(addr, ScratchRegister);
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ma_sub(ScratchRegister, dest);
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}
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void
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MacroAssemblerARMCompat::addPtr(Imm32 imm, const Register dest)
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{
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@ -925,11 +925,8 @@ class MacroAssemblerARMCompat : public MacroAssemblerARM
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void and32(Imm32 imm, Register dest);
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void and32(Imm32 imm, const Address &dest);
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void or32(Imm32 imm, const Address &dest);
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void xorPtr(Imm32 imm, Register dest);
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void orPtr(Imm32 imm, Register dest);
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void andPtr(Imm32 imm, Register dest);
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void addPtr(Register src, Register dest);
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void addPtr(const Address &src, Register dest);
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void move32(const Imm32 &imm, const Register &dest);
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@ -1026,7 +1023,6 @@ class MacroAssemblerARMCompat : public MacroAssemblerARM
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void cmpPtr(const Address &lhs, const ImmWord &rhs);
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void subPtr(Imm32 imm, const Register dest);
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void subPtr(const Address &addr, const Register dest);
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void addPtr(Imm32 imm, const Register dest);
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void addPtr(Imm32 imm, const Address &dest);
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void addPtr(ImmWord imm, const Register dest) {
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@ -390,18 +390,6 @@ class Assembler : public AssemblerX86Shared
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void addq(const Register &src, const Register &dest) {
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masm.addq_rr(src.code(), dest.code());
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}
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void addq(const Operand &src, const Register &dest) {
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switch (src.kind()) {
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case Operand::REG:
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masm.addq_rr(src.reg(), dest.code());
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break;
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case Operand::REG_DISP:
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masm.addq_mr(src.disp(), src.base(), dest.code());
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break;
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default:
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JS_NOT_REACHED("unexpected operand kind");
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}
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}
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void subq(Imm32 imm, const Register &dest) {
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masm.subq_ir(imm.value, dest.code());
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@ -409,18 +397,6 @@ class Assembler : public AssemblerX86Shared
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void subq(const Register &src, const Register &dest) {
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masm.subq_rr(src.code(), dest.code());
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}
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void subq(const Operand &src, const Register &dest) {
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switch (src.kind()) {
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case Operand::REG:
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masm.subq_rr(src.reg(), dest.code());
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break;
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case Operand::REG_DISP:
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masm.subq_mr(src.disp(), src.base(), dest.code());
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break;
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default:
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JS_NOT_REACHED("unexpected operand kind");
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}
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}
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void shlq(Imm32 imm, const Register &dest) {
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masm.shlq_i8r(imm.value, dest.code());
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}
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@ -448,9 +424,6 @@ class Assembler : public AssemblerX86Shared
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void xorq(const Register &src, const Register &dest) {
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masm.xorq_rr(src.code(), dest.code());
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}
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void xorq(Imm32 imm, const Register &dest) {
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masm.xorq_ir(imm.value, dest.code());
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}
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void mov(ImmWord word, const Register &dest) {
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movq(word, dest);
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@ -399,18 +399,12 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared
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movq(imm, ScratchReg);
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addq(ScratchReg, dest);
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}
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void addPtr(const Address &src, const Register &dest) {
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addq(Operand(src), dest);
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}
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void subPtr(Imm32 imm, const Register &dest) {
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subq(imm, dest);
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}
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void subPtr(const Register &src, const Register &dest) {
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subq(src, dest);
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}
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void subPtr(const Address &addr, const Register &dest) {
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subq(Operand(addr), dest);
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}
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// Specialization for AbsoluteAddress.
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void branchPtr(Condition cond, const AbsoluteAddress &addr, const Register &ptr, Label *label) {
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@ -497,15 +491,9 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared
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void lshiftPtr(Imm32 imm, Register dest) {
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shlq(imm, dest);
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}
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void xorPtr(Imm32 imm, Register dest) {
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xorq(imm, dest);
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}
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void orPtr(Imm32 imm, Register dest) {
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orq(imm, dest);
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}
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void andPtr(Imm32 imm, Register dest) {
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andq(imm, dest);
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}
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void splitTag(Register src, Register dest) {
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if (src != dest)
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@ -386,18 +386,9 @@ class MacroAssemblerX86 : public MacroAssemblerX86Shared
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void addPtr(Imm32 imm, const Address &dest) {
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addl(imm, Operand(dest));
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}
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void addPtr(const Address &src, const Register &dest) {
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addl(Operand(src), dest);
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}
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void subPtr(Imm32 imm, const Register &dest) {
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subl(imm, dest);
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}
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void subPtr(const Register &src, const Register &dest) {
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subl(src, dest);
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}
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void subPtr(const Address &addr, const Register &dest) {
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subl(Operand(addr), dest);
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}
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template <typename T, typename S>
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void branchPtr(Condition cond, T lhs, S ptr, Label *label) {
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@ -675,15 +666,9 @@ class MacroAssemblerX86 : public MacroAssemblerX86Shared
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void lshiftPtr(Imm32 imm, Register dest) {
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shll(imm, dest);
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}
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void xorPtr(Imm32 imm, Register dest) {
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xorl(imm, dest);
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}
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void orPtr(Imm32 imm, Register dest) {
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orl(imm, dest);
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}
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void andPtr(Imm32 imm, Register dest) {
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andl(imm, dest);
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}
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void loadInstructionPointerAfterCall(const Register &dest) {
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movl(Operand(StackPointer, 0x0), dest);
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