Fix long-range offsets on ARM. [Bug 596923] [r=nnethercote]

--HG--
extra : convert_revision : 9b1829d9cfe6fa074f308cf84bd9fe4c43b7a46e

js/src/lirasm/lirasm.cpp

@@ -2073,6 +2073,7 @@ Lirasm::Lirasm(bool verbose) :
 
     // XXX: could add more pointer-sized synonyms here
     mOpMap["paramp"] = mOpMap[PTR_SIZE("parami", "paramq")];
+    mOpMap["livep"]  = mOpMap[PTR_SIZE("livei", "liveq")];
 }
 
 Lirasm::~Lirasm()

js/src/lirasm/tests/bug596923.in

@@ -0,0 +1,17 @@
+; Try to get asm_load64 (ldd) to store straight to a stack slot with a large
+; offset from FP (on ARM, at least).
+
+a = immd 1.1
+p = allocp 1024
+std a p 0
+
+; Emit the load just before a regfence, so the result does not have a register
+; assigned.
+d = ldd p 0
+regfence
+
+retd d
+
+; Ensure that 'p' is live here, so it gets a stack slot before 'd' does (and so
+; extends the range required to store out 'd').
+livep p

js/src/lirasm/tests/bug596923.out

@@ -0,0 +1 @@
+Output is: 1.1

js/src/nanojit/NativeARM.cpp

@@ -1257,11 +1257,11 @@ Assembler::asm_restore(LIns* i, Register r)
         // memory.
         int d = findMemFor(i);
         if (ARM_VFP && IsFpReg(r)) {
-            if (isS8(d >> 2)) {
+            if (isU8(d/4) || isU8(-d/4)) {
                 FLDD(r, FP, d);
             } else {
-                FLDD(r, IP, 0);
-                asm_add_imm(IP, FP, d);
+                FLDD(r, IP, d%1024);
+                asm_add_imm(IP, FP, d-(d%1024));
             }
         } else {
             NIns merged;
@@ -1291,11 +1291,11 @@ Assembler::asm_spill(Register rr, int d, bool quad)
     NanoAssert(rr != IP);
     NanoAssert(rr != SP);
     if (ARM_VFP && IsFpReg(rr)) {
-        if (isS8(d >> 2)) {
+        if (isU8(d/4) || isU8(-d/4)) {
             FSTD(rr, FP, d);
         } else {
-            FSTD(rr, IP, 0);
-            asm_add_imm(IP, FP, d);
+            FSTD(rr, IP, d%1024);
+            asm_add_imm(IP, FP, d-(d%1024));
         }
     } else {
         NIns merged;
@@ -1342,7 +1342,7 @@ Assembler::asm_load64(LIns* ins)
                 FSTD(dd, FP, d);
             } else {
                 FSTD(dd, IP, d%1024);
-                asm_add_imm(IP, rn, d-(d%1024));
+                asm_add_imm(IP, FP, d-(d%1024));
             }
         }