Bug 1609381 - arm64 baseline simd, part 1: config, register sets, stubs. r=jseward

This lays the groundwork for ARM64 simd in the baseline compiler and
runtime.  Mostly this is non-dramatic.

The main problem to be solved is SIMD register allocation and
save/restore in the stubs.  We can't use the register sets in the
usual way to do this for reasons that are explained at length in
comments in Architecture-arm64.h, WasmStubs.cpp, and
WasmBaselineCompile.cpp, so there are a couple of cheats, that
basically come down to (sometimes contextually) treating doubles as
vectors.  By and large this is surprisingly clean.

The patch also splits a huge test file (simd/spec/nan-flavors.js) into
many smaller files so as to avoid OOM conditions when testing on
device with --ion-eager and similar switch settings that cause massive
amounts of jit code to be allocated.

Differential Revision: https://phabricator.services.mozilla.com/D90740

js/moz.configure

@@ -648,6 +648,10 @@ set_define('ENABLE_SHARED_MEMORY', enable_shared_memory)
 # Support for WebAssembly SIMD
 # =====================================================
 
+# Currently off by default for ARM64 (whether simulator or hardware)
+# and not properly supported by Cranelift, but can be enabled so as
+# to be tested with baseline.
+
 @depends('--enable-jit', '--enable-simulator', target)
 def default_wasm_simd(jit_enabled, simulator, target):
     if not jit_enabled or simulator:
@@ -666,10 +670,13 @@ def wasm_simd(value, jit_enabled, simulator, target):
         return
 
     if jit_enabled and not simulator:
-        if target.cpu in ('x86_64', 'x86'):
+        if target.cpu in ('x86_64', 'x86', 'aarch64'):
             return True
 
-    die('--enable-wasm-simd only possible when targeting the x86_64/x86 jit')
+    if jit_enabled and simulator and simulator[0] == 'arm64':
+        return True
+
+    die('--enable-wasm-simd only possible when targeting the x86_64/x86/arm64 jits')
 
 set_config('ENABLE_WASM_SIMD', wasm_simd)
 set_define('ENABLE_WASM_SIMD', wasm_simd)

js/src/jit-test/tests/wasm/simd/spec/nan-flavors2.js

@@ -0,0 +1,510 @@
+
+// Generated from simd_f32x4.wast and simd_f64x2.wast.  Generator
+// script is attached to https://bugzilla.mozilla.org/show_bug.cgi?id=1647288.
+
+// Manually split into four files following generation.
+
+// These predicates test for quiet NaNs only.
+
+function isAnyNaN32(bits) {
+    assertEq(bits & 0x7FC0_0000, 0x7FC0_0000);
+}
+function isCanonicalNaN32(bits) {
+    assertEq(bits & 0x7FFF_FFFF, 0x7FC0_0000);
+}
+function isAnyNaN64(bits) {
+    assertEq(bits & 0x7FF8_0000_0000_0000n, 0x7FF8_0000_0000_0000n);
+}
+function isCanonicalNaN64(bits) {
+    assertEq(bits & 0x7FFF_FFFF_FFFF_FFFFn, 0x7FF8_0000_0000_0000n);
+}
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 nan:0x4000000000000 nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 0x1p-1022 0x1p-1022))) (func (export "runv") (v128.store (i32.const 0) (f64x2.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.min (v128.const f64x2 nan:0x4000000000000 nan:0x4000000000000) (v128.const f64x2 0x1p-1022 0x1p-1022)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
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+isAnyNaN64(mem[0]);
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+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
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+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
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+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
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+isAnyNaN64(mem[0]);
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+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
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+`)));
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+`)));
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+`)));
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+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
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+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
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+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);

js/src/jit-test/tests/wasm/simd/spec/nan-flavors3.js

@@ -0,0 +1,762 @@
+
+// Generated from simd_f32x4.wast and simd_f64x2.wast.  Generator
+// script is attached to https://bugzilla.mozilla.org/show_bug.cgi?id=1647288.
+
+// Manually split into four files following generation.
+
+// These predicates test for quiet NaNs only.
+
+function isAnyNaN32(bits) {
+    assertEq(bits & 0x7FC0_0000, 0x7FC0_0000);
+}
+function isCanonicalNaN32(bits) {
+    assertEq(bits & 0x7FFF_FFFF, 0x7FC0_0000);
+}
+function isAnyNaN64(bits) {
+    assertEq(bits & 0x7FF8_0000_0000_0000n, 0x7FF8_0000_0000_0000n);
+}
+function isCanonicalNaN64(bits) {
+    assertEq(bits & 0x7FFF_FFFF_FFFF_FFFFn, 0x7FF8_0000_0000_0000n);
+}
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
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+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
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+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
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+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
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+ins.exports.setup(); ins.exports.runv();
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
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+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
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+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
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+ins.exports.setup(); ins.exports.runv();
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+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
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+`)));
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+`)));
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 -nan -nan -nan -nan)) (v128.store (i32.const 32) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 -nan -nan -nan -nan) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 -nan -nan -nan -nan)) (v128.store (i32.const 32) (v128.const f32x4 -nan:0x200000 -nan:0x200000 -nan:0x200000 -nan:0x200000))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 -nan -nan -nan -nan) (v128.const f32x4 -nan:0x200000 -nan:0x200000 -nan:0x200000 -nan:0x200000)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 0x0p+0 0x0p+0 0x0p+0 0x0p+0))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 0x0p+0 0x0p+0 0x0p+0 0x0p+0)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 -0x0p+0 -0x0p+0 -0x0p+0 -0x0p+0))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 -0x0p+0 -0x0p+0 -0x0p+0 -0x0p+0)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 0x1p-149 0x1p-149 0x1p-149 0x1p-149))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 0x1p-149 0x1p-149 0x1p-149 0x1p-149)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 -0x1p-149 -0x1p-149 -0x1p-149 -0x1p-149))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 -0x1p-149 -0x1p-149 -0x1p-149 -0x1p-149)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 0x1p-126 0x1p-126 0x1p-126 0x1p-126))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 0x1p-126 0x1p-126 0x1p-126 0x1p-126)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 -0x1p-126 -0x1p-126 -0x1p-126 -0x1p-126))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 -0x1p-126 -0x1p-126 -0x1p-126 -0x1p-126)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 0x1p-1 0x1p-1 0x1p-1 0x1p-1))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 0x1p-1 0x1p-1 0x1p-1 0x1p-1)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 -0x1p-1 -0x1p-1 -0x1p-1 -0x1p-1))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 -0x1p-1 -0x1p-1 -0x1p-1 -0x1p-1)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 0x1p+0 0x1p+0 0x1p+0 0x1p+0))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 0x1p+0 0x1p+0 0x1p+0 0x1p+0)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 -0x1p+0 -0x1p+0 -0x1p+0 -0x1p+0))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 -0x1p+0 -0x1p+0 -0x1p+0 -0x1p+0)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 0x1.921fb6p+2 0x1.921fb6p+2 0x1.921fb6p+2 0x1.921fb6p+2))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 0x1.921fb6p+2 0x1.921fb6p+2 0x1.921fb6p+2 0x1.921fb6p+2)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 -0x1.921fb6p+2 -0x1.921fb6p+2 -0x1.921fb6p+2 -0x1.921fb6p+2))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 -0x1.921fb6p+2 -0x1.921fb6p+2 -0x1.921fb6p+2 -0x1.921fb6p+2)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127))) (func (export "runv") (v128.store (i32.const 0) (f32x4.min (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.min (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);

js/src/jit-test/tests/wasm/simd/spec/nan-flavors4.js

@@ -0,0 +1,824 @@
+
+// Generated from simd_f32x4.wast and simd_f64x2.wast.  Generator
+// script is attached to https://bugzilla.mozilla.org/show_bug.cgi?id=1647288.
+
+// Manually split into four files following generation.
+
+// These predicates test for quiet NaNs only.
+
+function isAnyNaN32(bits) {
+    assertEq(bits & 0x7FC0_0000, 0x7FC0_0000);
+}
+function isCanonicalNaN32(bits) {
+    assertEq(bits & 0x7FFF_FFFF, 0x7FC0_0000);
+}
+function isAnyNaN64(bits) {
+    assertEq(bits & 0x7FF8_0000_0000_0000n, 0x7FF8_0000_0000_0000n);
+}
+function isCanonicalNaN64(bits) {
+    assertEq(bits & 0x7FFF_FFFF_FFFF_FFFFn, 0x7FF8_0000_0000_0000n);
+}
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 inf inf inf inf))) (func (export "runv") (v128.store (i32.const 0) (f32x4.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.max (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 inf inf inf inf)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);

js/src/jit-test/tests/wasm/simd/spec/nan-flavors5.js

@@ -0,0 +1,734 @@
+
+// Generated from simd_f32x4.wast and simd_f64x2.wast.  Generator
+// script is attached to https://bugzilla.mozilla.org/show_bug.cgi?id=1647288.
+
+// Manually split into many files following generation.
+
+// These predicates test for quiet NaNs only.
+
+function isAnyNaN32(bits) {
+    assertEq(bits & 0x7FC0_0000, 0x7FC0_0000);
+}
+function isCanonicalNaN32(bits) {
+    assertEq(bits & 0x7FFF_FFFF, 0x7FC0_0000);
+}
+function isAnyNaN64(bits) {
+    assertEq(bits & 0x7FF8_0000_0000_0000n, 0x7FF8_0000_0000_0000n);
+}
+function isCanonicalNaN64(bits) {
+    assertEq(bits & 0x7FFF_FFFF_FFFF_FFFFn, 0x7FF8_0000_0000_0000n);
+}
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
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+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
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+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
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+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
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+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN32(mem[0]);
+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
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+isCanonicalNaN32(mem[1]);
+isCanonicalNaN32(mem[2]);
+isCanonicalNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
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+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
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+ins.exports.run();
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+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 0x1p-126 0x1p-126 0x1p-126 0x1p-126))) (func (export "runv") (v128.store (i32.const 0) (f32x4.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.max (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 0x1p-126 0x1p-126 0x1p-126 0x1p-126)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 -0x1p-126 -0x1p-126 -0x1p-126 -0x1p-126))) (func (export "runv") (v128.store (i32.const 0) (f32x4.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.max (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 -0x1p-126 -0x1p-126 -0x1p-126 -0x1p-126)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 0x1p-1 0x1p-1 0x1p-1 0x1p-1))) (func (export "runv") (v128.store (i32.const 0) (f32x4.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.max (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 0x1p-1 0x1p-1 0x1p-1 0x1p-1)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 -0x1p-1 -0x1p-1 -0x1p-1 -0x1p-1))) (func (export "runv") (v128.store (i32.const 0) (f32x4.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.max (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 -0x1p-1 -0x1p-1 -0x1p-1 -0x1p-1)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000)) (v128.store (i32.const 32) (v128.const f32x4 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127))) (func (export "runv") (v128.store (i32.const 0) (f32x4.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f32x4.max (v128.const f32x4 nan:0x200000 nan:0x200000 nan:0x200000 nan:0x200000) (v128.const f32x4 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127)))))
+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
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+`)));
+var mem = new Int32Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN32(mem[0]);
+isAnyNaN32(mem[1]);
+isAnyNaN32(mem[2]);
+isAnyNaN32(mem[3]);

js/src/jit-test/tests/wasm/simd/spec/nan-flavors6.js

@@ -0,0 +1,690 @@
+
+// Generated from simd_f32x4.wast and simd_f64x2.wast.  Generator
+// script is attached to https://bugzilla.mozilla.org/show_bug.cgi?id=1647288.
+
+// Manually split into four files following generation.
+
+// These predicates test for quiet NaNs only.
+
+function isAnyNaN32(bits) {
+    assertEq(bits & 0x7FC0_0000, 0x7FC0_0000);
+}
+function isCanonicalNaN32(bits) {
+    assertEq(bits & 0x7FFF_FFFF, 0x7FC0_0000);
+}
+function isAnyNaN64(bits) {
+    assertEq(bits & 0x7FF8_0000_0000_0000n, 0x7FF8_0000_0000_0000n);
+}
+function isCanonicalNaN64(bits) {
+    assertEq(bits & 0x7FFF_FFFF_FFFF_FFFFn, 0x7FF8_0000_0000_0000n);
+}
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 nan nan)) (v128.store (i32.const 32) (v128.const f64x2 -0x1.fffffffffffffp+1023 -0x1.fffffffffffffp+1023))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 nan nan) (v128.const f64x2 -0x1.fffffffffffffp+1023 -0x1.fffffffffffffp+1023)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 nan nan)) (v128.store (i32.const 32) (v128.const f64x2 inf inf))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 nan nan) (v128.const f64x2 inf inf)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 nan nan)) (v128.store (i32.const 32) (v128.const f64x2 -inf -inf))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 nan nan) (v128.const f64x2 -inf -inf)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 nan nan)) (v128.store (i32.const 32) (v128.const f64x2 nan nan))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 nan nan) (v128.const f64x2 nan nan)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 nan nan)) (v128.store (i32.const 32) (v128.const f64x2 -nan -nan))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 nan nan) (v128.const f64x2 -nan -nan)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isCanonicalNaN64(mem[0]);
+isCanonicalNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isCanonicalNaN64(mem[0]);
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+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 -0x1p-1 -0x1p-1))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 -0x1p-1 -0x1p-1)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 0x1p+0 0x1p+0))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 0x1p+0 0x1p+0)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 -0x1p+0 -0x1p+0))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 -0x1p+0 -0x1p+0)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 0x1.921fb54442d18p+2 0x1.921fb54442d18p+2))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 0x1.921fb54442d18p+2 0x1.921fb54442d18p+2)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 -0x1.921fb54442d18p+2 -0x1.921fb54442d18p+2))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 -0x1.921fb54442d18p+2 -0x1.921fb54442d18p+2)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 0x1.fffffffffffffp+1023 0x1.fffffffffffffp+1023))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 0x1.fffffffffffffp+1023 0x1.fffffffffffffp+1023)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 -0x1.fffffffffffffp+1023 -0x1.fffffffffffffp+1023))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 -0x1.fffffffffffffp+1023 -0x1.fffffffffffffp+1023)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 inf inf))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 inf inf)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 -inf -inf))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 -inf -inf)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 nan nan))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 nan nan)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 -nan -nan))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 -nan -nan)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 nan:0x4000000000000 nan:0x4000000000000))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 nan:0x4000000000000 nan:0x4000000000000)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+var ins = new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(`
+(module (memory (export "mem") 1 1) (func (export "setup") (v128.store (i32.const 16) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)) (v128.store (i32.const 32) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000))) (func (export "runv") (v128.store (i32.const 0) (f64x2.max (v128.load (i32.const 16)) (v128.load (i32.const 32))))) (func (export "run") (v128.store (i32.const 0) (f64x2.max (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000) (v128.const f64x2 -nan:0x4000000000000 -nan:0x4000000000000)))))
+`)));
+var mem = new BigInt64Array(ins.exports.mem.buffer);
+ins.exports.run();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);
+ins.exports.setup(); ins.exports.runv();
+isAnyNaN64(mem[0]);
+isAnyNaN64(mem[1]);

js/src/jit/JitFrames.cpp

@@ -2217,9 +2217,7 @@ MachineState MachineState::FromBailout(RegisterDump::GPRArray& regs,
     machine.setRegisterLocation(
         FloatRegister(FloatRegisters::Encoding(i), FloatRegisters::Double),
         &fpregs[i]);
-#  ifdef ENABLE_WASM_SIMD
-#    error "More care needed here"
-#  endif
+    // No SIMD support in bailouts, SIMD is internal to wasm
   }
 
 #elif defined(JS_CODEGEN_NONE)

js/src/jit/Lowering.cpp

@@ -881,7 +881,8 @@ void LIRGenerator::visitTest(MTest* test) {
     }
   }
 
-#ifdef ENABLE_WASM_SIMD
+#if defined(ENABLE_WASM_SIMD) && \
+    (defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64))
   // Check if the operand for this test is an any_true/all_true SIMD operation.
   // If it is, we want to emit an LWasmReduceAndBranchSimd128 node to avoid
   // generating an intermediate boolean result.
@@ -5660,7 +5661,8 @@ void LIRGenerator::visitWasmFloatConstant(MWasmFloatConstant* ins) {
     case MIRType::Float32:
       define(new (alloc()) LFloat32(ins->toFloat32()), ins);
       break;
-#ifdef ENABLE_WASM_SIMD
+#if defined(ENABLE_WASM_SIMD) && \
+    (defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64))
     case MIRType::Simd128:
       define(new (alloc()) LSimd128(ins->toSimd128()), ins);
       break;

js/src/jit/arm64/Architecture-arm64.cpp

@@ -46,11 +46,10 @@ FloatRegisters::Code FloatRegisters::FromName(const char* name) {
   return Invalid;
 }
 
-FloatRegisterSet FloatRegister::ReduceSetForPush(const FloatRegisterSet& s) {
-#ifdef ENABLE_WASM_SIMD
-#  error "Needs more careful logic if SIMD is enabled"
-#endif
+// These assume no SIMD registers as the register sets do not directly support
+// SIMD.  When SIMD is needed (wasm baseline + stubs), other routines are used.
 
+FloatRegisterSet FloatRegister::ReduceSetForPush(const FloatRegisterSet& s) {
   LiveFloatRegisterSet ret;
   for (FloatRegisterIterator iter(s); iter.more(); ++iter) {
     ret.addUnchecked(FromCode((*iter).encoding()));
@@ -59,23 +58,22 @@ FloatRegisterSet FloatRegister::ReduceSetForPush(const FloatRegisterSet& s) {
 }
 
 uint32_t FloatRegister::GetPushSizeInBytes(const FloatRegisterSet& s) {
-#ifdef ENABLE_WASM_SIMD
-#  error "Needs more careful logic if SIMD is enabled"
-#endif
-
   return s.size() * sizeof(double);
 }
 
 uint32_t FloatRegister::getRegisterDumpOffsetInBytes() {
-#ifdef ENABLE_WASM_SIMD
-#  error "Needs more careful logic if SIMD is enabled"
-#endif
-
   // Although registers are 128-bits wide, only the first 64 need saving per
   // ABI.
   return encoding() * sizeof(double);
 }
 
+#if defined(ENABLE_WASM_SIMD)
+uint32_t FloatRegister::GetPushSizeInBytesForWasmStubs(
+    const FloatRegisterSet& s) {
+  return s.size() * SizeOfSimd128;
+}
+#endif
+
 uint32_t GetARM64Flags() { return 0; }
 
 void FlushICache(void* code, size_t size, bool codeIsThreadLocal) {

js/src/jit/arm64/Architecture-arm64.h

@@ -326,7 +326,44 @@ class FloatRegisters {
   typedef FPRegisterID Encoding;
   typedef uint64_t SetType;
 
-  enum Kind : uint8_t { Double, Single, NumTypes };
+  // WARNING!  About SIMD registers on Arm64:
+  //
+  // There is a Kind 'Simd128' but registers of this kind cannot be stored in
+  // register sets, the kind exists only to tag FloatRegisters as vector
+  // registers for use outside the sets, see below.  The reason for this
+  // weirdness is that the 64-bit SetType is too small to hold information about
+  // vector registers, and we have poor options for making SetType larger.
+  //
+  // (We have two options for increasing the size of SetType: __uint128_t and
+  // some simulation of __uint128_t or perhaps __uint96_t.  Using __uint128_t
+  // does not work because C++ compilers generate aligned accesses to
+  // __uint128_t fields, and structures containing register sets are frequently
+  // not properly aligned because they are allocated with TempAllocator.  Using
+  // a simulation will result in a lot of code, possibly reduce inlining of set
+  // operations, and slow down JS compilation.  We don't want to pay the penalty
+  // unless we have to.)
+  //
+  // Only the baseline compiler and the wasm stubs code need to deal with Arm64
+  // vector registers, Ion will never be exposed because JS does not have SIMD
+  // and we don't have Arm64 wasm support in Ion.  So a fix that introduces the
+  // notion of vector registers but does not allow them to be put into sets
+  // works fairly well: The baseline compiler manages vector registers by
+  // managing the double registers which alias the vector registers, while the
+  // stubs code uses special save and restore paths that always save and restore
+  // the vector registers when they may contain meaningful data.  The complexity
+  // is local to the stubs code, the lowest level of the register management
+  // code in the baseline compiler, and the code in this file.
+
+  enum Kind : uint8_t {
+    Double,
+    Single,
+#ifdef ENABLE_WASM_SIMD
+    Simd128,
+#endif
+    NumTypes
+  };
+
+  static constexpr int NumScalarTypes = 2;
 
   static constexpr Code Invalid = 0x80;
 
@@ -339,10 +376,17 @@ class FloatRegisters {
         "d30", "d31", "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",
         "s8",  "s9",  "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17",
         "s18", "s19", "s20", "s21", "s22", "s23", "s24", "s25", "s26", "s27",
-        "s28", "s29", "s30", "s31"};
-    static_assert(Total == sizeof(Names) / sizeof(Names[0]),
+        "s28", "s29", "s30", "s31",
+#ifdef ENABLE_WASM_SIMD
+        "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",
+        "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19",
+        "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29",
+        "v30", "v31",
+#endif
+    };
+    static_assert(TotalWithSimd == sizeof(Names) / sizeof(Names[0]),
                   "Table is the correct size");
-    if (code >= Total) {
+    if (code >= TotalWithSimd) {
       return "invalid";
     }
     return Names[code];
@@ -351,7 +395,8 @@ class FloatRegisters {
   static Code FromName(const char* name);
 
   static const uint32_t TotalPhys = 32;
-  static const uint32_t Total = TotalPhys * NumTypes;
+  static const uint32_t Total = TotalPhys * NumScalarTypes;
+  static const uint32_t TotalWithSimd = TotalPhys * NumTypes;
   static const uint32_t Allocatable = 31;  // Without d31, the scratch register.
 
   static_assert(sizeof(SetType) * 8 >= Total,
@@ -400,12 +445,14 @@ class FloatRegisters {
   };
 
   static constexpr Encoding encoding(Code c) {
-    // assert(c < Total);
+    // assert() not available in constexpr function.
+    // assert(c < TotalWithSimd);
     return Encoding(c & 31);
   }
 
   static constexpr Kind kind(Code c) {
-    // assert(c < Total && ((c >> 5) & 3) < NumTypes);
+    // assert() not available in constexpr function.
+    // assert(c < TotalWithSimd && ((c >> 5) & 3) < NumTypes);
     return Kind((c >> 5) & 3);
   }
 
@@ -461,11 +508,13 @@ struct FloatRegister {
     return 63 - mozilla::CountLeadingZeroes64(x);
   }
 
+  static constexpr size_t SizeOfSimd128 = 16;
+
  private:
   // These fields only hold valid values: an invalid register is always
   // represented as a valid encoding and kind with the invalid_ bit set.
   uint8_t encoding_;  // 32 encodings
-  uint8_t kind_;      // Double, Single; more later
+  uint8_t kind_;      // Double, Single, Simd128
   bool invalid_;
 
   typedef Codes::Kind Kind;
@@ -480,7 +529,7 @@ struct FloatRegister {
       : encoding_(0), kind_(FloatRegisters::Double), invalid_(true) {}
 
   static FloatRegister FromCode(uint32_t i) {
-    MOZ_ASSERT(i < Codes::Total);
+    MOZ_ASSERT(i < Codes::TotalWithSimd);
     return FloatRegister(FloatRegisters::encoding(i), FloatRegisters::kind(i));
   }
 
@@ -494,7 +543,11 @@ struct FloatRegister {
   }
   bool isSimd128() const {
     MOZ_ASSERT(!invalid_);
+#ifdef ENABLE_WASM_SIMD
+    return kind_ == FloatRegisters::Simd128;
+#else
     return false;
+#endif
   }
   bool isInvalid() const { return invalid_; }
 
@@ -506,15 +559,29 @@ struct FloatRegister {
     MOZ_ASSERT(!invalid_);
     return FloatRegister(Encoding(encoding_), FloatRegisters::Double);
   }
-  FloatRegister asSimd128() const { MOZ_CRASH(); }
+  FloatRegister asSimd128() const {
+    MOZ_ASSERT(!invalid_);
+#ifdef ENABLE_WASM_SIMD
+    return FloatRegister(Encoding(encoding_), FloatRegisters::Simd128);
+#else
+    MOZ_CRASH("No SIMD support");
+#endif
+  }
 
   constexpr uint32_t size() const {
     MOZ_ASSERT(!invalid_);
     if (kind_ == FloatRegisters::Double) {
       return sizeof(double);
     }
-    MOZ_ASSERT(kind_ == FloatRegisters::Single);
-    return sizeof(float);
+    if (kind_ == FloatRegisters::Single) {
+      return sizeof(float);
+    }
+#ifdef ENABLE_WASM_SIMD
+    MOZ_ASSERT(kind_ == FloatRegisters::Simd128);
+    return 16;
+#else
+    MOZ_CRASH("No SIMD support");
+#endif
   }
 
   constexpr Code code() const {
@@ -552,7 +619,10 @@ struct FloatRegister {
     return kind_ == other.kind_;
   }
 
-  uint32_t numAliased() const { return Codes::NumTypes; }
+  // numAliased is used only by Ion's register allocator, ergo we ignore SIMD
+  // registers here as Ion will not be exposed to SIMD on this platform.  See
+  // comments above in FloatRegisters.
+  uint32_t numAliased() const { return Codes::NumScalarTypes; }
   uint32_t numAlignedAliased() { return numAliased(); }
 
   FloatRegister aliased(uint32_t aliasIdx) {
@@ -585,6 +655,10 @@ struct FloatRegister {
   static TypedRegisterSet<FloatRegister> ReduceSetForPush(
       const TypedRegisterSet<FloatRegister>& s);
   static uint32_t GetPushSizeInBytes(const TypedRegisterSet<FloatRegister>& s);
+#ifdef ENABLE_WASM_SIMD
+  static uint32_t GetPushSizeInBytesForWasmStubs(
+      const TypedRegisterSet<FloatRegister>& s);
+#endif
   uint32_t getRegisterDumpOffsetInBytes();
 };
 

js/src/jit/arm64/Assembler-arm64.cpp

@@ -59,6 +59,19 @@ ABIArg ABIArgGenerator::next(MIRType type) {
       floatRegIndex_++;
       break;
 
+#ifdef ENABLE_WASM_SIMD
+    case MIRType::Simd128:
+      if (floatRegIndex_ == NumFloatArgRegs) {
+        current_ = ABIArg(stackOffset_);
+        stackOffset_ += FloatRegister::SizeOfSimd128;
+        break;
+      }
+      current_ = ABIArg(FloatRegister(FloatRegisters::Encoding(floatRegIndex_),
+                                      FloatRegisters::Simd128));
+      floatRegIndex_++;
+      break;
+#endif
+
     default:
       // Note that in Assembler-x64.cpp there's a special case for Win64 which
       // does not allow passing SIMD by value.  Since there's Win64 on ARM64 we

js/src/jit/arm64/Assembler-arm64.h

@@ -55,6 +55,24 @@ struct ScratchFloat32Scope : public AutoFloatRegisterScope {
       : AutoFloatRegisterScope(masm, ScratchFloat32Reg) {}
 };
 
+#ifdef ENABLE_WASM_SIMD
+static constexpr FloatRegister ReturnSimd128Reg = {FloatRegisters::v0,
+                                                   FloatRegisters::Simd128};
+static constexpr FloatRegister ScratchSimd128Reg = {FloatRegisters::v31,
+                                                    FloatRegisters::Simd128};
+struct ScratchSimd128Scope : public AutoFloatRegisterScope {
+  explicit ScratchSimd128Scope(MacroAssembler& masm)
+      : AutoFloatRegisterScope(masm, ScratchSimd128Reg) {}
+};
+#else
+struct ScratchSimd128Scope : public AutoFloatRegisterScope {
+  explicit ScratchSimd128Scope(MacroAssembler& masm)
+      : AutoFloatRegisterScope(masm, ScratchDoubleReg) {
+    MOZ_CRASH("SIMD not enabled");
+  }
+};
+#endif
+
 static constexpr Register InvalidReg{Registers::Invalid};
 static constexpr FloatRegister InvalidFloatReg = {};
 
@@ -78,9 +96,6 @@ static constexpr Register ZeroRegister{Registers::sp};
 static constexpr ARMRegister ZeroRegister64 = {Registers::sp, 64};
 static constexpr ARMRegister ZeroRegister32 = {Registers::sp, 32};
 
-static constexpr FloatRegister ReturnSimd128Reg = InvalidFloatReg;
-static constexpr FloatRegister ScratchSimd128Reg = InvalidFloatReg;
-
 // StackPointer is intentionally undefined on ARM64 to prevent misuse:
 //  using sp as a base register is only valid if sp % 16 == 0.
 static constexpr Register RealStackPointer{Registers::sp};
@@ -277,6 +292,7 @@ class Assembler : public vixl::Assembler {
   static bool SupportsFloatingPoint() { return true; }
   static bool SupportsUnalignedAccesses() { return true; }
   static bool SupportsFastUnalignedAccesses() { return true; }
+  static bool SupportsWasmSimd() { return true; }
 
   static bool HasRoundInstruction(RoundingMode mode) { return false; }
 

js/src/jit/arm64/MacroAssembler-arm64.cpp

@@ -463,12 +463,12 @@ void MacroAssembler::flush() { Assembler::flush(); }
 
 // ===============================================================
 // Stack manipulation functions.
+//
+// These all assume no SIMD registers, because SIMD registers are handled with
+// other routines when that is necessary.  See lengthy comment in
+// Architecture-arm64.h.
 
 void MacroAssembler::PushRegsInMask(LiveRegisterSet set) {
-#ifdef ENABLE_WASM_SIMD
-#  error "Needs more careful logic if SIMD is enabled"
-#endif
-
   for (GeneralRegisterBackwardIterator iter(set.gprs()); iter.more();) {
     vixl::CPURegister src[4] = {vixl::NoCPUReg, vixl::NoCPUReg, vixl::NoCPUReg,
                                 vixl::NoCPUReg};
@@ -497,10 +497,6 @@ void MacroAssembler::PushRegsInMask(LiveRegisterSet set) {
 
 void MacroAssembler::storeRegsInMask(LiveRegisterSet set, Address dest,
                                      Register scratch) {
-#ifdef ENABLE_WASM_SIMD
-#  error "Needs more careful logic if SIMD is enabled"
-#endif
-
   FloatRegisterSet fpuSet(set.fpus().reduceSetForPush());
   unsigned numFpu = fpuSet.size();
   int32_t diffF = fpuSet.getPushSizeInBytes();
@@ -537,10 +533,6 @@ void MacroAssembler::storeRegsInMask(LiveRegisterSet set, Address dest,
 
 void MacroAssembler::PopRegsInMaskIgnore(LiveRegisterSet set,
                                          LiveRegisterSet ignore) {
-#ifdef ENABLE_WASM_SIMD
-#  error "Needs more careful logic if SIMD is enabled"
-#endif
-
   // The offset of the data from the stack pointer.
   uint32_t offset = 0;
 
@@ -599,6 +591,100 @@ void MacroAssembler::PopRegsInMaskIgnore(LiveRegisterSet set,
   freeStack(bytesPushed);
 }
 
+#ifdef ENABLE_WASM_SIMD
+void MacroAssemblerCompat::PushRegsInMaskForWasmStubs(LiveRegisterSet set) {
+  for (GeneralRegisterBackwardIterator iter(set.gprs()); iter.more();) {
+    vixl::CPURegister src[4] = {vixl::NoCPUReg, vixl::NoCPUReg, vixl::NoCPUReg,
+                                vixl::NoCPUReg};
+
+    for (size_t i = 0; i < 4 && iter.more(); i++) {
+      src[i] = ARMRegister(*iter, 64);
+      ++iter;
+      asMasm().adjustFrame(8);
+    }
+    vixl::MacroAssembler::Push(src[0], src[1], src[2], src[3]);
+  }
+
+  // reduceSetForPush returns a set with the unique encodings and kind==0.  For
+  // each encoding in the set, just push the SIMD register.
+  for (FloatRegisterBackwardIterator iter(set.fpus().reduceSetForPush());
+       iter.more();) {
+    vixl::CPURegister src[4] = {vixl::NoCPUReg, vixl::NoCPUReg, vixl::NoCPUReg,
+                                vixl::NoCPUReg};
+
+    for (size_t i = 0; i < 4 && iter.more(); i++) {
+      src[i] = ARMFPRegister(*iter, 128);
+      ++iter;
+      asMasm().adjustFrame(FloatRegister::SizeOfSimd128);
+    }
+    vixl::MacroAssembler::Push(src[0], src[1], src[2], src[3]);
+  }
+}
+
+void MacroAssemblerCompat::PopRegsInMaskForWasmStubs(LiveRegisterSet set,
+                                                     LiveRegisterSet ignore) {
+  // The offset of the data from the stack pointer.
+  uint32_t offset = 0;
+
+  // See comments above
+  for (FloatRegisterIterator iter(set.fpus().reduceSetForPush());
+       iter.more();) {
+    vixl::CPURegister dest[2] = {vixl::NoCPUReg, vixl::NoCPUReg};
+    uint32_t nextOffset = offset;
+
+    for (size_t i = 0; i < 2 && iter.more(); i++) {
+      if (!ignore.has(*iter)) {
+        dest[i] = ARMFPRegister(*iter, 128);
+      }
+      ++iter;
+      nextOffset += FloatRegister::SizeOfSimd128;
+    }
+
+    if (!dest[0].IsNone() && !dest[1].IsNone()) {
+      Ldp(dest[0], dest[1], MemOperand(GetStackPointer64(), offset));
+    } else if (!dest[0].IsNone()) {
+      Ldr(dest[0], MemOperand(GetStackPointer64(), offset));
+    } else if (!dest[1].IsNone()) {
+      Ldr(dest[1], MemOperand(GetStackPointer64(), offset + 16));
+    }
+
+    offset = nextOffset;
+  }
+
+  MOZ_ASSERT(offset ==
+             FloatRegister::GetPushSizeInBytesForWasmStubs(set.fpus()));
+
+  for (GeneralRegisterIterator iter(set.gprs()); iter.more();) {
+    vixl::CPURegister dest[2] = {vixl::NoCPUReg, vixl::NoCPUReg};
+    uint32_t nextOffset = offset;
+
+    for (size_t i = 0; i < 2 && iter.more(); i++) {
+      if (!ignore.has(*iter)) {
+        dest[i] = ARMRegister(*iter, 64);
+      }
+      ++iter;
+      nextOffset += sizeof(uint64_t);
+    }
+
+    if (!dest[0].IsNone() && !dest[1].IsNone()) {
+      Ldp(dest[0], dest[1], MemOperand(GetStackPointer64(), offset));
+    } else if (!dest[0].IsNone()) {
+      Ldr(dest[0], MemOperand(GetStackPointer64(), offset));
+    } else if (!dest[1].IsNone()) {
+      Ldr(dest[1], MemOperand(GetStackPointer64(), offset + sizeof(uint64_t)));
+    }
+
+    offset = nextOffset;
+  }
+
+  size_t bytesPushed =
+      set.gprs().size() * sizeof(uint64_t) +
+      FloatRegister::GetPushSizeInBytesForWasmStubs(set.fpus());
+  MOZ_ASSERT(offset == bytesPushed);
+  asMasm().freeStack(bytesPushed);
+}
+#endif
+
 void MacroAssembler::Push(Register reg) {
   push(reg);
   adjustFrame(sizeof(intptr_t));

js/src/jit/arm64/MacroAssembler-arm64.h

@@ -250,6 +250,11 @@ class MacroAssemblerCompat : public vixl::MacroAssembler {
     vixl::MacroAssembler::Drop(Operand(ARMRegister(amount, 64)));
   }
 
+#ifdef ENABLE_WASM_SIMD
+  void PushRegsInMaskForWasmStubs(LiveRegisterSet set);
+  void PopRegsInMaskForWasmStubs(LiveRegisterSet set, LiveRegisterSet ignore);
+#endif
+
   // Update sp with the value of the current active stack pointer, if necessary.
   void syncStackPtr() {
     if (!GetStackPointer64().Is(vixl::sp)) {

js/src/jit/arm64/Trampoline-arm64.cpp

@@ -491,9 +491,7 @@ void JitRuntime::generateArgumentsRectifier(MacroAssembler& masm,
 }
 
 static void PushBailoutFrame(MacroAssembler& masm, Register spArg) {
-#ifdef ENABLE_WASM_SIMD
-#  error "Needs more careful logic if SIMD is enabled"
-#endif
+  // This assumes no SIMD registers, as JS does not support SIMD.
 
   // The stack saved in spArg must be (higher entries have higher memory
   // addresses):

js/src/jit/shared/CodeGenerator-shared.cpp

@@ -84,8 +84,9 @@ CodeGeneratorShared::CodeGeneratorShared(MIRGenerator* gen, LIRGraph* graph,
     frameDepth_ += gen->wasmMaxStackArgBytes();
 
 #ifdef ENABLE_WASM_SIMD
-#  if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86)
-    // On X64 and x86, we don't need alignment for Wasm SIMD at this time.
+#  if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86) || \
+      defined(JS_CODEGEN_ARM64)
+    // On X64/x86 and ARM64, we don't need alignment for Wasm SIMD at this time.
 #  else
 #    error \
         "we may need padding so that local slots are SIMD-aligned and the stack must be kept SIMD-aligned too."

js/src/jit/shared/Lowering-shared-inl.h

@@ -292,9 +292,13 @@ void LIRGeneratorShared::defineReturn(LInstruction* lir, MDefinition* mir) {
                                  LFloatReg(ReturnDoubleReg)));
       break;
     case MIRType::Simd128:
+#ifdef ENABLE_WASM_SIMD
       lir->setDef(0, LDefinition(vreg, LDefinition::SIMD128,
                                  LFloatReg(ReturnSimd128Reg)));
       break;
+#else
+      MOZ_CRASH("No SIMD support");
+#endif
     default:
       LDefinition::Type type = LDefinition::TypeFrom(mir->type());
       switch (type) {

js/src/jit/shared/Lowering-shared.cpp

@@ -301,7 +301,7 @@ void LIRGeneratorShared::assignWasmSafepoint(LInstruction* ins,
   }
 }
 
-#ifndef ENABLE_WASM_SIMD
+#if !defined(ENABLE_WASM_SIMD) || defined(JS_CODEGEN_ARM64)
 
 void LIRGenerator::visitWasmBitselectSimd128(MWasmBitselectSimd128*) {
   MOZ_CRASH("SIMD not enabled");

js/src/wasm/WasmBaselineCompile.cpp

@@ -205,9 +205,11 @@ static constexpr FloatRegister RabaldrScratchF64 = InvalidFloatReg;
 
 #ifdef JS_CODEGEN_ARM64
 #  define RABALDR_CHUNKY_STACK
+#  define RABALDR_SIDEALLOC_V128
 #  define RABALDR_SCRATCH_I32
 #  define RABALDR_SCRATCH_F32
 #  define RABALDR_SCRATCH_F64
+#  define RABALDR_SCRATCH_V128
 #  define RABALDR_SCRATCH_F32_ALIASES_F64
 
 static constexpr Register RabaldrScratchI32{Registers::x15};
@@ -220,9 +222,16 @@ static constexpr FloatRegister RabaldrScratchF32{FloatRegisters::s30,
                                                  FloatRegisters::Single};
 static constexpr FloatRegister RabaldrScratchF64{FloatRegisters::d30,
                                                  FloatRegisters::Double};
+#  ifdef ENABLE_WASM_SIMD
+static constexpr FloatRegister RabaldrScratchV128{FloatRegisters::d30,
+                                                  FloatRegisters::Simd128};
+#  endif
 
 static_assert(RabaldrScratchF32 != ScratchFloat32Reg, "Too busy");
 static_assert(RabaldrScratchF64 != ScratchDoubleReg, "Too busy");
+#  ifdef ENABLE_WASM_SIMD
+static_assert(RabaldrScratchV128 != ScratchSimd128Reg, "Too busy");
+#  endif
 #endif
 
 #ifdef JS_CODEGEN_X86
@@ -357,6 +366,40 @@ struct RegF64 : public FloatRegister {
 };
 
 #ifdef ENABLE_WASM_SIMD
+#  ifdef RABALDR_SIDEALLOC_V128
+class RegV128 {
+  // fpr_ is either invalid or a double that aliases the simd register, see
+  // comments below at BaseRegAlloc.
+  FloatRegister fpr_;
+
+ public:
+  RegV128() : fpr_(FloatRegister()) {}
+  explicit RegV128(FloatRegister reg)
+      : fpr_(FloatRegister(reg.encoding(), FloatRegisters::Double)) {
+    MOZ_ASSERT(reg.isSimd128());
+  }
+  static RegV128 fromDouble(FloatRegister reg) {
+    MOZ_ASSERT(reg.isDouble());
+    return RegV128(FloatRegister(reg.encoding(), FloatRegisters::Simd128));
+  }
+  FloatRegister asDouble() const { return fpr_; }
+  bool isInvalid() const { return fpr_.isInvalid(); }
+  bool isValid() const { return !isInvalid(); }
+  static RegV128 Invalid() { return RegV128(); }
+
+  operator FloatRegister() const {
+    return FloatRegister(fpr_.encoding(), FloatRegisters::Simd128);
+  }
+
+  bool operator==(const RegV128& that) const {
+    return asDouble() == that.asDouble();
+  }
+
+  bool operator!=(const RegV128& that) const {
+    return asDouble() != that.asDouble();
+  }
+};
+#  else
 struct RegV128 : public FloatRegister {
   RegV128() : FloatRegister() {}
   explicit RegV128(FloatRegister reg) : FloatRegister(reg) {
@@ -365,6 +408,7 @@ struct RegV128 : public FloatRegister {
   bool isValid() const { return !isInvalid(); }
   static RegV128 Invalid() { return RegV128(); }
 };
+#  endif
 #endif
 
 struct AnyReg {
@@ -571,15 +615,21 @@ class BaseRegAlloc {
   // properly with aliasing of registers: if s0 or s1 are allocated then d0 is
   // not allocatable; if s0 and s1 are freed individually then d0 becomes
   // allocatable.
+  //
+  // On platforms with RABALDR_SIDEALLOC_V128, the register set does not
+  // represent SIMD registers.  Instead, we allocate and free these registers as
+  // doubles and change the kind to Simd128 while the register is exposed to
+  // masm.  (This is the case on ARM64 for now, and is a consequence of needing
+  // more than 64 bits for FloatRegisters::SetType to represent SIMD registers.
+  // See lengty comment in Architecture-arm64.h.)
 
   BaseCompilerInterface* bc;
   AllocatableGeneralRegisterSet availGPR;
   AllocatableFloatRegisterSet availFPU;
 #ifdef DEBUG
-  AllocatableGeneralRegisterSet
-      allGPR;  // The registers available to the compiler
-  AllocatableFloatRegisterSet
-      allFPU;  //   after removing ScratchReg, HeapReg, etc
+  // The registers available after removing ScratchReg, HeapReg, etc.
+  AllocatableGeneralRegisterSet allGPR;
+  AllocatableFloatRegisterSet allFPU;
   uint32_t scratchTaken;
 #endif
 #ifdef JS_CODEGEN_X86
@@ -607,9 +657,21 @@ class BaseRegAlloc {
     return availFPU.hasAny<RegTypeOf<t>::value>();
   }
 
+#ifdef RABALDR_SIDEALLOC_V128
+  template <>
+  bool hasFPU<MIRType::Simd128>() {
+    MOZ_CRASH("Should not happen");
+  }
+#endif
+
   bool isAvailableGPR(Register r) { return availGPR.has(r); }
 
-  bool isAvailableFPU(FloatRegister r) { return availFPU.has(r); }
+  bool isAvailableFPU(FloatRegister r) {
+#ifdef RABALDR_SIDEALLOC_V128
+    MOZ_ASSERT(!r.isSimd128());
+#endif
+    return availFPU.has(r);
+  }
 
   void allocGPR(Register r) {
     MOZ_ASSERT(isAvailableGPR(r));
@@ -674,6 +736,9 @@ class BaseRegAlloc {
 #endif
 
   void allocFPU(FloatRegister r) {
+#ifdef RABALDR_SIDEALLOC_V128
+    MOZ_ASSERT(!r.isSimd128());
+#endif
     MOZ_ASSERT(isAvailableFPU(r));
     availFPU.take(r);
   }
@@ -683,6 +748,13 @@ class BaseRegAlloc {
     return availFPU.takeAny<RegTypeOf<t>::value>();
   }
 
+#ifdef RABALDR_SIDEALLOC_V128
+  template <>
+  FloatRegister allocFPU<MIRType::Simd128>() {
+    MOZ_CRASH("Should not happen");
+  }
+#endif
+
   void freeGPR(Register r) { availGPR.add(r); }
 
   void freeInt64(Register64 r) {
@@ -694,7 +766,12 @@ class BaseRegAlloc {
 #endif
   }
 
-  void freeFPU(FloatRegister r) { availFPU.add(r); }
+  void freeFPU(FloatRegister r) {
+#ifdef RABALDR_SIDEALLOC_V128
+    MOZ_ASSERT(!r.isSimd128());
+#endif
+    availFPU.add(r);
+  }
 
  public:
   explicit BaseRegAlloc()
@@ -787,7 +864,11 @@ class BaseRegAlloc {
   bool isAvailableF64(RegF64 r) { return isAvailableFPU(r); }
 
 #ifdef ENABLE_WASM_SIMD
+#  ifdef RABALDR_SIDEALLOC_V128
+  bool isAvailableV128(RegV128 r) { return isAvailableFPU(r.asDouble()); }
+#  else
   bool isAvailableV128(RegV128 r) { return isAvailableFPU(r); }
+#  endif
 #endif
 
   // TODO / OPTIMIZE (Bug 1316802): Do not sync everything on allocation
@@ -879,17 +960,31 @@ class BaseRegAlloc {
 
 #ifdef ENABLE_WASM_SIMD
   MOZ_MUST_USE RegV128 needV128() {
+#  ifdef RABALDR_SIDEALLOC_V128
+    if (!hasFPU<MIRType::Double>()) {
+      bc->sync();
+    }
+    return RegV128::fromDouble(allocFPU<MIRType::Double>());
+#  else
     if (!hasFPU<MIRType::Simd128>()) {
       bc->sync();
     }
     return RegV128(allocFPU<MIRType::Simd128>());
+#  endif
   }
 
   void needV128(RegV128 specific) {
+#  ifdef RABALDR_SIDEALLOC_V128
+    if (!isAvailableV128(specific)) {
+      bc->sync();
+    }
+    allocFPU(specific.asDouble());
+#  else
     if (!isAvailableV128(specific)) {
       bc->sync();
     }
     allocFPU(specific);
+#  endif
   }
 #endif
 
@@ -904,7 +999,13 @@ class BaseRegAlloc {
   void freeF32(RegF32 r) { freeFPU(r); }
 
 #ifdef ENABLE_WASM_SIMD
-  void freeV128(RegV128 r) { freeFPU(r); }
+  void freeV128(RegV128 r) {
+#  ifdef RABALDR_SIDEALLOC_V128
+    freeFPU(r.asDouble());
+#  else
+    freeFPU(r);
+#  endif
+  }
 #endif
 
   void freeTempPtr(RegPtr r, bool saved) {
@@ -962,7 +1063,13 @@ class BaseRegAlloc {
     void addKnownF64(RegF64 r) { knownFPU_.add(r); }
 
 #  ifdef ENABLE_WASM_SIMD
-    void addKnownV128(RegV128 r) { knownFPU_.add(r); }
+    void addKnownV128(RegV128 r) {
+#    ifdef RABALDR_SIDEALLOC_V128
+      knownFPU_.add(r.asDouble());
+#    else
+      knownFPU_.add(r);
+#    endif
+    }
 #  endif
 
     void addKnownRef(RegPtr r) { knownGPR_.add(r); }
@@ -1000,7 +1107,12 @@ class BaseScratchRegister {
 
 #ifdef ENABLE_WASM_SIMD
 #  ifdef RABALDR_SCRATCH_V128
-#    error "Not yet"
+class ScratchV128 : public BaseScratchRegister {
+ public:
+  explicit ScratchV128(BaseRegAlloc& ra)
+      : BaseScratchRegister(ra, BaseRegAlloc::ScratchKind::V128) {}
+  operator RegV128() const { return RegV128(RabaldrScratchV128); }
+};
 #  else
 class ScratchV128 : public ScratchSimd128Scope {
  public:
@@ -1947,7 +2059,7 @@ class BaseStackFrame final : public BaseStackFrameAllocator {
   uint32_t pushV128(RegV128 r) {
     DebugOnly<uint32_t> stackBefore = currentStackHeight();
 #  ifdef RABALDR_CHUNKY_STACK
-    pushChunkyBytes(bytes);
+    pushChunkyBytes(StackSizeOfV128);
 #  else
     masm.adjustStack(-(int)StackSizeOfV128);
 #  endif
@@ -5655,7 +5767,7 @@ class BaseCompiler final : public BaseCompilerInterface {
             ScratchV128 scratch(*this);
             loadV128(arg, scratch);
             masm.storeUnalignedSimd128(
-                scratch,
+                (RegV128)scratch,
                 Address(masm.getStackPointer(), argLoc.offsetFromArgBase()));
             break;
           }
@@ -13626,6 +13738,7 @@ bool BaseCompiler::emitVectorShuffle() {
 
 // Must be scalarized on x86/x64 and requires CL.
 bool BaseCompiler::emitVectorShiftRightI64x2() {
+#  if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
   Nothing unused_a, unused_b;
 
   if (!iter_.readVectorShift(&unused_a, &unused_b)) {
@@ -13652,6 +13765,9 @@ bool BaseCompiler::emitVectorShiftRightI64x2() {
   pushV128(lhsDest);
 
   return true;
+#  else
+  MOZ_CRASH("NYI");
+#  endif
 }
 #endif
 

js/src/wasm/WasmStubs.cpp

@@ -132,6 +132,42 @@ void ABIResultIter::settlePrev() {
   cur_ = ABIResult(type, nextStackOffset_);
 }
 
+// Register save/restore.
+//
+// On ARM64, the register sets are not able to represent SIMD registers (see
+// lengthy comment in Architecture-arm64.h for information), and so we use a
+// hack to save and restore them: on this architecture, when we care about SIMD,
+// we call special routines that know about them.
+//
+// In a couple of cases it is not currently necessary to save and restore SIMD
+// registers, but the extra traffic is all along slow paths and not really worth
+// optimizing.
+static void PushRegsInMask(MacroAssembler& masm, const LiveRegisterSet& set) {
+#if defined(ENABLE_WASM_SIMD) && defined(JS_CODEGEN_ARM64)
+  masm.PushRegsInMaskForWasmStubs(set);
+#else
+  masm.PushRegsInMask(set);
+#endif
+}
+
+static void PopRegsInMask(MacroAssembler& masm, const LiveRegisterSet& set) {
+#if defined(ENABLE_WASM_SIMD) && defined(JS_CODEGEN_ARM64)
+  masm.PopRegsInMaskForWasmStubs(set, LiveRegisterSet());
+#else
+  masm.PopRegsInMask(set);
+#endif
+}
+
+static void PopRegsInMaskIgnore(MacroAssembler& masm,
+                                const LiveRegisterSet& set,
+                                const LiveRegisterSet& ignore) {
+#if defined(ENABLE_WASM_SIMD) && defined(JS_CODEGEN_ARM64)
+  masm.PopRegsInMaskForWasmStubs(set, ignore);
+#else
+  masm.PopRegsInMaskIgnore(set, ignore);
+#endif
+}
+
 #ifdef WASM_CODEGEN_DEBUG
 template <class Closure>
 static void GenPrint(DebugChannel channel, MacroAssembler& masm,
@@ -142,7 +178,7 @@ static void GenPrint(DebugChannel channel, MacroAssembler& masm,
 
   AllocatableRegisterSet regs(RegisterSet::All());
   LiveRegisterSet save(regs.asLiveSet());
-  masm.PushRegsInMask(save);
+  PushRegsInMask(masm, save);
 
   if (taken) {
     regs.take(taken.value());
@@ -156,7 +192,7 @@ static void GenPrint(DebugChannel channel, MacroAssembler& masm,
     passArgAndCall(IsCompilingWasm(), temp);
   }
 
-  masm.PopRegsInMask(save);
+  PopRegsInMask(masm, save);
 }
 
 static void GenPrintf(DebugChannel channel, MacroAssembler& masm,
@@ -510,6 +546,10 @@ static const LiveRegisterSet NonVolatileRegs =
 
 #if defined(JS_CODEGEN_NONE)
 static const unsigned NonVolatileRegsPushSize = 0;
+#elif defined(ENABLE_WASM_SIMD) && defined(JS_CODEGEN_ARM64)
+static const unsigned NonVolatileRegsPushSize =
+    NonVolatileRegs.gprs().size() * sizeof(intptr_t) +
+    FloatRegister::GetPushSizeInBytesForWasmStubs(NonVolatileRegs.fpus());
 #else
 static const unsigned NonVolatileRegsPushSize =
     NonVolatileRegs.gprs().size() * sizeof(intptr_t) +
@@ -703,7 +743,7 @@ static bool GenerateInterpEntry(MacroAssembler& masm, const FuncExport& fe,
   // Save all caller non-volatile registers before we clobber them here and in
   // the wasm callee (which does not preserve non-volatile registers).
   masm.setFramePushed(0);
-  masm.PushRegsInMask(NonVolatileRegs);
+  PushRegsInMask(masm, NonVolatileRegs);
   MOZ_ASSERT(masm.framePushed() == NonVolatileRegsPushSize);
 
   // Put the 'argv' argument into a non-argument/return/TLS register so that
@@ -821,7 +861,7 @@ static bool GenerateInterpEntry(MacroAssembler& masm, const FuncExport& fe,
   masm.bind(&join);
 
   // Restore clobbered non-volatile registers of the caller.
-  masm.PopRegsInMask(NonVolatileRegs);
+  PopRegsInMask(masm, NonVolatileRegs);
   MOZ_ASSERT(masm.framePushed() == 0);
 
 #if defined(JS_CODEGEN_ARM64)
@@ -909,7 +949,7 @@ static void GenerateBigIntInitialization(MacroAssembler& masm,
   // We need to avoid clobbering other argument registers and the input.
   AllocatableRegisterSet regs(RegisterSet::Volatile());
   LiveRegisterSet save(regs.asLiveSet());
-  masm.PushRegsInMask(save);
+  PushRegsInMask(masm, save);
 
   unsigned frameSize = StackDecrementForCall(
       ABIStackAlignment, masm.framePushed() + bytesPushedByPrologue, 0);
@@ -930,7 +970,7 @@ static void GenerateBigIntInitialization(MacroAssembler& masm,
 
   LiveRegisterSet ignore;
   ignore.add(scratch);
-  masm.PopRegsInMaskIgnore(save, ignore);
+  PopRegsInMaskIgnore(masm, save, ignore);
 
   masm.branchTest32(Assembler::Zero, scratch, scratch, fail);
   masm.initializeBigInt64(Scalar::BigInt64, scratch, input);
@@ -2600,14 +2640,15 @@ static const LiveRegisterSet RegsToPreserve(
 // We assume that traps do not happen while lr is live. This both ensures that
 // the size of RegsToPreserve is a multiple of 2 (preserving WasmStackAlignment)
 // and gives us a register to clobber in the return path.
+//
+// Note there are no SIMD registers in the set; the doubles in the set stand in
+// for SIMD registers, which are pushed as appropriate.  See comments above at
+// PushRegsInMask and lengty comment in Architecture-arm64.h.
 static const LiveRegisterSet RegsToPreserve(
     GeneralRegisterSet(Registers::AllMask &
                        ~((uint32_t(1) << Registers::StackPointer) |
                          (uint32_t(1) << Registers::lr))),
     FloatRegisterSet(FloatRegisters::AllDoubleMask));
-#  ifdef ENABLE_WASM_SIMD
-#    error "high lanes of SIMD registers need to be saved too."
-#  endif
 #elif defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
 // It's correct to use FloatRegisters::AllMask even when SIMD is not enabled;
 // PushRegsInMask strips out the high lanes of the XMM registers in this case,
@@ -2661,7 +2702,7 @@ static bool GenerateTrapExit(MacroAssembler& masm, Label* throwLabel,
   // Push a dummy word to use as return address below.
   WasmPush(masm, ImmWord(TrapExitDummyValue));
   unsigned framePushedBeforePreserve = masm.framePushed();
-  masm.PushRegsInMask(RegsToPreserve);
+  PushRegsInMask(masm, RegsToPreserve);
   unsigned offsetOfReturnWord = masm.framePushed() - framePushedBeforePreserve;
 
   // We know that StackPointer is word-aligned, but not necessarily
@@ -2685,7 +2726,7 @@ static bool GenerateTrapExit(MacroAssembler& masm, Label* throwLabel,
   // use to jump to via ret.
   masm.moveToStackPtr(preAlignStackPointer);
   masm.storePtr(ReturnReg, Address(masm.getStackPointer(), offsetOfReturnWord));
-  masm.PopRegsInMask(RegsToPreserve);
+  PopRegsInMask(masm, RegsToPreserve);
 #ifdef JS_CODEGEN_ARM64
   WasmPop(masm, lr);
   masm.abiret();
@@ -2749,7 +2790,7 @@ static bool GenerateDebugTrapStub(MacroAssembler& masm, Label* throwLabel,
   GenerateExitPrologue(masm, 0, ExitReason::Fixed::DebugTrap, offsets);
 
   // Save all registers used between baseline compiler operations.
-  masm.PushRegsInMask(AllAllocatableRegs);
+  PushRegsInMask(masm, AllAllocatableRegs);
 
   uint32_t framePushed = masm.framePushed();
 
@@ -2783,7 +2824,7 @@ static bool GenerateDebugTrapStub(MacroAssembler& masm, Label* throwLabel,
 #endif
 
   masm.setFramePushed(framePushed);
-  masm.PopRegsInMask(AllAllocatableRegs);
+  PopRegsInMask(masm, AllAllocatableRegs);
 
   GenerateExitEpilogue(masm, 0, ExitReason::Fixed::DebugTrap, offsets);
 

js/src/wasm/WasmTypes.h

@@ -3363,6 +3363,9 @@ class DebugFrame {
   // alignment.
   uint32_t padding_;
 #endif
+#if defined(ENABLE_WASM_SIMD) && defined(JS_CODEGEN_ARM64)
+  uint64_t padding_;
+#endif
 
  private:
   // The Frame goes at the end since the stack grows down.