Bug 1279248 - Part 6: Implement the 64bit variant of BitOp on x86, r=bbouvier

This commit is contained in:
Hannes Verschore 2016-07-29 16:51:41 +02:00
Родитель 5e33b202ad
Коммит 7df878a85a
7 изменённых файлов: 75 добавлений и 37 удалений

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@ -719,6 +719,7 @@ class MacroAssembler : public MacroAssemblerSpecific
inline void orPtr(Register src, Register dest) PER_ARCH;
inline void orPtr(Imm32 imm, Register dest) PER_ARCH;
inline void and64(Register64 src, Register64 dest) DEFINED_ON(x86);
inline void or64(Register64 src, Register64 dest) PER_ARCH;
inline void xor64(Register64 src, Register64 dest) PER_ARCH;
@ -728,6 +729,10 @@ class MacroAssembler : public MacroAssemblerSpecific
inline void xorPtr(Register src, Register dest) PER_ARCH;
inline void xorPtr(Imm32 imm, Register dest) PER_ARCH;
inline void and64(const Operand& src, Register64 dest) DEFINED_ON(x64);
inline void or64(const Operand& src, Register64 dest) DEFINED_ON(x64);
inline void xor64(const Operand& src, Register64 dest) DEFINED_ON(x64);
// ===============================================================
// Arithmetic functions

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@ -262,36 +262,6 @@ CodeGeneratorX64::visitCompareI64AndBranch(LCompareI64AndBranch* lir)
emitBranch(JSOpToCondition(lir->jsop(), isSigned), lir->ifTrue(), lir->ifFalse());
}
void
CodeGeneratorX64::visitBitOpI64(LBitOpI64* lir)
{
Register lhs = ToRegister(lir->getOperand(0));
const LAllocation* rhs = lir->getOperand(1);
switch (lir->bitop()) {
case JSOP_BITOR:
if (rhs->isConstant())
masm.or64(Imm64(ToInt64(rhs)), Register64(lhs));
else
masm.orq(ToOperand(rhs), lhs);
break;
case JSOP_BITXOR:
if (rhs->isConstant())
masm.xor64(Imm64(ToInt64(rhs)), Register64(lhs));
else
masm.xorq(ToOperand(rhs), lhs);
break;
case JSOP_BITAND:
if (rhs->isConstant())
masm.and64(Imm64(ToInt64(rhs)), Register64(lhs));
else
masm.andq(ToOperand(rhs), lhs);
break;
default:
MOZ_CRASH("unexpected binary opcode");
}
}
void
CodeGeneratorX64::visitRotate64(LRotate64* lir)
{

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@ -52,7 +52,6 @@ class CodeGeneratorX64 : public CodeGeneratorX86Shared
void visitCompareBitwiseAndBranch(LCompareBitwiseAndBranch* lir);
void visitCompareI64(LCompareI64* lir);
void visitCompareI64AndBranch(LCompareI64AndBranch* lir);
void visitBitOpI64(LBitOpI64* lir);
void visitRotate64(LRotate64* lir);
void visitAddI64(LAddI64* lir);
void visitSubI64(LSubI64* lir);

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@ -113,6 +113,24 @@ MacroAssembler::xorPtr(Imm32 imm, Register dest)
xorq(imm, dest);
}
void
MacroAssembler::and64(const Operand& src, Register64 dest)
{
andq(src, dest.reg);
}
void
MacroAssembler::or64(const Operand& src, Register64 dest)
{
orq(src, dest.reg);
}
void
MacroAssembler::xor64(const Operand& src, Register64 dest)
{
xorq(src, dest.reg);
}
// ===============================================================
// Arithmetic functions

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@ -1666,6 +1666,38 @@ CodeGeneratorX86Shared::visitBitOpI(LBitOpI* ins)
}
}
void
CodeGeneratorX86Shared::visitBitOpI64(LBitOpI64* lir)
{
const LInt64Allocation lhs = lir->getInt64Operand(LBitOpI64::Lhs);
const LInt64Allocation rhs = lir->getInt64Operand(LBitOpI64::Rhs);
MOZ_ASSERT(ToOutRegister64(lir) == ToRegister64(lhs));
switch (lir->bitop()) {
case JSOP_BITOR:
if (IsConstant(rhs))
masm.or64(Imm64(ToInt64(rhs)), ToRegister64(lhs));
else
masm.or64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
break;
case JSOP_BITXOR:
if (IsConstant(rhs))
masm.xor64(Imm64(ToInt64(rhs)), ToRegister64(lhs));
else
masm.xor64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
break;
case JSOP_BITAND:
if (IsConstant(rhs))
masm.and64(Imm64(ToInt64(rhs)), ToRegister64(lhs));
else
masm.and64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
break;
default:
MOZ_CRASH("unexpected binary opcode");
}
}
void
CodeGeneratorX86Shared::visitShiftI(LShiftI* ins)
{

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@ -247,6 +247,7 @@ class CodeGeneratorX86Shared : public CodeGeneratorShared
virtual void visitModPowTwoI(LModPowTwoI* ins);
virtual void visitBitNotI(LBitNotI* ins);
virtual void visitBitOpI(LBitOpI* ins);
virtual void visitBitOpI64(LBitOpI64* ins);
virtual void visitShiftI(LShiftI* ins);
virtual void visitShiftI64(LShiftI64* ins);
virtual void visitUrshD(LUrshD* ins);

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@ -48,22 +48,28 @@ MacroAssembler::andPtr(Imm32 imm, Register dest)
void
MacroAssembler::and64(Imm64 imm, Register64 dest)
{
andl(Imm32(imm.value & 0xFFFFFFFFL), dest.low);
andl(Imm32((imm.value >> 32) & 0xFFFFFFFFL), dest.high);
if (imm.low().value != int32_t(0xFFFFFFFF))
andl(imm.low(), dest.low);
if (imm.hi().value != int32_t(0xFFFFFFFF))
andl(imm.hi(), dest.high);
}
void
MacroAssembler::or64(Imm64 imm, Register64 dest)
{
orl(Imm32(imm.value & 0xFFFFFFFFL), dest.low);
orl(Imm32((imm.value >> 32) & 0xFFFFFFFFL), dest.high);
if (imm.low().value != 0)
orl(imm.low(), dest.low);
if (imm.hi().value != 0)
orl(imm.hi(), dest.high);
}
void
MacroAssembler::xor64(Imm64 imm, Register64 dest)
{
xorl(Imm32(imm.value & 0xFFFFFFFFL), dest.low);
xorl(Imm32((imm.value >> 32) & 0xFFFFFFFFL), dest.high);
if (imm.low().value != 0)
xorl(imm.low(), dest.low);
if (imm.hi().value != 0)
xorl(imm.hi(), dest.high);
}
void
@ -78,6 +84,13 @@ MacroAssembler::orPtr(Imm32 imm, Register dest)
orl(imm, dest);
}
void
MacroAssembler::and64(Register64 src, Register64 dest)
{
andl(src.low, dest.low);
andl(src.high, dest.high);
}
void
MacroAssembler::or64(Register64 src, Register64 dest)
{