зеркало из https://github.com/mozilla/gecko-dev.git
Bug 1279248 - Part 6: Implement the 64bit variant of BitOp on x86, r=bbouvier
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Коммит
7df878a85a
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@ -719,6 +719,7 @@ class MacroAssembler : public MacroAssemblerSpecific
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inline void orPtr(Register src, Register dest) PER_ARCH;
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inline void orPtr(Imm32 imm, Register dest) PER_ARCH;
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inline void and64(Register64 src, Register64 dest) DEFINED_ON(x86);
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inline void or64(Register64 src, Register64 dest) PER_ARCH;
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inline void xor64(Register64 src, Register64 dest) PER_ARCH;
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@ -728,6 +729,10 @@ class MacroAssembler : public MacroAssemblerSpecific
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inline void xorPtr(Register src, Register dest) PER_ARCH;
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inline void xorPtr(Imm32 imm, Register dest) PER_ARCH;
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inline void and64(const Operand& src, Register64 dest) DEFINED_ON(x64);
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inline void or64(const Operand& src, Register64 dest) DEFINED_ON(x64);
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inline void xor64(const Operand& src, Register64 dest) DEFINED_ON(x64);
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// ===============================================================
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// Arithmetic functions
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@ -262,36 +262,6 @@ CodeGeneratorX64::visitCompareI64AndBranch(LCompareI64AndBranch* lir)
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emitBranch(JSOpToCondition(lir->jsop(), isSigned), lir->ifTrue(), lir->ifFalse());
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}
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void
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CodeGeneratorX64::visitBitOpI64(LBitOpI64* lir)
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{
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Register lhs = ToRegister(lir->getOperand(0));
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const LAllocation* rhs = lir->getOperand(1);
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switch (lir->bitop()) {
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case JSOP_BITOR:
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if (rhs->isConstant())
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masm.or64(Imm64(ToInt64(rhs)), Register64(lhs));
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else
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masm.orq(ToOperand(rhs), lhs);
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break;
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case JSOP_BITXOR:
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if (rhs->isConstant())
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masm.xor64(Imm64(ToInt64(rhs)), Register64(lhs));
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else
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masm.xorq(ToOperand(rhs), lhs);
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break;
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case JSOP_BITAND:
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if (rhs->isConstant())
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masm.and64(Imm64(ToInt64(rhs)), Register64(lhs));
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else
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masm.andq(ToOperand(rhs), lhs);
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break;
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default:
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MOZ_CRASH("unexpected binary opcode");
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}
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}
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void
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CodeGeneratorX64::visitRotate64(LRotate64* lir)
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{
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@ -52,7 +52,6 @@ class CodeGeneratorX64 : public CodeGeneratorX86Shared
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void visitCompareBitwiseAndBranch(LCompareBitwiseAndBranch* lir);
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void visitCompareI64(LCompareI64* lir);
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void visitCompareI64AndBranch(LCompareI64AndBranch* lir);
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void visitBitOpI64(LBitOpI64* lir);
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void visitRotate64(LRotate64* lir);
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void visitAddI64(LAddI64* lir);
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void visitSubI64(LSubI64* lir);
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@ -113,6 +113,24 @@ MacroAssembler::xorPtr(Imm32 imm, Register dest)
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xorq(imm, dest);
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}
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void
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MacroAssembler::and64(const Operand& src, Register64 dest)
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{
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andq(src, dest.reg);
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}
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void
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MacroAssembler::or64(const Operand& src, Register64 dest)
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{
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orq(src, dest.reg);
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}
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void
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MacroAssembler::xor64(const Operand& src, Register64 dest)
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{
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xorq(src, dest.reg);
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}
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// ===============================================================
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// Arithmetic functions
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@ -1666,6 +1666,38 @@ CodeGeneratorX86Shared::visitBitOpI(LBitOpI* ins)
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}
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}
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void
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CodeGeneratorX86Shared::visitBitOpI64(LBitOpI64* lir)
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{
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const LInt64Allocation lhs = lir->getInt64Operand(LBitOpI64::Lhs);
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const LInt64Allocation rhs = lir->getInt64Operand(LBitOpI64::Rhs);
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MOZ_ASSERT(ToOutRegister64(lir) == ToRegister64(lhs));
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switch (lir->bitop()) {
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case JSOP_BITOR:
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if (IsConstant(rhs))
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masm.or64(Imm64(ToInt64(rhs)), ToRegister64(lhs));
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else
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masm.or64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
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break;
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case JSOP_BITXOR:
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if (IsConstant(rhs))
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masm.xor64(Imm64(ToInt64(rhs)), ToRegister64(lhs));
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else
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masm.xor64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
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break;
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case JSOP_BITAND:
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if (IsConstant(rhs))
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masm.and64(Imm64(ToInt64(rhs)), ToRegister64(lhs));
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else
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masm.and64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
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break;
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default:
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MOZ_CRASH("unexpected binary opcode");
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}
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}
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void
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CodeGeneratorX86Shared::visitShiftI(LShiftI* ins)
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{
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@ -247,6 +247,7 @@ class CodeGeneratorX86Shared : public CodeGeneratorShared
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virtual void visitModPowTwoI(LModPowTwoI* ins);
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virtual void visitBitNotI(LBitNotI* ins);
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virtual void visitBitOpI(LBitOpI* ins);
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virtual void visitBitOpI64(LBitOpI64* ins);
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virtual void visitShiftI(LShiftI* ins);
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virtual void visitShiftI64(LShiftI64* ins);
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virtual void visitUrshD(LUrshD* ins);
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@ -48,22 +48,28 @@ MacroAssembler::andPtr(Imm32 imm, Register dest)
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void
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MacroAssembler::and64(Imm64 imm, Register64 dest)
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{
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andl(Imm32(imm.value & 0xFFFFFFFFL), dest.low);
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andl(Imm32((imm.value >> 32) & 0xFFFFFFFFL), dest.high);
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if (imm.low().value != int32_t(0xFFFFFFFF))
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andl(imm.low(), dest.low);
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if (imm.hi().value != int32_t(0xFFFFFFFF))
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andl(imm.hi(), dest.high);
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}
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void
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MacroAssembler::or64(Imm64 imm, Register64 dest)
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{
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orl(Imm32(imm.value & 0xFFFFFFFFL), dest.low);
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orl(Imm32((imm.value >> 32) & 0xFFFFFFFFL), dest.high);
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if (imm.low().value != 0)
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orl(imm.low(), dest.low);
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if (imm.hi().value != 0)
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orl(imm.hi(), dest.high);
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}
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void
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MacroAssembler::xor64(Imm64 imm, Register64 dest)
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{
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xorl(Imm32(imm.value & 0xFFFFFFFFL), dest.low);
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xorl(Imm32((imm.value >> 32) & 0xFFFFFFFFL), dest.high);
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if (imm.low().value != 0)
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xorl(imm.low(), dest.low);
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if (imm.hi().value != 0)
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xorl(imm.hi(), dest.high);
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}
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void
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@ -78,6 +84,13 @@ MacroAssembler::orPtr(Imm32 imm, Register dest)
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orl(imm, dest);
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}
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void
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MacroAssembler::and64(Register64 src, Register64 dest)
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{
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andl(src.low, dest.low);
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andl(src.high, dest.high);
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}
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void
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MacroAssembler::or64(Register64 src, Register64 dest)
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{
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