зеркало из https://github.com/mozilla/gecko-dev.git
Bug 816015 - Make ARM's second scratch register configurable. r=mjrosenb
This commit is contained in:
Jan de Mooij
Родитель
3204a15335
Коммит
8a07f51037
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@ -753,13 +753,13 @@ MacroAssemblerARM::ma_mod_mask(Register src, Register dest, Register hold, int32
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bind(&head);
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// Extract the bottom bits into lr.
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ma_and(Imm32(mask), ScratchRegister, lr);
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ma_and(Imm32(mask), ScratchRegister, secondScratchReg_);
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// Add those bits to the accumulator.
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ma_add(lr, dest, dest);
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ma_add(secondScratchReg_, dest, dest);
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// Do a trial subtraction, this is the same operation as cmp, but we store the dest
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ma_sub(dest, Imm32(mask), lr, SetCond);
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ma_sub(dest, Imm32(mask), secondScratchReg_, SetCond);
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// If (sum - C) > 0, store sum - C back into sum, thus performing a modulus.
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ma_mov(lr, dest, NoSetCond, Unsigned);
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ma_mov(secondScratchReg_, dest, NoSetCond, Unsigned);
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// Get rid of the bits that we extracted before, and set the condition codes
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as_mov(ScratchRegister, lsr(ScratchRegister, shift), SetCond);
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// If the shift produced zero, finish, otherwise, continue in the loop.
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@ -1707,8 +1707,8 @@ MacroAssemblerARMCompat::loadFloatAsDouble(const BaseIndex &src, const FloatRegi
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void
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MacroAssemblerARMCompat::store8(const Imm32 &imm, const Address &address)
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{
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ma_mov(imm, lr);
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store8(lr, address);
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ma_mov(imm, secondScratchReg_);
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store8(secondScratchReg_, address);
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}
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void
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@ -1720,8 +1720,8 @@ MacroAssemblerARMCompat::store8(const Register &src, const Address &address)
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void
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MacroAssemblerARMCompat::store8(const Imm32 &imm, const BaseIndex &dest)
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{
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ma_mov(imm, lr);
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store8(lr, dest);
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ma_mov(imm, secondScratchReg_);
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store8(secondScratchReg_, dest);
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}
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void
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@ -1740,8 +1740,8 @@ MacroAssemblerARMCompat::store8(const Register &src, const BaseIndex &dest)
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void
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MacroAssemblerARMCompat::store16(const Imm32 &imm, const Address &address)
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{
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ma_mov(imm, lr);
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store16(lr, address);
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ma_mov(imm, secondScratchReg_);
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store16(secondScratchReg_, address);
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}
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void
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@ -1753,8 +1753,8 @@ MacroAssemblerARMCompat::store16(const Register &src, const Address &address)
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void
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MacroAssemblerARMCompat::store16(const Imm32 &imm, const BaseIndex &dest)
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{
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ma_mov(imm, lr);
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store16(lr, dest);
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ma_mov(imm, secondScratchReg_);
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store16(secondScratchReg_, dest);
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}
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void
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MacroAssemblerARMCompat::store16(const Register &src, const BaseIndex &address)
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@ -1795,8 +1795,8 @@ MacroAssemblerARMCompat::store32(const Imm32 &src, const Address &address)
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void
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MacroAssemblerARMCompat::store32(const Imm32 &imm, const BaseIndex &dest)
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{
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ma_mov(imm, lr);
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store32(lr, dest);
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ma_mov(imm, secondScratchReg_);
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store32(secondScratchReg_, dest);
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}
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void
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@ -1894,8 +1894,8 @@ MacroAssemblerARMCompat::cmpPtr(const Address &lhs, const Register &rhs)
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void
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MacroAssemblerARMCompat::cmpPtr(const Address &lhs, const ImmWord &rhs)
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{
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loadPtr(lhs, lr);
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ma_cmp(lr, Imm32(rhs.value));
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loadPtr(lhs, secondScratchReg_);
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ma_cmp(secondScratchReg_, Imm32(rhs.value));
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}
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void
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@ -2499,10 +2499,10 @@ MacroAssemblerARMCompat::storePayload(const Value &val, Operand dest)
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{
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jsval_layout jv = JSVAL_TO_IMPL(val);
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if (val.isMarkable())
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ma_mov(ImmGCPtr((gc::Cell *)jv.s.payload.ptr), lr);
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ma_mov(ImmGCPtr((gc::Cell *)jv.s.payload.ptr), secondScratchReg_);
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else
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ma_mov(Imm32(jv.s.payload.i32), lr);
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ma_str(lr, ToPayload(dest));
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ma_mov(Imm32(jv.s.payload.i32), secondScratchReg_);
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ma_str(secondScratchReg_, ToPayload(dest));
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}
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void
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MacroAssemblerARMCompat::storePayload(Register src, Operand dest)
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@ -2543,8 +2543,8 @@ MacroAssemblerARMCompat::storePayload(Register src, Register base, Register inde
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void
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MacroAssemblerARMCompat::storeTypeTag(ImmTag tag, Operand dest) {
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if (dest.getTag() == Operand::MEM) {
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ma_mov(tag, lr);
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ma_str(lr, ToType(dest));
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ma_mov(tag, secondScratchReg_);
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ma_str(secondScratchReg_, ToType(dest));
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return;
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}
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@ -26,10 +26,23 @@ JS_STATIC_ASSERT(1 << defaultShift == sizeof(jsval));
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// MacroAssemblerARM is inheriting form Assembler defined in Assembler-arm.{h,cpp}
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class MacroAssemblerARM : public Assembler
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{
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protected:
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// On ARM, some instructions require a second scratch register. This register
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// defaults to lr, since it's non-allocatable (as it can be clobbered by some
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// instructions). Allow the baseline compiler to override this though, since
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// baseline IC stubs rely on lr holding the return address.
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Register secondScratchReg_;
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public:
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MacroAssemblerARM()
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: secondScratchReg_(lr)
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{ }
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void setSecondScratchReg(Register reg) {
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JS_ASSERT(reg != ScratchRegister);
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secondScratchReg_ = reg;
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}
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void convertInt32ToDouble(const Register &src, const FloatRegister &dest);
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void convertUInt32ToDouble(const Register &src, const FloatRegister &dest);
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void convertDoubleToFloat(const FloatRegister &src, const FloatRegister &dest);
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@ -460,9 +473,10 @@ class MacroAssemblerARMCompat : public MacroAssemblerARM
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}
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void pushWithPadding(const Imm32 &imm, const Imm32 extraSpace) {
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Imm32 totSpace = Imm32(extraSpace.value + 4);
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// need to use lr, since ma_dtr may need the scratch register to adjust the stack.
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ma_mov(imm, lr);
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ma_dtr(IsStore, sp, totSpace, lr, PreIndex);
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// ma_dtr may need the scratch register to adjust the stack, so use the
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// second scratch register.
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ma_mov(imm, secondScratchReg_);
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ma_dtr(IsStore, sp, totSpace, secondScratchReg_, PreIndex);
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}
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void pop(const Register ®) {
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@ -708,34 +722,23 @@ class MacroAssemblerARMCompat : public MacroAssemblerARM
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}
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template <typename T>
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CodeOffsetJump branchPtrWithPatch(Condition cond, Address addr, T ptr, RepatchLabel *label) {
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// if (compare(*addr, ptr) == cond) goto label
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// with only one temp reg, this is downright PAINFUL.
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// HAXHAXHAXHAXHAX I've reserved lr for private use until I figure out how
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// to teach the register allocator that it is more volatile than most.
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// In the end, this will require us to take an extra temp register and pass it in
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// (or spend 4 instructions making the comparison :()
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// since I wish to get this tested, I'm using a register that should not be used.
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// when everything breaks, this is probably the cause
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// See also branchPtr.
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ma_ldr(addr, lr);
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ma_cmp(lr, ptr);
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ma_ldr(addr, secondScratchReg_);
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ma_cmp(secondScratchReg_, ptr);
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return jumpWithPatch(label, cond);
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}
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void branchPtr(Condition cond, Address addr, ImmGCPtr ptr, Label *label) {
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// See the comment in branchPtrWithPatch.
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ma_ldr(addr, lr);
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ma_cmp(lr, ptr);
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ma_ldr(addr, secondScratchReg_);
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ma_cmp(secondScratchReg_, ptr);
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ma_b(label, cond);
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}
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void branchPtr(Condition cond, Address addr, ImmWord ptr, Label *label) {
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// See the comment in branchPtrWithPatch.
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ma_ldr(addr, lr);
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ma_cmp(lr, ptr);
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ma_ldr(addr, secondScratchReg_);
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ma_cmp(secondScratchReg_, ptr);
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ma_b(label, cond);
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}
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void branchPtr(Condition cond, const AbsoluteAddress &addr, const Register &ptr, Label *label) {
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loadPtr(addr, lr); // ma_cmp will use the scratch register.
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ma_cmp(lr, ptr);
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loadPtr(addr, secondScratchReg_); // ma_cmp will use the scratch register.
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ma_cmp(secondScratchReg_, ptr);
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ma_b(label, cond);
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}
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@ -761,8 +764,8 @@ class MacroAssemblerARMCompat : public MacroAssemblerARM
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storeValue(val, Operand(dest));
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}
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void storeValue(JSValueType type, Register reg, Address dest) {
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ma_mov(ImmTag(JSVAL_TYPE_TO_TAG(type)), lr);
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ma_str(lr, Address(dest.base, dest.offset + 4));
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ma_mov(ImmTag(JSVAL_TYPE_TO_TAG(type)), secondScratchReg_);
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ma_str(secondScratchReg_, Address(dest.base, dest.offset + 4));
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ma_str(reg, dest);
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}
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void storeValue(JSValueType type, Register reg, BaseIndex dest) {
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@ -778,13 +781,13 @@ class MacroAssemblerARMCompat : public MacroAssemblerARM
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}
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void storeValue(const Value &val, Address dest) {
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jsval_layout jv = JSVAL_TO_IMPL(val);
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ma_mov(Imm32(jv.s.tag), lr);
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ma_str(lr, Address(dest.base, dest.offset + 4));
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ma_mov(Imm32(jv.s.tag), secondScratchReg_);
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ma_str(secondScratchReg_, Address(dest.base, dest.offset + 4));
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if (val.isMarkable())
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ma_mov(ImmGCPtr(reinterpret_cast<gc::Cell *>(val.toGCThing())), lr);
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ma_mov(ImmGCPtr(reinterpret_cast<gc::Cell *>(val.toGCThing())), secondScratchReg_);
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else
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ma_mov(Imm32(jv.s.payload.i32), lr);
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ma_str(lr, dest);
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ma_mov(Imm32(jv.s.payload.i32), secondScratchReg_);
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ma_str(secondScratchReg_, dest);
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}
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void storeValue(const Value &val, BaseIndex dest) {
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// Harder cases not handled yet.
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