diff --git a/js/src/jit/MacroAssembler.h b/js/src/jit/MacroAssembler.h
index 72770fe55da0..fff89c6dcca6 100644
--- a/js/src/jit/MacroAssembler.h
+++ b/js/src/jit/MacroAssembler.h
@@ -930,7 +930,7 @@ class MacroAssembler : public MacroAssemblerSpecific
 
     // temp may be invalid only if the chip has the POPCNT instruction.
     inline void popcnt64(Register64 src, Register64 dest, Register temp)
-        DEFINED_ON(x86, x64, arm, mips64);
+        DEFINED_ON(x86, x64, arm, mips32, mips64);
 
     // ===============================================================
     // Branch functions
diff --git a/js/src/jit/mips32/MacroAssembler-mips32-inl.h b/js/src/jit/mips32/MacroAssembler-mips32-inl.h
index 4c39903ef389..4d1633502da6 100644
--- a/js/src/jit/mips32/MacroAssembler-mips32-inl.h
+++ b/js/src/jit/mips32/MacroAssembler-mips32-inl.h
@@ -663,6 +663,29 @@ MacroAssembler::rotateRight64(Register shift, Register64 src, Register64 dest, R
     bind(&done);
 }
 
+// ===============================================================
+// Bit counting functions
+
+void
+MacroAssembler::popcnt64(Register64 src, Register64 dest, Register tmp)
+{
+    MOZ_ASSERT(dest.low != tmp);
+    MOZ_ASSERT(dest.high != tmp);
+    MOZ_ASSERT(dest.low != dest.high);
+
+    if (dest.low != src.high) {
+        popcnt32(src.low, dest.low, tmp);
+        popcnt32(src.high, dest.high, tmp);
+    } else {
+        MOZ_ASSERT(dest.high != src.high);
+        popcnt32(src.low, dest.high, tmp);
+        popcnt32(src.high, dest.low, tmp);
+    }
+
+    ma_addu(dest.low, dest.high);
+    move32(Imm32(0), dest.high);
+}
+
 // ===============================================================
 // Branch functions