зеркало из https://github.com/mozilla/gecko-dev.git
Bug 568486 - SH4 (a.k.a ST40) target support for NanoJIT (r+nnethercote,edwsmith,rreitmai) [Cedrick Vincent]
--HG-- extra : convert_revision : 00cee92849b45f9ab8a908446ce62cd2480d036b
This commit is contained in:
Rick Reitmaier
Родитель
f934ae18a2
Коммит
967c2e2c46
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@ -1057,7 +1057,7 @@ namespace nanojit
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if (target->isop(LIR_jtbl)) {
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// Need to patch up a whole jump table, 'where' is the table.
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LIns *jtbl = target;
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NIns** native_table = (NIns**) where;
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NIns** native_table = (NIns**) (void *) where;
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for (uint32_t i = 0, n = jtbl->getTableSize(); i < n; i++) {
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LabelState* lstate = _labels.get(jtbl->getTarget(i));
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NIns* ntarget = lstate->addr;
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@ -312,6 +312,13 @@ extern "C" void sync_instruction_memory(caddr_t v, u_int len);
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sync_instruction_memory((char*)start, len);
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}
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#elif defined NANOJIT_SH4
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#include <asm/cachectl.h> /* CACHEFLUSH_*, */
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#include <sys/syscall.h> /* __NR_cacheflush, */
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void CodeAlloc::flushICache(void *start, size_t len) {
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syscall(__NR_cacheflush, start, len, CACHEFLUSH_D_WB | CACHEFLUSH_I);
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}
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#elif defined(AVMPLUS_UNIX) && defined(NANOJIT_MIPS)
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void CodeAlloc::flushICache(void *start, size_t len) {
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// FIXME Use synci on MIPS32R2
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@ -418,7 +425,7 @@ extern "C" void sync_instruction_memory(caddr_t v, u_int len);
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} else {
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// there's enough space left to split into three blocks (two new ones)
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CodeList* b1 = getBlock(start, end);
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CodeList* b2 = (CodeList*) holeStart;
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CodeList* b2 = (CodeList*) (void*) holeStart;
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CodeList* b3 = (CodeList*) (uintptr_t(holeEnd) - offsetof(CodeList, code));
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b1->higher = b2;
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b2->lower = b1;
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@ -64,6 +64,8 @@
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#include "NativeSparc.h"
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#elif defined(NANOJIT_X64)
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#include "NativeX64.h"
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#elif defined(NANOJIT_SH4)
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#include "NativeSH4.h"
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#elif defined(NANOJIT_MIPS)
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#include "NativeMIPS.h"
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#else
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -0,0 +1,455 @@
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/* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: nil; tab-width: 4 -*-
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*
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* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1/GPL 2.0/LGPL 2.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is [Open Source Virtual Machine].
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*
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* The Initial Developer of the Original Code is
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* STMicroelectronics.
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* Portions created by the Initial Developer are Copyright (C) 2010
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Cédric VINCENT <cedric.vincent@st.com> for STMicroelectronics
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*
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* Alternatively, the contents of this file may be used under the terms of
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* either the GNU General Public License Version 2 or later (the "GPL"), or
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* the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
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* in which case the provisions of the GPL or the LGPL are applicable instead
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* of those above. If you wish to allow use of your version of this file only
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* under the terms of either the GPL or the LGPL, and not to allow others to
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* use your version of this file under the terms of the MPL, indicate your
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* decision by deleting the provisions above and replace them with the notice
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* and other provisions required by the GPL or the LGPL. If you do not delete
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* the provisions above, a recipient may use your version of this file under
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* the terms of any one of the MPL, the GPL or the LGPL.
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*
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* ***** END LICENSE BLOCK ***** */
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#ifndef __nanojit_NativeSH4__
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#define __nanojit_NativeSH4__
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namespace nanojit
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{
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/***********************************************************************
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* Definitions for the register allocation.
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*/
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// General purpose and ABI registers.
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enum Register {
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// Scratch registers (a.k.a caller-saved, a.k.a local).
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R0 = 0,
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R1,
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R2,
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R3, // Excluded from the regalloc because of its use as a hyper-scratch.
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R4,
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R5,
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R6,
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R7,
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// Saved registers (a.k.a callee-saved, a.k.a global).
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R8,
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R9,
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R10,
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R11,
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R12,
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R13,
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// ABI registers, excluded from the register allocation.
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FP,
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SP,
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// Floatting-point registers.
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_D0,
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_F0 = _D0,
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_F1,
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_D1,
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_F2 = _D1,
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_F3,
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_D2,
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_F4 = _D2,
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_F5,
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_D3,
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_F6 = _D3,
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_F7,
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_D4,
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_F8 = _D4,
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_F9,
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_D5,
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_F10 = _D5,
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_F11,
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_D6,
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_F12 = _D6,
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_F13,
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_D7,
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_F14 = _D7, // Excluded from the regalloc because of its use as a hyper-scratch.
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_F15,
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// Helpers.
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FirstReg = R0,
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LastReg = _D7,
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deprecated_UnknownReg = LastReg + 2,
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UnspecifiedReg = LastReg + 2,
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Rtemp = R3,
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Dtemp = _D7
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};
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// There's 16 integer registers + 8 double registers on SH4.
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typedef uint32_t RegisterMask;
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static const int NumSavedRegs = 6;
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static const RegisterMask SavedRegs = ((1<<R8) | (1<<R9) | (1<<R10) | (1<<R11) | (1<<R12) | (1<<R13));
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static const RegisterMask ScratchRegs = ((1<<R0) | (1<<R1) | (1<<R2) | (1<<R4) | (1<<R5) | (1<<R6) | (1<<R7));
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static const RegisterMask GpRegs = ScratchRegs | SavedRegs;
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static const RegisterMask FpRegs = ((1<<_D0) | (1<<_D1) | (1<<_D2) | (1<<_D3) | (1<<_D4) | (1<<_D5) | (1<<_D6));
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#define IsFpReg(reg) ((rmask((Register)(reg)) & (FpRegs | (1<<_D7))) != 0)
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#define IsGpReg(reg) ((rmask((Register)(reg)) & (GpRegs)) != 0)
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/***********************************************************************
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* Definitions for the code generation.
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*/
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// Fixed instruction width of 16 bits.
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typedef uint16_t NIns;
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// Minimum size in bytes of an allocation for a code-buffer.
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const int32_t LARGEST_UNDERRUN_PROT = 32 * sizeof(NIns);
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// Maximum size in bytes of a patch for a branch, keep in sync' with nPatchBranch().
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const size_t LARGEST_BRANCH_PATCH = 3 * sizeof(NIns) + sizeof(uint32_t);
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// Maximum size in bytes of a stack entry.
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#define NJ_MAX_STACK_ENTRY 4096
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// Minimum alignement for the stack pointer.
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#define NJ_ALIGN_STACK 8
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// Support the extended load/store opcodes.
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#define NJ_EXPANDED_LOADSTORE_SUPPORTED 1
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// Maximum size in bytes of a FP64 load, keep in sync' with asm_immd_nochk().
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#define SH4_IMMD_NOCHK_SIZE (9 * sizeof(NIns) + 2 * sizeof(uint32_t))
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/***********************************************************************
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* Extensions specific to this platform.
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*/
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verbose_only( extern const char* regNames[]; )
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// Extensions for the instruction assembler.
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#define DECLARE_PLATFORM_ASSEMBLER() \
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const static int NumArgRegs; \
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const static int NumArgDregs; \
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const static Register argRegs[4], retRegs[2]; \
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const static Register argDregs[4], retDregs[1]; \
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int max_stack_args; \
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\
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void nativePageReset(); \
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void nativePageSetup(); \
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void underrunProtect(int); \
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bool simplifyOpcode(LOpcode &); \
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\
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NIns *asm_immi(int, Register, bool force = false); \
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void asm_immd(uint64_t, Register); \
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void asm_immd_nochk(uint64_t, Register); \
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void asm_arg_regi(LIns*, Register); \
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void asm_arg_regd(LIns*, Register); \
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void asm_arg_stacki(LIns*, int); \
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void asm_arg_stackd(LIns*, int); \
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void asm_base_offset(int, Register); \
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void asm_load32i(int, Register, Register); \
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void asm_load16i(int, Register, Register, bool); \
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void asm_load8i(int, Register, Register, bool); \
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void asm_load64d(int, Register, Register); \
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void asm_load32d(int, Register, Register); \
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void asm_store32i(Register, int, Register); \
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void asm_store16i(Register, int, Register); \
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void asm_store8i(Register, int, Register); \
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void asm_store64d(Register, int, Register); \
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void asm_store32d(Register, int, Register); \
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void asm_cmp(LOpcode, LIns*); \
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NIns *asm_branch(bool, NIns *); \
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\
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void MR(Register, Register); \
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void JMP(NIns*, bool from_underrunProtect = false); \
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\
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void SH4_emit16(uint16_t value); \
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void SH4_emit32(uint32_t value); \
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void SH4_add_imm(int imm, Register Rx); \
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void SH4_add(Register Ry, Register Rx); \
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void SH4_addc(Register Ry, Register Rx); \
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void SH4_addv(Register Ry, Register Rx); \
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void SH4_and_imm_R0(int imm); \
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void SH4_and(Register Ry, Register Rx); \
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void SH4_andb_imm_dispR0GBR(int imm); \
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void SH4_bra(int imm); \
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void SH4_bsr(int imm); \
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void SH4_bt(int imm); \
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void SH4_bf(int imm); \
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void SH4_bts(int imm); \
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void SH4_bfs(int imm); \
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void SH4_clrmac(); \
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void SH4_clrs(); \
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void SH4_clrt(); \
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void SH4_cmpeq_imm_R0(int imm); \
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void SH4_cmpeq(Register Ry, Register Rx); \
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void SH4_cmpge(Register Ry, Register Rx); \
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void SH4_cmpgt(Register Ry, Register Rx); \
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void SH4_cmphi(Register Ry, Register Rx); \
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void SH4_cmphs(Register Ry, Register Rx); \
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void SH4_cmppl(Register Rx); \
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void SH4_cmppz(Register Rx); \
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void SH4_cmpstr(Register Ry, Register Rx); \
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void SH4_div0s(Register Ry, Register Rx); \
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void SH4_div0u(); \
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void SH4_div1(Register Ry, Register Rx); \
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void SH4_extsb(Register Ry, Register Rx); \
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void SH4_extsw(Register Ry, Register Rx); \
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void SH4_extub(Register Ry, Register Rx); \
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void SH4_extuw(Register Ry, Register Rx); \
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void SH4_icbi_indRx(Register Rx); \
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void SH4_jmp_indRx(Register Rx); \
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void SH4_jsr_indRx(Register Rx); \
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void SH4_ldc_SR(Register Rx); \
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void SH4_ldc_GBR(Register Rx); \
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void SH4_ldc_SGR(Register Rx); \
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void SH4_ldc_VBR(Register Rx); \
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void SH4_ldc_SSR(Register Rx); \
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void SH4_ldc_SPC(Register Rx); \
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void SH4_ldc_DBR(Register Rx); \
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void SH4_ldc_bank(Register Rx, int imm); \
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void SH4_ldcl_incRx_SR(Register Rx); \
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void SH4_ldcl_incRx_GBR(Register Rx); \
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void SH4_ldcl_incRx_VBR(Register Rx); \
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void SH4_ldcl_incRx_SGR(Register Rx); \
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void SH4_ldcl_incRx_SSR(Register Rx); \
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void SH4_ldcl_incRx_SPC(Register Rx); \
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void SH4_ldcl_incRx_DBR(Register Rx); \
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void SH4_ldcl_incRx_bank(Register Rx, int imm); \
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void SH4_lds_MACH(Register Rx); \
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void SH4_lds_MACL(Register Rx); \
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void SH4_lds_PR(Register Rx); \
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void SH4_lds_FPUL(Register Ry); \
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void SH4_lds_FPSCR(Register Ry); \
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void SH4_ldsl_incRx_MACH(Register Rx); \
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void SH4_ldsl_incRx_MACL(Register Rx); \
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void SH4_ldsl_incRx_PR(Register Rx); \
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void SH4_ldsl_incRy_FPUL(Register Ry); \
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void SH4_ldsl_incRy_FPSCR(Register Ry); \
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void SH4_ldtlb(); \
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void SH4_macw_incRy_incRx(Register Ry, Register Rx); \
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void SH4_mov_imm(int imm, Register Rx); \
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void SH4_mov(Register Ry, Register Rx); \
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void SH4_movb_dispR0Rx(Register Ry, Register Rx); \
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void SH4_movb_decRx(Register Ry, Register Rx); \
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void SH4_movb_indRx(Register Ry, Register Rx); \
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void SH4_movb_dispRy_R0(int imm, Register Ry); \
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void SH4_movb_dispGBR_R0(int imm); \
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void SH4_movb_dispR0Ry(Register Ry, Register Rx); \
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void SH4_movb_incRy(Register Ry, Register Rx); \
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void SH4_movb_indRy(Register Ry, Register Rx); \
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void SH4_movb_R0_dispRx(int imm, Register Ry); \
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void SH4_movb_R0_dispGBR(int imm); \
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void SH4_movl_dispRx(Register Ry, int imm, Register Rx); \
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void SH4_movl_dispR0Rx(Register Ry, Register Rx); \
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void SH4_movl_decRx(Register Ry, Register Rx); \
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void SH4_movl_indRx(Register Ry, Register Rx); \
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void SH4_movl_dispRy(int imm, Register Ry, Register Rx); \
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void SH4_movl_dispGBR_R0(int imm); \
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void SH4_movl_dispPC(int imm, Register Rx); \
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void SH4_movl_dispR0Ry(Register Ry, Register Rx); \
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void SH4_movl_incRy(Register Ry, Register Rx); \
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void SH4_movl_indRy(Register Ry, Register Rx); \
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void SH4_movl_R0_dispGBR(int imm); \
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void SH4_movw_dispR0Rx(Register Ry, Register Rx); \
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void SH4_movw_decRx(Register Ry, Register Rx); \
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void SH4_movw_indRx(Register Ry, Register Rx); \
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void SH4_movw_dispRy_R0(int imm, Register Ry); \
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void SH4_movw_dispGBR_R0(int imm); \
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void SH4_movw_dispPC(int imm, Register Rx); \
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void SH4_movw_dispR0Ry(Register Ry, Register Rx); \
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void SH4_movw_incRy(Register Ry, Register Rx); \
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void SH4_movw_indRy(Register Ry, Register Rx); \
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void SH4_movw_R0_dispRx(int imm, Register Ry); \
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void SH4_movw_R0_dispGBR(int imm); \
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void SH4_mova_dispPC_R0(int imm); \
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void SH4_movcal_R0_indRx(Register Rx); \
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void SH4_movcol_R0_indRx(Register Rx); \
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void SH4_movlil_indRy_R0(Register Ry); \
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void SH4_movt(Register Rx); \
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void SH4_movual_indRy_R0(Register Ry); \
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void SH4_movual_incRy_R0(Register Ry); \
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void SH4_mulsw(Register Ry, Register Rx); \
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void SH4_muls(Register Ry, Register Rx); \
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void SH4_mull(Register Ry, Register Rx); \
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void SH4_muluw(Register Ry, Register Rx); \
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void SH4_mulu(Register Ry, Register Rx); \
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void SH4_neg(Register Ry, Register Rx); \
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void SH4_negc(Register Ry, Register Rx); \
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void SH4_nop(); \
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void SH4_not(Register Ry, Register Rx); \
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void SH4_ocbi_indRx(Register Rx); \
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void SH4_ocbp_indRx(Register Rx); \
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void SH4_ocbwb_indRx(Register Rx); \
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void SH4_or_imm_R0(int imm); \
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void SH4_or(Register Ry, Register Rx); \
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void SH4_orb_imm_dispR0GBR(int imm); \
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void SH4_pref_indRx(Register Rx); \
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void SH4_prefi_indRx(Register Rx); \
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void SH4_rotcl(Register Rx); \
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void SH4_rotcr(Register Rx); \
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void SH4_rotl(Register Rx); \
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void SH4_rotr(Register Rx); \
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void SH4_rte(); \
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void SH4_rts(); \
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void SH4_sets(); \
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void SH4_sett(); \
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void SH4_shad(Register Ry, Register Rx); \
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void SH4_shld(Register Ry, Register Rx); \
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void SH4_shal(Register Rx); \
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void SH4_shar(Register Rx); \
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void SH4_shll(Register Rx); \
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void SH4_shll16(Register Rx); \
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void SH4_shll2(Register Rx); \
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void SH4_shll8(Register Rx); \
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void SH4_shlr(Register Rx); \
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void SH4_shlr16(Register Rx); \
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void SH4_shlr2(Register Rx); \
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void SH4_shlr8(Register Rx); \
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void SH4_sleep(); \
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void SH4_stc_SR(Register Rx); \
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void SH4_stc_GBR(Register Rx); \
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void SH4_stc_VBR(Register Rx); \
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void SH4_stc_SSR(Register Rx); \
|
||||
void SH4_stc_SPC(Register Rx); \
|
||||
void SH4_stc_SGR(Register Rx); \
|
||||
void SH4_stc_DBR(Register Rx); \
|
||||
void SH4_stc_bank(int imm, Register Rx); \
|
||||
void SH4_stcl_SR_decRx(Register Rx); \
|
||||
void SH4_stcl_VBR_decRx(Register Rx); \
|
||||
void SH4_stcl_SSR_decRx(Register Rx); \
|
||||
void SH4_stcl_SPC_decRx(Register Rx); \
|
||||
void SH4_stcl_GBR_decRx(Register Rx); \
|
||||
void SH4_stcl_SGR_decRx(Register Rx); \
|
||||
void SH4_stcl_DBR_decRx(Register Rx); \
|
||||
void SH4_stcl_bank_decRx(int imm, Register Rx); \
|
||||
void SH4_sts_MACH(Register Rx); \
|
||||
void SH4_sts_MACL(Register Rx); \
|
||||
void SH4_sts_PR(Register Rx); \
|
||||
void SH4_sts_FPUL(Register Rx); \
|
||||
void SH4_sts_FPSCR(Register Rx); \
|
||||
void SH4_stsl_MACH_decRx(Register Rx); \
|
||||
void SH4_stsl_MACL_decRx(Register Rx); \
|
||||
void SH4_stsl_PR_decRx(Register Rx); \
|
||||
void SH4_stsl_FPUL_decRx(Register Rx); \
|
||||
void SH4_stsl_FPSCR_decRx(Register Rx); \
|
||||
void SH4_sub(Register Ry, Register Rx); \
|
||||
void SH4_subc(Register Ry, Register Rx); \
|
||||
void SH4_subv(Register Ry, Register Rx); \
|
||||
void SH4_swapb(Register Ry, Register Rx); \
|
||||
void SH4_swapw(Register Ry, Register Rx); \
|
||||
void SH4_synco(); \
|
||||
void SH4_tasb_indRx(Register Rx); \
|
||||
void SH4_trapa_imm(int imm); \
|
||||
void SH4_tst_imm_R0(int imm); \
|
||||
void SH4_tst(Register Ry, Register Rx); \
|
||||
void SH4_tstb_imm_dispR0GBR(int imm); \
|
||||
void SH4_xor_imm_R0(int imm); \
|
||||
void SH4_xor(Register Ry, Register Rx); \
|
||||
void SH4_xorb_imm_dispR0GBR(int imm); \
|
||||
void SH4_xtrct(Register Ry, Register Rx); \
|
||||
void SH4_dt(Register Rx); \
|
||||
void SH4_dmulsl(Register Ry, Register Rx); \
|
||||
void SH4_dmulul(Register Ry, Register Rx); \
|
||||
void SH4_macl_incRy_incRx(Register Ry, Register Rx); \
|
||||
void SH4_braf(Register Rx); \
|
||||
void SH4_bsrf(Register Rx); \
|
||||
void SH4_fabs(Register Rx); \
|
||||
void SH4_fabs_double(Register Rx); \
|
||||
void SH4_fadd(Register Ry, Register Rx); \
|
||||
void SH4_fadd_double(Register Ry, Register Rx); \
|
||||
void SH4_fcmpeq(Register Ry, Register Rx); \
|
||||
void SH4_fcmpeq_double(Register Ry, Register Rx); \
|
||||
void SH4_fcmpgt(Register Ry, Register Rx); \
|
||||
void SH4_fcmpgt_double(Register Ry, Register Rx); \
|
||||
void SH4_fcnvds_double_FPUL(Register Rx); \
|
||||
void SH4_fcnvsd_FPUL_double(Register Rx); \
|
||||
void SH4_fdiv(Register Ry, Register Rx); \
|
||||
void SH4_fdiv_double(Register Ry, Register Rx); \
|
||||
void SH4_fipr(Register Ry, Register Rx); \
|
||||
void SH4_fldi0(Register Rx); \
|
||||
void SH4_fldi1(Register Rx); \
|
||||
void SH4_flds_FPUL(Register Rx); \
|
||||
void SH4_float_FPUL(Register Rx); \
|
||||
void SH4_float_FPUL_double(Register Rx); \
|
||||
void SH4_fmac(Register Ry, Register Rx); \
|
||||
void SH4_fmov(Register Ry, Register Rx); \
|
||||
void SH4_fmov_Xdouble_Xdouble(Register Ry, Register Rx); \
|
||||
void SH4_fmov_indRy(Register Ry, Register Rx); \
|
||||
void SH4_fmov_indRy_Xdouble(Register Ry, Register Rx); \
|
||||
void SH4_fmov_indRx(Register Ry, Register Rx); \
|
||||
void SH4_fmov_Xdouble_indRx(Register Ry, Register Rx); \
|
||||
void SH4_fmov_incRy(Register Ry, Register Rx); \
|
||||
void SH4_fmov_incRy_Xdouble(Register Ry, Register Rx); \
|
||||
void SH4_fmov_decRx(Register Ry, Register Rx); \
|
||||
void SH4_fmov_Xdouble_decRx(Register Ry, Register Rx); \
|
||||
void SH4_fmov_dispR0Ry(Register Ry, Register Rx); \
|
||||
void SH4_fmov_dispR0Ry_Xdouble(Register Ry, Register Rx); \
|
||||
void SH4_fmov_dispR0Rx(Register Ry, Register Rx); \
|
||||
void SH4_fmov_Xdouble_dispR0Rx(Register Ry, Register Rx); \
|
||||
void SH4_fmovd_indRy_Xdouble(Register Ry, Register Rx); \
|
||||
void SH4_fmovd_Xdouble_indRx(Register Ry, Register Rx); \
|
||||
void SH4_fmovd_incRy_Xdouble(Register Ry, Register Rx); \
|
||||
void SH4_fmovd_Xdouble_decRx(Register Ry, Register Rx); \
|
||||
void SH4_fmovd_dispR0Ry_Xdouble(Register Ry, Register Rx); \
|
||||
void SH4_fmovd_Xdouble_dispR0Rx(Register Ry, Register Rx); \
|
||||
void SH4_fmovs_indRy(Register Ry, Register Rx); \
|
||||
void SH4_fmovs_indRx(Register Ry, Register Rx); \
|
||||
void SH4_fmovs_incRy(Register Ry, Register Rx); \
|
||||
void SH4_fmovs_decRx(Register Ry, Register Rx); \
|
||||
void SH4_fmovs_dispR0Ry(Register Ry, Register Rx); \
|
||||
void SH4_fmovs_dispR0Rx(Register Ry, Register Rx); \
|
||||
void SH4_fmul(Register Ry, Register Rx); \
|
||||
void SH4_fmul_double(Register Ry, Register Rx); \
|
||||
void SH4_fneg(Register Rx); \
|
||||
void SH4_fneg_double(Register Rx); \
|
||||
void SH4_fpchg(); \
|
||||
void SH4_frchg(); \
|
||||
void SH4_fsca_FPUL_double(Register Rx); \
|
||||
void SH4_fschg(); \
|
||||
void SH4_fsqrt(Register Rx); \
|
||||
void SH4_fsqrt_double(Register Rx); \
|
||||
void SH4_fsrra(Register Rx); \
|
||||
void SH4_fsts_FPUL(Register Rx); \
|
||||
void SH4_fsub(Register Ry, Register Rx); \
|
||||
void SH4_fsub_double(Register Ry, Register Rx); \
|
||||
void SH4_ftrc_FPUL(Register Rx); \
|
||||
void SH4_ftrc_double_FPUL(Register Rx); \
|
||||
void SH4_ftrv(Register Rx);
|
||||
|
||||
// Extensions for the register allocation, not [yet] used for the SH4.
|
||||
#define DECLARE_PLATFORM_REGALLOC()
|
||||
|
||||
// Extensions for the statistic computation, not [yet] used for the SH4.
|
||||
#define DECLARE_PLATFORM_STATS()
|
||||
|
||||
// Supports float->int conversion.
|
||||
#define NJ_F2I_SUPPORTED 1
|
||||
|
||||
}
|
||||
|
||||
#endif /* __nanojit_NativeSH4__ */
|
||||
|
|
@ -61,6 +61,10 @@ ifeq (sparc,$(TARGET_CPU))
|
|||
nanojit_cpu_cxxsrc := NativeSparc.cpp
|
||||
endif
|
||||
|
||||
ifeq (sh4,$(TARGET_CPU))
|
||||
nanojit_cpu_cxxsrc := NativeSH4.cpp
|
||||
endif
|
||||
|
||||
ifeq (mips,$(TARGET_CPU))
|
||||
nanojit_cpu_cxxsrc := NativeMIPS.cpp
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -54,6 +54,8 @@
|
|||
#define NANOJIT_SPARC
|
||||
#elif defined AVMPLUS_AMD64
|
||||
#define NANOJIT_X64
|
||||
#elif defined VMCFG_SH4
|
||||
#define NANOJIT_SH4
|
||||
#elif defined AVMPLUS_MIPS
|
||||
#define NANOJIT_MIPS
|
||||
#else
|
||||
|
|
|
|||
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