зеркало из https://github.com/mozilla/gecko-dev.git
Bug 1629791 part 13 - Auto-generate boilerplate for more ops. r=mgaudet
Differential Revision: https://phabricator.services.mozilla.com/D71322
This commit is contained in:
Jan de Mooij
Родитель
9b13ee4cec
Коммит
976500d7ac
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@ -6616,8 +6616,8 @@ AttachDecision BinaryArithIRGenerator::tryAttachBitwise() {
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trackAttached("BinaryArith.Bitwise.BitOr");
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break;
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case JSOp::BitXor:
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writer.int32BitXOrResult(lhsIntId, rhsIntId);
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trackAttached("BinaryArith.Bitwise.BitXOr");
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writer.int32BitXorResult(lhsIntId, rhsIntId);
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trackAttached("BinaryArith.Bitwise.BitXor");
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break;
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case JSOp::BitAnd:
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writer.int32BitAndResult(lhsIntId, rhsIntId);
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@ -1154,26 +1154,6 @@ class MOZ_RAII CacheIRWriter : public JS::CustomAutoRooter {
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writeOperandId(rhsId);
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}
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void int32MulResult(Int32OperandId lhs, Int32OperandId rhs) {
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writeOpWithOperandId(CacheOp::Int32MulResult, lhs);
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writeOperandId(rhs);
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}
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void int32DivResult(Int32OperandId lhs, Int32OperandId rhs) {
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writeOpWithOperandId(CacheOp::Int32DivResult, lhs);
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writeOperandId(rhs);
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}
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void int32ModResult(Int32OperandId lhs, Int32OperandId rhs) {
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writeOpWithOperandId(CacheOp::Int32ModResult, lhs);
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writeOperandId(rhs);
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}
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void int32PowResult(Int32OperandId lhs, Int32OperandId rhs) {
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writeOpWithOperandId(CacheOp::Int32PowResult, lhs);
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writeOperandId(rhs);
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}
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void bigIntAddResult(BigIntOperandId lhsId, BigIntOperandId rhsId) {
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writeOpWithOperandId(CacheOp::BigIntAddResult, lhsId);
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writeOperandId(rhsId);
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@ -1204,42 +1184,6 @@ class MOZ_RAII CacheIRWriter : public JS::CustomAutoRooter {
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writeOperandId(rhsId);
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}
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void int32BitOrResult(Int32OperandId lhs, Int32OperandId rhs) {
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writeOpWithOperandId(CacheOp::Int32BitOrResult, lhs);
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writeOperandId(rhs);
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}
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void int32BitXOrResult(Int32OperandId lhs, Int32OperandId rhs) {
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writeOpWithOperandId(CacheOp::Int32BitXorResult, lhs);
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writeOperandId(rhs);
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}
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void int32BitAndResult(Int32OperandId lhs, Int32OperandId rhs) {
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writeOpWithOperandId(CacheOp::Int32BitAndResult, lhs);
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writeOperandId(rhs);
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}
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void int32LeftShiftResult(Int32OperandId lhs, Int32OperandId rhs) {
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writeOpWithOperandId(CacheOp::Int32LeftShiftResult, lhs);
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writeOperandId(rhs);
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}
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void int32RightShiftResult(Int32OperandId lhs, Int32OperandId rhs) {
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writeOpWithOperandId(CacheOp::Int32RightShiftResult, lhs);
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writeOperandId(rhs);
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}
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void int32URightShiftResult(Int32OperandId lhs, Int32OperandId rhs,
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bool allowDouble) {
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writeOpWithOperandId(CacheOp::Int32URightShiftResult, lhs);
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writeOperandId(rhs);
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buffer_.writeByte(uint32_t(allowDouble));
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}
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void int32NotResult(Int32OperandId id) {
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writeOpWithOperandId(CacheOp::Int32NotResult, id);
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}
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void int32NegationResult(Int32OperandId id) {
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writeOpWithOperandId(CacheOp::Int32NegationResult, id);
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}
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@ -2498,11 +2498,12 @@ bool CacheIRCompiler::emitInt32SubResult(Int32OperandId lhsId,
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return true;
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}
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bool CacheIRCompiler::emitInt32MulResult() {
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bool CacheIRCompiler::emitInt32MulResult(Int32OperandId lhsId,
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Int32OperandId rhsId) {
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JitSpew(JitSpew_Codegen, "%s", __FUNCTION__);
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AutoOutputRegister output(*this);
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Register lhs = allocator.useRegister(masm, reader.int32OperandId());
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Register rhs = allocator.useRegister(masm, reader.int32OperandId());
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Register lhs = allocator.useRegister(masm, lhsId);
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Register rhs = allocator.useRegister(masm, rhsId);
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AutoScratchRegister scratch(allocator, masm);
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AutoScratchRegisterMaybeOutput scratch2(allocator, masm, output);
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@ -2528,11 +2529,12 @@ bool CacheIRCompiler::emitInt32MulResult() {
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return true;
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}
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bool CacheIRCompiler::emitInt32DivResult() {
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bool CacheIRCompiler::emitInt32DivResult(Int32OperandId lhsId,
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Int32OperandId rhsId) {
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JitSpew(JitSpew_Codegen, "%s", __FUNCTION__);
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AutoOutputRegister output(*this);
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Register lhs = allocator.useRegister(masm, reader.int32OperandId());
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Register rhs = allocator.useRegister(masm, reader.int32OperandId());
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Register lhs = allocator.useRegister(masm, lhsId);
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Register rhs = allocator.useRegister(masm, rhsId);
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AutoScratchRegister rem(allocator, masm);
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AutoScratchRegisterMaybeOutput scratch(allocator, masm, output);
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@ -2563,11 +2565,12 @@ bool CacheIRCompiler::emitInt32DivResult() {
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return true;
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}
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bool CacheIRCompiler::emitInt32ModResult() {
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bool CacheIRCompiler::emitInt32ModResult(Int32OperandId lhsId,
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Int32OperandId rhsId) {
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JitSpew(JitSpew_Codegen, "%s", __FUNCTION__);
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AutoOutputRegister output(*this);
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Register lhs = allocator.useRegister(masm, reader.int32OperandId());
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Register rhs = allocator.useRegister(masm, reader.int32OperandId());
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Register lhs = allocator.useRegister(masm, lhsId);
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Register rhs = allocator.useRegister(masm, rhsId);
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AutoScratchRegisterMaybeOutput scratch(allocator, masm, output);
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FailurePath* failure;
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@ -2630,11 +2633,12 @@ class MOZ_RAII AutoScratchRegisterMaybeOutputType {
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operator Register() const { return scratchReg_; }
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};
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bool CacheIRCompiler::emitInt32PowResult() {
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bool CacheIRCompiler::emitInt32PowResult(Int32OperandId lhsId,
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Int32OperandId rhsId) {
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JitSpew(JitSpew_Codegen, "%s", __FUNCTION__);
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AutoOutputRegister output(*this);
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Register base = allocator.useRegister(masm, reader.int32OperandId());
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Register power = allocator.useRegister(masm, reader.int32OperandId());
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Register base = allocator.useRegister(masm, lhsId);
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Register power = allocator.useRegister(masm, rhsId);
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AutoScratchRegisterMaybeOutput scratch1(allocator, masm, output);
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AutoScratchRegisterMaybeOutputType scratch2(allocator, masm, output);
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AutoScratchRegister scratch3(allocator, masm);
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@ -2650,13 +2654,14 @@ bool CacheIRCompiler::emitInt32PowResult() {
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return true;
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}
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bool CacheIRCompiler::emitInt32BitOrResult() {
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bool CacheIRCompiler::emitInt32BitOrResult(Int32OperandId lhsId,
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Int32OperandId rhsId) {
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JitSpew(JitSpew_Codegen, "%s", __FUNCTION__);
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AutoOutputRegister output(*this);
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AutoScratchRegisterMaybeOutput scratch(allocator, masm, output);
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Register lhs = allocator.useRegister(masm, reader.int32OperandId());
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Register rhs = allocator.useRegister(masm, reader.int32OperandId());
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Register lhs = allocator.useRegister(masm, lhsId);
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Register rhs = allocator.useRegister(masm, rhsId);
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masm.mov(rhs, scratch);
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masm.or32(lhs, scratch);
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@ -2664,13 +2669,14 @@ bool CacheIRCompiler::emitInt32BitOrResult() {
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return true;
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}
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bool CacheIRCompiler::emitInt32BitXorResult() {
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bool CacheIRCompiler::emitInt32BitXorResult(Int32OperandId lhsId,
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Int32OperandId rhsId) {
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JitSpew(JitSpew_Codegen, "%s", __FUNCTION__);
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AutoOutputRegister output(*this);
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AutoScratchRegisterMaybeOutput scratch(allocator, masm, output);
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Register lhs = allocator.useRegister(masm, reader.int32OperandId());
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Register rhs = allocator.useRegister(masm, reader.int32OperandId());
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Register lhs = allocator.useRegister(masm, lhsId);
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Register rhs = allocator.useRegister(masm, rhsId);
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masm.mov(rhs, scratch);
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masm.xor32(lhs, scratch);
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@ -2678,13 +2684,14 @@ bool CacheIRCompiler::emitInt32BitXorResult() {
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return true;
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}
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bool CacheIRCompiler::emitInt32BitAndResult() {
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bool CacheIRCompiler::emitInt32BitAndResult(Int32OperandId lhsId,
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Int32OperandId rhsId) {
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JitSpew(JitSpew_Codegen, "%s", __FUNCTION__);
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AutoOutputRegister output(*this);
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AutoScratchRegisterMaybeOutput scratch(allocator, masm, output);
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Register lhs = allocator.useRegister(masm, reader.int32OperandId());
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Register rhs = allocator.useRegister(masm, reader.int32OperandId());
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Register lhs = allocator.useRegister(masm, lhsId);
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Register rhs = allocator.useRegister(masm, rhsId);
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masm.mov(rhs, scratch);
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masm.and32(lhs, scratch);
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@ -2692,11 +2699,12 @@ bool CacheIRCompiler::emitInt32BitAndResult() {
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return true;
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}
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bool CacheIRCompiler::emitInt32LeftShiftResult() {
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bool CacheIRCompiler::emitInt32LeftShiftResult(Int32OperandId lhsId,
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Int32OperandId rhsId) {
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JitSpew(JitSpew_Codegen, "%s", __FUNCTION__);
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AutoOutputRegister output(*this);
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Register lhs = allocator.useRegister(masm, reader.int32OperandId());
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Register rhs = allocator.useRegister(masm, reader.int32OperandId());
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Register lhs = allocator.useRegister(masm, lhsId);
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Register rhs = allocator.useRegister(masm, rhsId);
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AutoScratchRegisterMaybeOutput scratch(allocator, masm, output);
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masm.mov(lhs, scratch);
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@ -2708,11 +2716,12 @@ bool CacheIRCompiler::emitInt32LeftShiftResult() {
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return true;
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}
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bool CacheIRCompiler::emitInt32RightShiftResult() {
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bool CacheIRCompiler::emitInt32RightShiftResult(Int32OperandId lhsId,
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Int32OperandId rhsId) {
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JitSpew(JitSpew_Codegen, "%s", __FUNCTION__);
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AutoOutputRegister output(*this);
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Register lhs = allocator.useRegister(masm, reader.int32OperandId());
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Register rhs = allocator.useRegister(masm, reader.int32OperandId());
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Register lhs = allocator.useRegister(masm, lhsId);
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Register rhs = allocator.useRegister(masm, rhsId);
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AutoScratchRegisterMaybeOutput scratch(allocator, masm, output);
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masm.mov(lhs, scratch);
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@ -2724,13 +2733,14 @@ bool CacheIRCompiler::emitInt32RightShiftResult() {
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return true;
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}
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bool CacheIRCompiler::emitInt32URightShiftResult() {
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bool CacheIRCompiler::emitInt32URightShiftResult(Int32OperandId lhsId,
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Int32OperandId rhsId,
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bool allowDouble) {
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JitSpew(JitSpew_Codegen, "%s", __FUNCTION__);
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AutoOutputRegister output(*this);
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Register lhs = allocator.useRegister(masm, reader.int32OperandId());
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Register rhs = allocator.useRegister(masm, reader.int32OperandId());
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bool allowDouble = reader.readBool();
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Register lhs = allocator.useRegister(masm, lhsId);
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Register rhs = allocator.useRegister(masm, rhsId);
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AutoScratchRegisterMaybeOutput scratch(allocator, masm, output);
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FailurePath* failure;
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@ -2816,10 +2826,10 @@ bool CacheIRCompiler::emitInt32DecResult() {
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return true;
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}
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bool CacheIRCompiler::emitInt32NotResult() {
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bool CacheIRCompiler::emitInt32NotResult(Int32OperandId inputId) {
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JitSpew(JitSpew_Codegen, "%s", __FUNCTION__);
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AutoOutputRegister output(*this);
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Register val = allocator.useRegister(masm, reader.int32OperandId());
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Register val = allocator.useRegister(masm, inputId);
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AutoScratchRegisterMaybeOutput scratch(allocator, masm, output);
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masm.mov(val, scratch);
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@ -1004,24 +1004,28 @@
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- name: Int32MulResult
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shared: true
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gen_boilerplate: true
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operands:
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lhs: Int32Id
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rhs: Int32Id
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- name: Int32DivResult
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shared: true
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gen_boilerplate: true
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operands:
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lhs: Int32Id
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rhs: Int32Id
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- name: Int32ModResult
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shared: true
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gen_boilerplate: true
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operands:
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lhs: Int32Id
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rhs: Int32Id
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- name: Int32PowResult
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shared: true
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gen_boilerplate: true
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operands:
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lhs: Int32Id
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rhs: Int32Id
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@ -1064,36 +1068,42 @@
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- name: Int32BitOrResult
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shared: true
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gen_boilerplate: true
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operands:
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lhs: Int32Id
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rhs: Int32Id
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- name: Int32BitXorResult
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shared: true
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gen_boilerplate: true
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operands:
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lhs: Int32Id
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rhs: Int32Id
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- name: Int32BitAndResult
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shared: true
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gen_boilerplate: true
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operands:
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lhs: Int32Id
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rhs: Int32Id
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- name: Int32LeftShiftResult
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shared: true
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gen_boilerplate: true
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operands:
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lhs: Int32Id
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rhs: Int32Id
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- name: Int32RightShiftResult
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shared: true
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gen_boilerplate: true
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operands:
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lhs: Int32Id
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rhs: Int32Id
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- name: Int32URightShiftResult
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shared: true
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gen_boilerplate: true
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operands:
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lhs: Int32Id
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rhs: Int32Id
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@ -1101,6 +1111,7 @@
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- name: Int32NotResult
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shared: true
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gen_boilerplate: true
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operands:
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input: Int32Id
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