Bug 1687936 - Fix uminv/umaxv/sminv/smaxv; fix config. r=nbp

Fix the vector min/max reductions to not overwrite the source before writing the
destination, if src == dest.

Fix moz.configure to enable wasm simd by default even if we're running on the
simulator, this was a bug that has prevented us from testing cranelift
(and the simulator, as this bug shows) as well as we should, up until now.

Differential Revision: https://phabricator.services.mozilla.com/D102594

js/moz.configure

@@ -764,9 +764,15 @@ set_define("ENABLE_SHARED_MEMORY", enable_shared_memory)
 
 @depends("--enable-jit", "--enable-simulator", target)
 def default_wasm_simd(jit_enabled, simulator, target):
-    if not jit_enabled or simulator:
+    if not jit_enabled:
         return
 
+    if simulator:
+        if simulator[0] == "arm64":
+            return True
+        else:
+            return
+
     if target.cpu in ("x86_64", "x86", "aarch64"):
         return True
 
@@ -783,11 +789,16 @@ def wasm_simd(value, jit_enabled, simulator, target):
     if not value:
         return
 
-    if jit_enabled and not simulator:
-        if target.cpu in ("x86_64", "x86", "aarch64"):
-            return True
+    if not jit_enabled:
+        return
 
-    if jit_enabled and simulator and simulator[0] == "arm64":
+    if simulator:
+        if simulator[0] == "arm64":
+            return True
+        else:
+            return
+
+    if target.cpu in ("x86_64", "x86", "aarch64"):
         return True
 
     die("--enable-wasm-simd only possible when targeting the x86_64/x86/arm64 jits")

js/src/jit/arm64/vixl/Logic-vixl.cpp

@@ -1165,7 +1165,6 @@ LogicVRegister Simulator::sminmaxv(VectorFormat vform,
   dst.ClearForWrite(vform);
   int64_t dst_val = max ? INT64_MIN : INT64_MAX;
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst.SetInt(vform, i, 0);
     int64_t src_val = src.Int(vform, i);
     if (max == true) {
       dst_val = (src_val > dst_val) ? src_val : dst_val;
@@ -1173,6 +1172,9 @@ LogicVRegister Simulator::sminmaxv(VectorFormat vform,
       dst_val = (src_val < dst_val) ? src_val : dst_val;
     }
   }
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    dst.SetInt(vform, i, 0);
+  }
   dst.SetInt(vform, 0, dst_val);
   return dst;
 }
@@ -1280,7 +1282,6 @@ LogicVRegister Simulator::uminmaxv(VectorFormat vform,
   dst.ClearForWrite(vform);
   uint64_t dst_val = max ? 0 : UINT64_MAX;
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst.SetUint(vform, i, 0);
     uint64_t src_val = src.Uint(vform, i);
     if (max == true) {
       dst_val = (src_val > dst_val) ? src_val : dst_val;
@@ -1288,6 +1289,9 @@ LogicVRegister Simulator::uminmaxv(VectorFormat vform,
       dst_val = (src_val < dst_val) ? src_val : dst_val;
     }
   }
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    dst.SetUint(vform, i, 0);
+  }
   dst.SetUint(vform, 0, dst_val);
   return dst;
 }