From a0e8029ae0393967b74840fa097880ffb8a9e732 Mon Sep 17 00:00:00 2001
From: Nicholas Cameron <ncameron@mozilla.com>
Date: Tue, 18 Dec 2012 23:55:12 +1300
Subject: [PATCH] Bug 818816; add conditional breakpoints for the ARM macro
 assembler. r=mjrosenb

---
 js/src/ion/arm/Assembler-arm.h        | 16 ++++++++--------
 js/src/ion/arm/MacroAssembler-arm.cpp |  6 ++++++
 js/src/ion/arm/MacroAssembler-arm.h   |  2 ++
 3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/js/src/ion/arm/Assembler-arm.h b/js/src/ion/arm/Assembler-arm.h
index 3f9b382ae464..cefa9751b2f5 100644
--- a/js/src/ion/arm/Assembler-arm.h
+++ b/js/src/ion/arm/Assembler-arm.h
@@ -709,28 +709,28 @@ class DtrOffReg : public DtrOff
     // These are designed to be called by a constructor of a subclass.
     // Constructing the necessary RIS/RRS structures are annoying
   protected:
-    DtrOffReg(Register rn, ShiftType type, datastore::RIS shiftImm)
-      : DtrOff(datastore::Reg(rn.code(), type, 0, shiftImm.encode()))
+    DtrOffReg(Register rn, ShiftType type, datastore::RIS shiftImm, IsUp_ iu = IsUp)
+      : DtrOff(datastore::Reg(rn.code(), type, 0, shiftImm.encode()), iu)
     { }
 
-    DtrOffReg(Register rn, ShiftType type, datastore::RRS shiftReg)
-      : DtrOff(datastore::Reg(rn.code(), type, 1, shiftReg.encode()))
+    DtrOffReg(Register rn, ShiftType type, datastore::RRS shiftReg, IsUp_ iu = IsUp)
+      : DtrOff(datastore::Reg(rn.code(), type, 1, shiftReg.encode()), iu)
     { }
 };
 
 class DtrRegImmShift : public DtrOffReg
 {
   public:
-    DtrRegImmShift(Register rn, ShiftType type, uint32_t shift)
-      : DtrOffReg(rn, type, datastore::RIS(shift))
+    DtrRegImmShift(Register rn, ShiftType type, uint32_t shift, IsUp_ iu = IsUp)
+      : DtrOffReg(rn, type, datastore::RIS(shift), iu)
     { }
 };
 
 class DtrRegRegShift : public DtrOffReg
 {
   public:
-    DtrRegRegShift(Register rn, ShiftType type, Register rs)
-      : DtrOffReg(rn, type, datastore::RRS(rs.code()))
+    DtrRegRegShift(Register rn, ShiftType type, Register rs, IsUp_ iu = IsUp)
+      : DtrOffReg(rn, type, datastore::RRS(rs.code()), iu)
     { }
 };
 
diff --git a/js/src/ion/arm/MacroAssembler-arm.cpp b/js/src/ion/arm/MacroAssembler-arm.cpp
index 74e9f10a6513..f1c900cc46c3 100644
--- a/js/src/ion/arm/MacroAssembler-arm.cpp
+++ b/js/src/ion/arm/MacroAssembler-arm.cpp
@@ -2644,6 +2644,12 @@ MacroAssemblerARMCompat::breakpoint()
     as_bkpt();
 }
 
+void
+MacroAssemblerARMCompat::breakpoint(Condition cc)
+{
+    ma_ldr(DTRAddr(r12, DtrRegImmShift(r12, LSL, 0, IsDown)), r12, Offset, cc);
+}
+
 void
 MacroAssemblerARMCompat::setupABICall(uint32_t args)
 {
diff --git a/js/src/ion/arm/MacroAssembler-arm.h b/js/src/ion/arm/MacroAssembler-arm.h
index 209beacb3a6d..c1ad7a16b939 100644
--- a/js/src/ion/arm/MacroAssembler-arm.h
+++ b/js/src/ion/arm/MacroAssembler-arm.h
@@ -1030,6 +1030,8 @@ class MacroAssemblerARMCompat : public MacroAssemblerARM
     void setStackArg(const Register &reg, uint32_t arg);
 
     void breakpoint();
+    // conditional breakpoint
+    void breakpoint(Condition cc);
 
     void compareDouble(FloatRegister lhs, FloatRegister rhs);
     void branchDouble(DoubleCondition cond, const FloatRegister &lhs, const FloatRegister &rhs,