зеркало из https://github.com/mozilla/gecko-dev.git
Bug 1756347 part 1 - Work around a GCC issue with generated atomics. r=lth
Use MOZ_NEVER_INLINE for GCC x86-32. It seems to run out of byte registers when inlining these functions. Differential Revision: https://phabricator.services.mozilla.com/D139703
This commit is contained in:
Jan de Mooij
Родитель
88428ea7e6
Коммит
a373891863
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@ -10,6 +10,7 @@ import buildconfig
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is_64bit = "JS_64BIT" in buildconfig.defines
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cpu_arch = buildconfig.substs["CPU_ARCH"]
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is_gcc = buildconfig.substs["CC_TYPE"] == "gcc"
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def fmt_insn(s):
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@ -19,21 +20,21 @@ def fmt_insn(s):
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def gen_seqcst(fun_name):
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if cpu_arch in ("x86", "x86_64"):
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return r"""
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inline void %(fun_name)s() {
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INLINE_ATTR void %(fun_name)s() {
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asm volatile ("mfence\n\t" ::: "memory");
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}""" % {
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"fun_name": fun_name,
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}
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if cpu_arch == "aarch64":
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return r"""
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inline void %(fun_name)s() {
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INLINE_ATTR void %(fun_name)s() {
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asm volatile ("dmb ish\n\t" ::: "memory");
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}""" % {
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"fun_name": fun_name,
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}
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if cpu_arch == "arm":
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return r"""
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inline void %(fun_name)s() {
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INLINE_ATTR void %(fun_name)s() {
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asm volatile ("dmb sy\n\t" ::: "memory");
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}""" % {
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"fun_name": fun_name,
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@ -63,7 +64,7 @@ def gen_load(fun_name, cpp_type, size, barrier):
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if barrier:
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insns += fmt_insn("mfence")
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return """
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inline %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) {
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INLINE_ATTR %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) {
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%(cpp_type)s res;
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asm volatile (%(insns)s
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: [res] "=r" (res)
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@ -91,7 +92,7 @@ def gen_load(fun_name, cpp_type, size, barrier):
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if barrier:
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insns += fmt_insn("dmb ish")
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return """
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inline %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) {
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INLINE_ATTR %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) {
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%(cpp_type)s res;
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asm volatile (%(insns)s
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: [res] "=r" (res)
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@ -117,7 +118,7 @@ def gen_load(fun_name, cpp_type, size, barrier):
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if barrier:
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insns += fmt_insn("dmb sy")
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return """
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inline %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) {
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INLINE_ATTR %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) {
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%(cpp_type)s res;
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asm volatile (%(insns)s
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: [res] "=r" (res)
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@ -154,7 +155,7 @@ def gen_store(fun_name, cpp_type, size, barrier):
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if barrier:
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insns += fmt_insn("mfence")
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return """
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inline void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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INLINE_ATTR void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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asm volatile (%(insns)s
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:
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: [addr] "r" (addr), [val] "r"(val)
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@ -180,7 +181,7 @@ def gen_store(fun_name, cpp_type, size, barrier):
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if barrier:
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insns += fmt_insn("dmb ish")
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return """
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inline void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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INLINE_ATTR void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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asm volatile (%(insns)s
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:
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: [addr] "r" (addr), [val] "r"(val)
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@ -204,7 +205,7 @@ def gen_store(fun_name, cpp_type, size, barrier):
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if barrier:
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insns += fmt_insn("dmb sy")
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return """
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inline void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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INLINE_ATTR void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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asm volatile (%(insns)s
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:
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: [addr] "r" (addr), [val] "r"(val)
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@ -235,7 +236,7 @@ def gen_exchange(fun_name, cpp_type, size):
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assert size == 64
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insns += fmt_insn("xchgq %[val], (%[addr])")
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return """
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inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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asm volatile (%(insns)s
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: [val] "+r" (val)
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: [addr] "r" (addr)
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@ -266,7 +267,7 @@ def gen_exchange(fun_name, cpp_type, size):
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insns += fmt_insn("cbnz %w[scratch], 0b")
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insns += fmt_insn("dmb ish")
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return """
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inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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%(cpp_type)s res;
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uint32_t scratch;
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asm volatile (%(insns)s
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@ -297,7 +298,7 @@ def gen_exchange(fun_name, cpp_type, size):
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insns += fmt_insn("beq 0b")
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insns += fmt_insn("dmb sy")
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return """
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inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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%(cpp_type)s res;
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uint32_t scratch;
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asm volatile (%(insns)s
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@ -321,7 +322,7 @@ def gen_cmpxchg(fun_name, cpp_type, size):
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# Use a +A constraint to load `oldval` into EDX:EAX as input/output.
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# `newval` is loaded into ECX:EBX.
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return r"""
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inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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%(cpp_type)s oldval,
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%(cpp_type)s newval) {
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asm volatile ("lock; cmpxchg8b (%%[addr])\n\t"
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@ -337,7 +338,7 @@ def gen_cmpxchg(fun_name, cpp_type, size):
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}
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if cpu_arch == "arm" and size == 64:
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return r"""
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inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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%(cpp_type)s oldval,
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%(cpp_type)s newval) {
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uint32_t oldval0 = oldval & 0xffff'ffff;
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@ -380,7 +381,7 @@ def gen_cmpxchg(fun_name, cpp_type, size):
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assert size == 64
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insns += fmt_insn("lock; cmpxchgq %[newval], (%[addr])")
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return """
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inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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%(cpp_type)s oldval,
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%(cpp_type)s newval) {
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asm volatile (%(insns)s
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@ -425,7 +426,7 @@ def gen_cmpxchg(fun_name, cpp_type, size):
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insns += fmt_insn("cbnz %w[scratch], 0b")
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insns += fmt_insn("1: dmb ish")
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return """
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inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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%(cpp_type)s oldval,
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%(cpp_type)s newval) {
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%(cpp_type)s res, scratch;
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@ -466,7 +467,7 @@ def gen_cmpxchg(fun_name, cpp_type, size):
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insns += fmt_insn("beq 0b")
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insns += fmt_insn("1: dmb sy")
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return """
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inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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%(cpp_type)s oldval,
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%(cpp_type)s newval) {
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%(cpp_type)s res, scratch;
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@ -501,7 +502,7 @@ def gen_fetchop(fun_name, cpp_type, size, op):
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assert size == 64
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insns += fmt_insn("lock; xaddq %[val], (%[addr])")
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return """
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inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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asm volatile (%(insns)s
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: [val] "+&r" (val)
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: [addr] "r" (addr)
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@ -539,7 +540,7 @@ def gen_fetchop(fun_name, cpp_type, size, op):
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insns = insns.replace("OP", op)
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insns += fmt_insn("jnz 0b")
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return """
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inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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%(cpp_type)s res, scratch;
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asm volatile (%(insns)s
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: [res] "=&a" (res), [scratch] "=&r" (scratch)
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@ -581,7 +582,7 @@ def gen_fetchop(fun_name, cpp_type, size, op):
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insns += fmt_insn("cbnz %w[scratch2], 0b")
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insns += fmt_insn("dmb ish")
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return """
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inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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%(cpp_type)s res;
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uintptr_t scratch1, scratch2;
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asm volatile (%(insns)s
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@ -621,7 +622,7 @@ def gen_fetchop(fun_name, cpp_type, size, op):
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insns += fmt_insn("beq 0b")
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insns += fmt_insn("dmb sy")
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return """
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inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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%(cpp_type)s res;
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uintptr_t scratch1, scratch2;
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asm volatile (%(insns)s
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@ -681,7 +682,7 @@ def gen_copy(fun_name, cpp_type, size, unroll, direction):
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offset -= 1
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return """
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inline void %(fun_name)s(uint8_t* dst, const uint8_t* src) {
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INLINE_ATTR void %(fun_name)s(uint8_t* dst, const uint8_t* src) {
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%(cpp_type)s* dst_ = reinterpret_cast<%(cpp_type)s*>(dst);
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const %(cpp_type)s* src_ = reinterpret_cast<const %(cpp_type)s*>(src);
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%(cpp_type)s scratch;
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@ -853,6 +854,13 @@ def generate_atomics_header(c_out):
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"constexpr size_t JS_GENERATED_ATOMICS_WORDSIZE = " + str(wordsize) + ";\n"
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)
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# Work around a GCC issue on 32-bit x86 by adding MOZ_NEVER_INLINE.
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# See bug 1756347.
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if is_gcc and cpu_arch == "x86":
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contents = contents.replace("INLINE_ATTR", "MOZ_NEVER_INLINE inline")
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else:
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contents = contents.replace("INLINE_ATTR", "inline")
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c_out.write(
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HEADER_TEMPLATE
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% {
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