зеркало из https://github.com/mozilla/gecko-dev.git
Bug 1752404 - Remove MacroAssembler-x86-shared-SIMD-unused.cpp. r=lth
Differential Revision: https://phabricator.services.mozilla.com/D137458
This commit is contained in:
Yury Delendik
Родитель
472075915e
Коммит
a55812b188
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@ -104,7 +104,6 @@ elif CONFIG["JS_CODEGEN_X86"] or CONFIG["JS_CODEGEN_X64"]:
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"x86-shared/AssemblerBuffer-x86-shared.cpp",
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"x86-shared/CodeGenerator-x86-shared.cpp",
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"x86-shared/Lowering-x86-shared.cpp",
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"x86-shared/MacroAssembler-x86-shared-SIMD-unused.cpp",
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"x86-shared/MacroAssembler-x86-shared-SIMD.cpp",
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"x86-shared/MacroAssembler-x86-shared.cpp",
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"x86-shared/MoveEmitter-x86-shared.cpp",
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@ -1,627 +0,0 @@
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/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 2 -*-
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* vim: set ts=8 sts=2 et sw=2 tw=80:
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#include "jit/MacroAssembler.h"
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#include "jit/x86-shared/MacroAssembler-x86-shared.h"
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#include "jit/MacroAssembler-inl.h"
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using namespace js;
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using namespace js::jit;
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using mozilla::DebugOnly;
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using mozilla::FloatingPoint;
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using mozilla::Maybe;
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using mozilla::SpecificNaN;
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// The following routines are from the old asm.js implementation but are UNUSED
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// in the wasm implementation currently. They are preserved here because it's
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// sad to throw out working code. They are defined in the header file.
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//
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// Before using these, they should minimally be moved to
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// MacroAssembler-x86-shared-SIMD.cpp, and it would be a wrong move to assume
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// that they are correct according to the wasm spec.
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void MacroAssemblerX86Shared::checkedConvertFloat32x4ToInt32x4(
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FloatRegister src, FloatRegister dest, Register temp, Label* oolEntry,
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Label* rejoin) {
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// Does the conversion and jumps to the OOL entry if the result value
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// is the undefined integer pattern.
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static const SimdConstant InvalidResult =
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SimdConstant::SplatX4(int32_t(-2147483648));
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convertFloat32x4ToInt32x4(src, dest);
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ScratchSimd128Scope scratch(asMasm());
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asMasm().loadConstantSimd128Int(InvalidResult, scratch);
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vpcmpeqd(Operand(dest), scratch, scratch);
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// TODO (bug 1156228): If we have SSE4.1, we can use PTEST here instead of
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// the two following instructions.
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vmovmskps(scratch, temp);
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cmp32(temp, Imm32(0));
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j(Assembler::NotEqual, oolEntry);
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bind(rejoin);
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}
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void MacroAssemblerX86Shared::oolConvertFloat32x4ToInt32x4(
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FloatRegister src, Register temp, Label* rejoin, Label* onConversionError) {
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static const SimdConstant Int32MaxX4 = SimdConstant::SplatX4(2147483647.f);
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static const SimdConstant Int32MinX4 = SimdConstant::SplatX4(-2147483648.f);
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ScratchSimd128Scope scratch(asMasm());
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asMasm().loadConstantSimd128Float(Int32MinX4, scratch);
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vcmpleps(Operand(src), scratch, scratch);
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vmovmskps(scratch, temp);
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cmp32(temp, Imm32(15));
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j(Assembler::NotEqual, onConversionError);
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asMasm().loadConstantSimd128Float(Int32MaxX4, scratch);
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vcmpleps(Operand(src), scratch, scratch);
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vmovmskps(scratch, temp);
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cmp32(temp, Imm32(0));
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j(Assembler::NotEqual, onConversionError);
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jump(rejoin);
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}
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void MacroAssemblerX86Shared::checkedConvertFloat32x4ToUint32x4(
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FloatRegister in, FloatRegister out, Register temp, FloatRegister tempF,
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Label* failed) {
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// Classify lane values into 4 disjoint classes:
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//
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// N-lanes: in <= -1.0
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// A-lanes: -1.0 < in <= 0x0.ffffffp31
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// B-lanes: 0x1.0p31 <= in <= 0x0.ffffffp32
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// V-lanes: 0x1.0p32 <= in, or isnan(in)
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//
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// We need to bail out to throw a RangeError if we see any N-lanes or
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// V-lanes.
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//
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// For A-lanes and B-lanes, we make two float -> int32 conversions:
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//
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// A = cvttps2dq(in)
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// B = cvttps2dq(in - 0x1.0p31f)
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//
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// Note that the subtraction for the B computation is exact for B-lanes.
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// There is no rounding, so B is the low 31 bits of the correctly converted
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// result.
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//
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// The cvttps2dq instruction produces 0x80000000 when the input is NaN or
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// out of range for a signed int32_t. This conveniently provides the missing
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// high bit for B, so the desired result is A for A-lanes and A|B for
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// B-lanes.
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ScratchSimd128Scope scratch(asMasm());
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// TODO: If the majority of lanes are A-lanes, it could be faster to compute
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// A first, use vmovmskps to check for any non-A-lanes and handle them in
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// ool code. OTOH, we we're wrong about the lane distribution, that would be
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// slower.
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// Compute B in |scratch|.
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static const float Adjust = 0x80000000; // 0x1.0p31f for the benefit of MSVC.
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static const SimdConstant Bias = SimdConstant::SplatX4(-Adjust);
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asMasm().loadConstantSimd128Float(Bias, scratch);
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packedAddFloat32(Operand(in), scratch);
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convertFloat32x4ToInt32x4(scratch, scratch);
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// Compute A in |out|. This is the last time we use |in| and the first time
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// we use |out|, so we can tolerate if they are the same register.
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convertFloat32x4ToInt32x4(in, out);
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// We can identify A-lanes by the sign bits in A: Any A-lanes will be
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// positive in A, and N, B, and V-lanes will be 0x80000000 in A. Compute a
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// mask of non-A-lanes into |tempF|.
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zeroSimd128Float(tempF);
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vpcmpgtd(Operand(out), tempF, tempF);
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// Clear the A-lanes in B.
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bitwiseAndSimdInt(scratch, Operand(tempF), scratch);
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// Compute the final result: A for A-lanes, A|B for B-lanes.
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bitwiseOrSimdInt(out, Operand(scratch), out);
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// We still need to filter out the V-lanes. They would show up as 0x80000000
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// in both A and B. Since we cleared the valid A-lanes in B, the V-lanes are
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// the remaining negative lanes in B.
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vmovmskps(scratch, temp);
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cmp32(temp, Imm32(0));
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j(Assembler::NotEqual, failed);
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}
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void MacroAssemblerX86Shared::createInt32x4(Register lane0, Register lane1,
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Register lane2, Register lane3,
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FloatRegister dest) {
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if (AssemblerX86Shared::HasSSE41()) {
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vmovd(lane0, dest);
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vpinsrd(1, lane1, dest, dest);
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vpinsrd(2, lane2, dest, dest);
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vpinsrd(3, lane3, dest, dest);
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return;
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}
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asMasm().reserveStack(Simd128DataSize);
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store32(lane0, Address(StackPointer, 0 * sizeof(int32_t)));
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store32(lane1, Address(StackPointer, 1 * sizeof(int32_t)));
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store32(lane2, Address(StackPointer, 2 * sizeof(int32_t)));
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store32(lane3, Address(StackPointer, 3 * sizeof(int32_t)));
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loadAlignedSimd128Int(Address(StackPointer, 0), dest);
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asMasm().freeStack(Simd128DataSize);
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}
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void MacroAssemblerX86Shared::createFloat32x4(
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FloatRegister lane0, FloatRegister lane1, FloatRegister lane2,
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FloatRegister lane3, FloatRegister temp, FloatRegister output) {
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FloatRegister lane0Copy = reusedInputSimd128Float(lane0, output);
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FloatRegister lane1Copy = reusedInputSimd128Float(lane1, temp);
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vunpcklps(lane3, lane1Copy, temp);
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vunpcklps(lane2, lane0Copy, output);
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vunpcklps(temp, output, output);
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}
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void MacroAssemblerX86Shared::reinterpretSimd(bool isIntegerLaneType,
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FloatRegister input,
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FloatRegister output) {
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if (input.aliases(output)) {
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return;
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}
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if (isIntegerLaneType) {
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vmovdqa(input, output);
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} else {
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vmovaps(input, output);
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}
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}
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void MacroAssemblerX86Shared::extractLaneSimdBool(FloatRegister input,
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Register output,
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unsigned numLanes,
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unsigned lane) {
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switch (numLanes) {
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case 4:
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extractLaneInt32x4(input, output, lane);
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break;
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case 8:
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// Get a lane, don't bother fixing the high bits since we'll mask below.
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extractLaneInt16x8(input, output, lane, SimdSign::NotApplicable);
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break;
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case 16:
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extractLaneInt8x16(input, output, lane, SimdSign::NotApplicable);
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break;
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default:
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MOZ_CRASH("Unhandled SIMD number of lanes");
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}
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// We need to generate a 0/1 value. We have 0/-1 and possibly dirty high bits.
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asMasm().and32(Imm32(1), output);
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}
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void MacroAssemblerX86Shared::allTrueSimdBool(FloatRegister input,
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Register output) {
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// We know that the input lanes are boolean, so they are either 0 or -1.
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// The all-true vector has all 128 bits set, no matter the lane geometry.
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vpmovmskb(input, output);
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cmp32(output, Imm32(0xffff));
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emitSet(Assembler::Zero, output);
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}
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void MacroAssemblerX86Shared::anyTrueSimdBool(FloatRegister input,
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Register output) {
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vpmovmskb(input, output);
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cmp32(output, Imm32(0x0));
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emitSet(Assembler::NonZero, output);
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}
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void MacroAssemblerX86Shared::swizzleInt32x4(FloatRegister input,
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FloatRegister output,
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unsigned lanes[4]) {
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uint32_t mask = MacroAssembler::ComputeShuffleMask(lanes[0], lanes[1],
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lanes[2], lanes[3]);
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shuffleInt32(mask, input, output);
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}
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// For SIMD.js
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void MacroAssemblerX86Shared::oldSwizzleInt8x16(FloatRegister input,
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FloatRegister output,
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const Maybe<Register>& temp,
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int8_t lanes[16]) {
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if (AssemblerX86Shared::HasSSSE3()) {
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ScratchSimd128Scope scratch(asMasm());
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asMasm().loadConstantSimd128Int(SimdConstant::CreateX16(lanes), scratch);
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FloatRegister inputCopy = reusedInputInt32x4(input, output);
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vpshufb(scratch, inputCopy, output);
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return;
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}
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// Worst-case fallback for pre-SSSE3 machines. Bounce through memory.
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MOZ_ASSERT(!!temp, "needs a temp for the memory fallback");
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asMasm().reserveStack(2 * Simd128DataSize);
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storeAlignedSimd128Int(input, Address(StackPointer, Simd128DataSize));
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for (unsigned i = 0; i < 16; i++) {
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load8ZeroExtend(Address(StackPointer, Simd128DataSize + lanes[i]), *temp);
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store8(*temp, Address(StackPointer, i));
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}
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loadAlignedSimd128Int(Address(StackPointer, 0), output);
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asMasm().freeStack(2 * Simd128DataSize);
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}
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static inline bool LanesMatch(unsigned lanes[4], unsigned x, unsigned y,
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unsigned z, unsigned w) {
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return lanes[0] == x && lanes[1] == y && lanes[2] == z && lanes[3] == w;
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}
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void MacroAssemblerX86Shared::swizzleFloat32x4(FloatRegister input,
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FloatRegister output,
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unsigned lanes[4]) {
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if (AssemblerX86Shared::HasSSE3()) {
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if (LanesMatch(lanes, 0, 0, 2, 2)) {
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vmovsldup(input, output);
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return;
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}
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if (LanesMatch(lanes, 1, 1, 3, 3)) {
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vmovshdup(input, output);
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return;
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}
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}
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// TODO Here and below, arch specific lowering could identify this pattern
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// and use defineReuseInput to avoid this move (bug 1084404)
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if (LanesMatch(lanes, 2, 3, 2, 3)) {
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FloatRegister inputCopy = reusedInputSimd128Float(input, output);
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vmovhlps(input, inputCopy, output);
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return;
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}
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if (LanesMatch(lanes, 0, 1, 0, 1)) {
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if (AssemblerX86Shared::HasSSE3() && !AssemblerX86Shared::HasAVX()) {
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vmovddup(Operand(input), output);
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return;
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}
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FloatRegister inputCopy = reusedInputSimd128Float(input, output);
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vmovlhps(input, inputCopy, output);
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return;
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}
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if (LanesMatch(lanes, 0, 0, 1, 1)) {
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FloatRegister inputCopy = reusedInputSimd128Float(input, output);
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vunpcklps(input, inputCopy, output);
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return;
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}
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if (LanesMatch(lanes, 2, 2, 3, 3)) {
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FloatRegister inputCopy = reusedInputSimd128Float(input, output);
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vunpckhps(input, inputCopy, output);
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return;
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}
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uint32_t x = lanes[0];
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uint32_t y = lanes[1];
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uint32_t z = lanes[2];
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uint32_t w = lanes[3];
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uint32_t mask = MacroAssembler::ComputeShuffleMask(x, y, z, w);
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shuffleFloat32(mask, input, output);
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}
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void MacroAssemblerX86Shared::shuffleX4(FloatRegister lhs, Operand rhs,
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FloatRegister out,
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const Maybe<FloatRegister>& maybeTemp,
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unsigned lanes[4]) {
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uint32_t x = lanes[0];
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uint32_t y = lanes[1];
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uint32_t z = lanes[2];
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uint32_t w = lanes[3];
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// Check that lanes come from LHS in majority:
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unsigned numLanesFromLHS = (x < 4) + (y < 4) + (z < 4) + (w < 4);
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MOZ_ASSERT(numLanesFromLHS >= 2);
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// When reading this method, remember that vshufps takes the two first
|
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// inputs of the destination operand (right operand) and the two last
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// inputs of the source operand (left operand).
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//
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// Legend for explanations:
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// - L: LHS
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// - R: RHS
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// - T: temporary
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uint32_t mask;
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// If all lanes came from a single vector, we should use swizzle instead.
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MOZ_ASSERT(numLanesFromLHS < 4);
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// If all values stay in their lane, this is a blend.
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if (AssemblerX86Shared::HasSSE41()) {
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if (x % 4 == 0 && y % 4 == 1 && z % 4 == 2 && w % 4 == 3) {
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vblendps(blendpsMask(x >= 4, y >= 4, z >= 4, w >= 4), rhs, lhs, out);
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return;
|
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}
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}
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// One element of the second, all other elements of the first
|
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if (numLanesFromLHS == 3) {
|
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unsigned firstMask = -1, secondMask = -1;
|
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|
||||
// register-register vmovss preserves the high lanes.
|
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if (LanesMatch(lanes, 4, 1, 2, 3) && rhs.kind() == Operand::FPREG) {
|
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vmovss(FloatRegister::FromCode(rhs.fpu()), lhs, out);
|
||||
return;
|
||||
}
|
||||
|
||||
// SSE4.1 vinsertps can handle any single element.
|
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unsigned numLanesUnchanged = (x == 0) + (y == 1) + (z == 2) + (w == 3);
|
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if (AssemblerX86Shared::HasSSE41() && numLanesUnchanged == 3) {
|
||||
unsigned srcLane;
|
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unsigned dstLane;
|
||||
if (x >= 4) {
|
||||
srcLane = x - 4;
|
||||
dstLane = 0;
|
||||
} else if (y >= 4) {
|
||||
srcLane = y - 4;
|
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dstLane = 1;
|
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} else if (z >= 4) {
|
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srcLane = z - 4;
|
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dstLane = 2;
|
||||
} else {
|
||||
MOZ_ASSERT(w >= 4);
|
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srcLane = w - 4;
|
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dstLane = 3;
|
||||
}
|
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vinsertps(vinsertpsMask(srcLane, dstLane), rhs, lhs, out);
|
||||
return;
|
||||
}
|
||||
|
||||
MOZ_ASSERT(!!maybeTemp);
|
||||
FloatRegister rhsCopy = *maybeTemp;
|
||||
loadAlignedSimd128Float(rhs, rhsCopy);
|
||||
|
||||
if (x < 4 && y < 4) {
|
||||
if (w >= 4) {
|
||||
w %= 4;
|
||||
// T = (Rw Rw Lz Lz) = vshufps(firstMask, lhs, rhs, rhsCopy)
|
||||
firstMask = MacroAssembler::ComputeShuffleMask(w, w, z, z);
|
||||
// (Lx Ly Lz Rw) = (Lx Ly Tz Tx) = vshufps(secondMask, T, lhs, out)
|
||||
secondMask = MacroAssembler::ComputeShuffleMask(x, y, 2, 0);
|
||||
} else {
|
||||
MOZ_ASSERT(z >= 4);
|
||||
z %= 4;
|
||||
// T = (Rz Rz Lw Lw) = vshufps(firstMask, lhs, rhs, rhsCopy)
|
||||
firstMask = MacroAssembler::ComputeShuffleMask(z, z, w, w);
|
||||
// (Lx Ly Rz Lw) = (Lx Ly Tx Tz) = vshufps(secondMask, T, lhs, out)
|
||||
secondMask = MacroAssembler::ComputeShuffleMask(x, y, 0, 2);
|
||||
}
|
||||
|
||||
vshufps(firstMask, lhs, rhsCopy, rhsCopy);
|
||||
vshufps(secondMask, rhsCopy, lhs, out);
|
||||
return;
|
||||
}
|
||||
|
||||
MOZ_ASSERT(z < 4 && w < 4);
|
||||
|
||||
if (y >= 4) {
|
||||
y %= 4;
|
||||
// T = (Ry Ry Lx Lx) = vshufps(firstMask, lhs, rhs, rhsCopy)
|
||||
firstMask = MacroAssembler::ComputeShuffleMask(y, y, x, x);
|
||||
// (Lx Ry Lz Lw) = (Tz Tx Lz Lw) = vshufps(secondMask, lhs, T, out)
|
||||
secondMask = MacroAssembler::ComputeShuffleMask(2, 0, z, w);
|
||||
} else {
|
||||
MOZ_ASSERT(x >= 4);
|
||||
x %= 4;
|
||||
// T = (Rx Rx Ly Ly) = vshufps(firstMask, lhs, rhs, rhsCopy)
|
||||
firstMask = MacroAssembler::ComputeShuffleMask(x, x, y, y);
|
||||
// (Rx Ly Lz Lw) = (Tx Tz Lz Lw) = vshufps(secondMask, lhs, T, out)
|
||||
secondMask = MacroAssembler::ComputeShuffleMask(0, 2, z, w);
|
||||
}
|
||||
|
||||
vshufps(firstMask, lhs, rhsCopy, rhsCopy);
|
||||
if (AssemblerX86Shared::HasAVX()) {
|
||||
vshufps(secondMask, lhs, rhsCopy, out);
|
||||
} else {
|
||||
vshufps(secondMask, lhs, rhsCopy, rhsCopy);
|
||||
moveSimd128Float(rhsCopy, out);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
// Two elements from one vector, two other elements from the other
|
||||
MOZ_ASSERT(numLanesFromLHS == 2);
|
||||
|
||||
// TODO Here and below, symmetric case would be more handy to avoid a move,
|
||||
// but can't be reached because operands would get swapped (bug 1084404).
|
||||
if (LanesMatch(lanes, 2, 3, 6, 7)) {
|
||||
ScratchSimd128Scope scratch(asMasm());
|
||||
if (AssemblerX86Shared::HasAVX()) {
|
||||
FloatRegister rhsCopy = reusedInputAlignedSimd128Float(rhs, scratch);
|
||||
vmovhlps(lhs, rhsCopy, out);
|
||||
} else {
|
||||
loadAlignedSimd128Float(rhs, scratch);
|
||||
vmovhlps(lhs, scratch, scratch);
|
||||
moveSimd128Float(scratch, out);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if (LanesMatch(lanes, 0, 1, 4, 5)) {
|
||||
FloatRegister rhsCopy;
|
||||
ScratchSimd128Scope scratch(asMasm());
|
||||
if (rhs.kind() == Operand::FPREG) {
|
||||
// No need to make an actual copy, since the operand is already
|
||||
// in a register, and it won't be clobbered by the vmovlhps.
|
||||
rhsCopy = FloatRegister::FromCode(rhs.fpu());
|
||||
} else {
|
||||
loadAlignedSimd128Float(rhs, scratch);
|
||||
rhsCopy = scratch;
|
||||
}
|
||||
vmovlhps(rhsCopy, lhs, out);
|
||||
return;
|
||||
}
|
||||
|
||||
if (LanesMatch(lanes, 0, 4, 1, 5)) {
|
||||
vunpcklps(rhs, lhs, out);
|
||||
return;
|
||||
}
|
||||
|
||||
// TODO swapped case would be better (bug 1084404)
|
||||
if (LanesMatch(lanes, 4, 0, 5, 1)) {
|
||||
ScratchSimd128Scope scratch(asMasm());
|
||||
if (AssemblerX86Shared::HasAVX()) {
|
||||
FloatRegister rhsCopy = reusedInputAlignedSimd128Float(rhs, scratch);
|
||||
vunpcklps(lhs, rhsCopy, out);
|
||||
} else {
|
||||
loadAlignedSimd128Float(rhs, scratch);
|
||||
vunpcklps(lhs, scratch, scratch);
|
||||
moveSimd128Float(scratch, out);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if (LanesMatch(lanes, 2, 6, 3, 7)) {
|
||||
vunpckhps(rhs, lhs, out);
|
||||
return;
|
||||
}
|
||||
|
||||
// TODO swapped case would be better (bug 1084404)
|
||||
if (LanesMatch(lanes, 6, 2, 7, 3)) {
|
||||
ScratchSimd128Scope scratch(asMasm());
|
||||
if (AssemblerX86Shared::HasAVX()) {
|
||||
FloatRegister rhsCopy = reusedInputAlignedSimd128Float(rhs, scratch);
|
||||
vunpckhps(lhs, rhsCopy, out);
|
||||
} else {
|
||||
loadAlignedSimd128Float(rhs, scratch);
|
||||
vunpckhps(lhs, scratch, scratch);
|
||||
moveSimd128Float(scratch, out);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
// In one vshufps
|
||||
if (x < 4 && y < 4) {
|
||||
mask = MacroAssembler::ComputeShuffleMask(x, y, z % 4, w % 4);
|
||||
vshufps(mask, rhs, lhs, out);
|
||||
return;
|
||||
}
|
||||
|
||||
// At creation, we should have explicitly swapped in this case.
|
||||
MOZ_ASSERT(!(z >= 4 && w >= 4));
|
||||
|
||||
// In two vshufps, for the most generic case:
|
||||
uint32_t firstMask[4], secondMask[4];
|
||||
unsigned i = 0, j = 2, k = 0;
|
||||
|
||||
#define COMPUTE_MASK(lane) \
|
||||
if (lane >= 4) { \
|
||||
firstMask[j] = lane % 4; \
|
||||
secondMask[k++] = j++; \
|
||||
} else { \
|
||||
firstMask[i] = lane; \
|
||||
secondMask[k++] = i++; \
|
||||
}
|
||||
|
||||
COMPUTE_MASK(x)
|
||||
COMPUTE_MASK(y)
|
||||
COMPUTE_MASK(z)
|
||||
COMPUTE_MASK(w)
|
||||
#undef COMPUTE_MASK
|
||||
|
||||
MOZ_ASSERT(i == 2 && j == 4 && k == 4);
|
||||
|
||||
mask = MacroAssembler::ComputeShuffleMask(firstMask[0], firstMask[1],
|
||||
firstMask[2], firstMask[3]);
|
||||
vshufps(mask, rhs, lhs, lhs);
|
||||
|
||||
mask = MacroAssembler::ComputeShuffleMask(secondMask[0], secondMask[1],
|
||||
secondMask[2], secondMask[3]);
|
||||
vshufps(mask, lhs, lhs, lhs);
|
||||
}
|
||||
|
||||
void MacroAssemblerX86Shared::minNumFloat32x4(FloatRegister lhs, Operand rhs,
|
||||
FloatRegister temp,
|
||||
FloatRegister output) {
|
||||
ScratchSimd128Scope scratch(asMasm());
|
||||
asMasm().loadConstantSimd128Int(SimdConstant::SplatX4(int32_t(0x80000000)),
|
||||
temp);
|
||||
|
||||
FloatRegister mask = scratch;
|
||||
FloatRegister tmpCopy = reusedInputSimd128Float(temp, scratch);
|
||||
vpcmpeqd(Operand(lhs), tmpCopy, mask);
|
||||
vandps(temp, mask, mask);
|
||||
|
||||
FloatRegister lhsCopy = reusedInputSimd128Float(lhs, temp);
|
||||
vminps(rhs, lhsCopy, temp);
|
||||
vorps(mask, temp, temp);
|
||||
|
||||
if (AssemblerX86Shared::HasAVX()) {
|
||||
MOZ_CRASH("Can do better by avoiding the movaps");
|
||||
} else {
|
||||
vmovaps(rhs, mask);
|
||||
vcmpneqps(rhs, mask, mask);
|
||||
}
|
||||
|
||||
if (AssemblerX86Shared::HasAVX()) {
|
||||
vblendvps(mask, lhs, temp, output);
|
||||
} else {
|
||||
// Emulate vblendvps.
|
||||
// With SSE.4.1 we could use blendvps, however it's awkward since
|
||||
// it requires the mask to be in xmm0.
|
||||
if (lhs != output) {
|
||||
moveSimd128Float(lhs, output);
|
||||
}
|
||||
vandps(Operand(mask), output, output);
|
||||
vandnps(Operand(temp), mask, mask);
|
||||
vorps(Operand(mask), output, output);
|
||||
}
|
||||
}
|
||||
|
||||
void MacroAssemblerX86Shared::maxNumFloat32x4(FloatRegister lhs, Operand rhs,
|
||||
FloatRegister temp,
|
||||
FloatRegister output) {
|
||||
ScratchSimd128Scope scratch(asMasm());
|
||||
FloatRegister mask = scratch;
|
||||
|
||||
asMasm().loadConstantSimd128Int(SimdConstant::SplatX4(0), mask);
|
||||
vpcmpeqd(Operand(lhs), mask, mask);
|
||||
|
||||
asMasm().loadConstantSimd128Int(SimdConstant::SplatX4(int32_t(0x80000000)),
|
||||
temp);
|
||||
vandps(temp, mask, mask);
|
||||
|
||||
FloatRegister lhsCopy = reusedInputSimd128Float(lhs, temp);
|
||||
vmaxps(rhs, lhsCopy, temp);
|
||||
vandnps(Operand(temp), mask, mask);
|
||||
|
||||
// Ensure temp always contains the temporary result
|
||||
mask = temp;
|
||||
temp = scratch;
|
||||
|
||||
if (AssemblerX86Shared::HasAVX()) {
|
||||
MOZ_CRASH("Can do better by avoiding the movaps");
|
||||
} else {
|
||||
vmovaps(rhs, mask);
|
||||
vcmpneqps(rhs, mask, mask);
|
||||
}
|
||||
|
||||
if (AssemblerX86Shared::HasAVX()) {
|
||||
vblendvps(mask, lhs, temp, output);
|
||||
} else {
|
||||
// Emulate vblendvps.
|
||||
// With SSE.4.1 we could use blendvps, however it's awkward since
|
||||
// it requires the mask to be in xmm0.
|
||||
if (lhs != output) {
|
||||
moveSimd128Float(lhs, output);
|
||||
}
|
||||
vandps(Operand(mask), output, output);
|
||||
vandnps(Operand(temp), mask, mask);
|
||||
vorps(Operand(mask), output, output);
|
||||
}
|
||||
}
|
||||
|
||||
void MacroAssemblerX86Shared::selectX4(FloatRegister mask, FloatRegister onTrue,
|
||||
FloatRegister onFalse,
|
||||
FloatRegister temp,
|
||||
FloatRegister output) {
|
||||
if (AssemblerX86Shared::HasAVX()) {
|
||||
vblendvps(mask, onTrue, onFalse, output);
|
||||
} else {
|
||||
selectSimd128(mask, onTrue, onFalse, temp, output);
|
||||
}
|
||||
}
|
||||
|
|
@ -690,130 +690,6 @@ class MacroAssemblerX86Shared : public Assembler {
|
|||
vshufps(mask, srcCopy, srcCopy, dest);
|
||||
}
|
||||
|
||||
// Unused SIMD methods, defined in MacroAssemble-x86-shared-SIMD-unused.cpp.
|
||||
// Don't use these without moving them out of that file and moving the
|
||||
// declaration into the list above.
|
||||
|
||||
void checkedConvertFloat32x4ToInt32x4(FloatRegister src, FloatRegister dest,
|
||||
Register temp, Label* oolCheck,
|
||||
Label* rejoin);
|
||||
void oolConvertFloat32x4ToInt32x4(FloatRegister src, Register temp,
|
||||
Label* rejoin, Label* onConversionError);
|
||||
void checkedConvertFloat32x4ToUint32x4(FloatRegister src, FloatRegister dest,
|
||||
Register temp, FloatRegister tempF,
|
||||
Label* failed);
|
||||
void createInt32x4(Register lane0, Register lane1, Register lane2,
|
||||
Register lane3, FloatRegister dest);
|
||||
void createFloat32x4(FloatRegister lane0, FloatRegister lane1,
|
||||
FloatRegister lane2, FloatRegister lane3,
|
||||
FloatRegister temp, FloatRegister output);
|
||||
void reinterpretSimd(bool isIntegerLaneType, FloatRegister input,
|
||||
FloatRegister output);
|
||||
void extractLaneSimdBool(FloatRegister input, Register output,
|
||||
unsigned numLanes, unsigned lane);
|
||||
void allTrueSimdBool(FloatRegister input, Register output);
|
||||
void anyTrueSimdBool(FloatRegister input, Register output);
|
||||
void swizzleInt32x4(FloatRegister input, FloatRegister output,
|
||||
unsigned lanes[4]);
|
||||
void swizzleFloat32x4(FloatRegister input, FloatRegister output,
|
||||
unsigned lanes[4]);
|
||||
void oldSwizzleInt8x16(FloatRegister input, FloatRegister output,
|
||||
const mozilla::Maybe<Register>& temp,
|
||||
int8_t lanes[16]);
|
||||
void shuffleX4(FloatRegister lhs, Operand rhs, FloatRegister out,
|
||||
const mozilla::Maybe<FloatRegister>& maybeTemp,
|
||||
unsigned lanes[4]);
|
||||
void minNumFloat32x4(FloatRegister lhs, Operand rhs, FloatRegister temp,
|
||||
FloatRegister output);
|
||||
void maxNumFloat32x4(FloatRegister lhs, Operand rhs, FloatRegister temp,
|
||||
FloatRegister output);
|
||||
|
||||
// Unused inline methods ditto.
|
||||
|
||||
void bitwiseAndSimdInt(FloatRegister lhs, const Operand& rhs,
|
||||
FloatRegister dest) {
|
||||
vpand(rhs, lhs, dest);
|
||||
}
|
||||
void bitwiseOrSimdInt(FloatRegister lhs, const Operand& rhs,
|
||||
FloatRegister dest) {
|
||||
vpor(rhs, lhs, dest);
|
||||
}
|
||||
void bitwiseOrFloat32x4(FloatRegister lhs, const Operand& rhs,
|
||||
FloatRegister dest) {
|
||||
vorps(rhs, lhs, dest);
|
||||
}
|
||||
void bitwiseAndNotFloat32x4(FloatRegister lhs, const Operand& rhs,
|
||||
FloatRegister dest) {
|
||||
vandnps(rhs, lhs, dest);
|
||||
}
|
||||
FloatRegister reusedInputAlignedInt32x4(const Operand& src,
|
||||
FloatRegister dest) {
|
||||
MOZ_ASSERT(dest.isSimd128());
|
||||
if (HasAVX() && src.kind() == Operand::FPREG) {
|
||||
return FloatRegister::FromCode(src.fpu());
|
||||
}
|
||||
loadAlignedSimd128Int(src, dest);
|
||||
return dest;
|
||||
}
|
||||
void packedAddInt8(const Operand& src, FloatRegister dest) {
|
||||
vpaddb(src, dest, dest);
|
||||
}
|
||||
void packedSubInt8(const Operand& src, FloatRegister dest) {
|
||||
vpsubb(src, dest, dest);
|
||||
}
|
||||
void packedAddInt16(const Operand& src, FloatRegister dest) {
|
||||
vpaddw(src, dest, dest);
|
||||
}
|
||||
void packedSubInt16(const Operand& src, FloatRegister dest) {
|
||||
vpsubw(src, dest, dest);
|
||||
}
|
||||
void packedAddInt32(const Operand& src, FloatRegister dest) {
|
||||
vpaddd(src, dest, dest);
|
||||
}
|
||||
void packedSubInt32(const Operand& src, FloatRegister dest) {
|
||||
vpsubd(src, dest, dest);
|
||||
}
|
||||
void packedRcpApproximationFloat32x4(const Operand& src, FloatRegister dest) {
|
||||
// This function is an approximation of the result, this might need
|
||||
// fix up if the spec requires a given precision for this operation.
|
||||
// TODO See also bug 1068028.
|
||||
vrcpps(src, dest);
|
||||
}
|
||||
void packedRcpSqrtApproximationFloat32x4(const Operand& src,
|
||||
FloatRegister dest) {
|
||||
// TODO See comment above. See also bug 1068028.
|
||||
vrsqrtps(src, dest);
|
||||
}
|
||||
FloatRegister reusedInputAlignedSimd128Float(const Operand& src,
|
||||
FloatRegister dest) {
|
||||
MOZ_ASSERT(dest.isSimd128());
|
||||
if (HasAVX() && src.kind() == Operand::FPREG) {
|
||||
return FloatRegister::FromCode(src.fpu());
|
||||
}
|
||||
loadAlignedSimd128Float(src, dest);
|
||||
return dest;
|
||||
}
|
||||
void packedAddFloat32(const Operand& src, FloatRegister dest) {
|
||||
vaddps(src, dest, dest);
|
||||
}
|
||||
void packedSubFloat32(const Operand& src, FloatRegister dest) {
|
||||
vsubps(src, dest, dest);
|
||||
}
|
||||
void packedMulFloat32(const Operand& src, FloatRegister dest) {
|
||||
vmulps(src, dest, dest);
|
||||
}
|
||||
void packedDivFloat32(const Operand& src, FloatRegister dest) {
|
||||
vdivps(src, dest, dest);
|
||||
}
|
||||
void shuffleMix(uint32_t mask, const Operand& src, FloatRegister dest) {
|
||||
// Note this uses vshufps, which is a cross-domain penalty on CPU where it
|
||||
// applies, but that's the way clang and gcc do it.
|
||||
vshufps(mask, src, dest, dest);
|
||||
}
|
||||
void selectX4(FloatRegister mask, FloatRegister onTrue, FloatRegister onFalse,
|
||||
FloatRegister temp, FloatRegister output);
|
||||
// End unused SIMD.
|
||||
|
||||
void moveFloatAsDouble(Register src, FloatRegister dest) {
|
||||
vmovd(src, dest);
|
||||
vcvtss2sd(dest, dest, dest);
|
||||
|
|
|
|||
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