зеркало из https://github.com/mozilla/gecko-dev.git
Bug 1488726: Implement CPU detection of LZCNT, BMI1, BMI2; r=sunfish
--HG-- extra : rebase_source : 864eea5108ce66909b7bf4499047d40330643cf3 extra : histedit_source : 09dfc073278306dd7b56887e880029a9ab9a3cdd
This commit is contained in:
Benjamin Bouvier
Родитель
edf43f5289
Коммит
bcfda3e9d9
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@ -237,6 +237,9 @@ CPUInfo::SSEVersion CPUInfo::maxEnabledSSEVersion = UnknownSSE;
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bool CPUInfo::avxPresent = false;
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bool CPUInfo::avxEnabled = false;
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bool CPUInfo::popcntPresent = false;
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bool CPUInfo::bmi1Present = false;
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bool CPUInfo::bmi2Present = false;
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bool CPUInfo::lzcntPresent = false;
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bool CPUInfo::needAmdBugWorkaround = false;
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static uintptr_t
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@ -263,95 +266,119 @@ ReadXGETBV()
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return xcr0EAX;
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}
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void
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CPUInfo::SetSSEVersion()
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static void
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ReadCPUInfo(int* flagsEax, int* flagsEbx, int* flagsEcx, int* flagsEdx)
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{
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int flagsEAX = 0;
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int flagsECX = 0;
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int flagsEDX = 0;
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#ifdef _MSC_VER
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int cpuinfo[4];
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__cpuid(cpuinfo, 1);
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flagsEAX = cpuinfo[0];
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flagsECX = cpuinfo[2];
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flagsEDX = cpuinfo[3];
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__cpuid(cpuinfo, *flagsEax);
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*flagsEax = cpuinfo[0];
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*flagsEbx = cpuinfo[1];
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*flagsEcx = cpuinfo[2];
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*flagsEdx = cpuinfo[3];
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#elif defined(__GNUC__)
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// Some older 32-bits processors don't fill the ecx register with cpuid, so
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// clobber it before calling cpuid, so that there's no risk of picking
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// random bits indicating SSE3/SSE4 are present. Also make sure that it's
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// set to 0 as an input for BMI detection on all platforms.
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*flagsEcx = 0;
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# ifdef JS_CODEGEN_X64
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asm (
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"movl $0x1, %%eax;"
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"cpuid;"
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: "=a" (flagsEAX), "=c" (flagsECX), "=d" (flagsEDX)
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:
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: "%ebx"
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: "+a" (*flagsEax), "=b" (*flagsEbx), "+c" (*flagsEcx), "=d" (*flagsEdx)
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);
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# else
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// On x86, preserve ebx. The compiler needs it for PIC mode.
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// Some older processors don't fill the ecx register with cpuid, so clobber
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// it before calling cpuid, so that there's no risk of picking random bits
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// indicating SSE3/SSE4 are present.
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asm (
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"xor %%ecx, %%ecx;"
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"movl $0x1, %%eax;"
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"pushl %%ebx;"
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"mov %%ebx, %%edi;"
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"cpuid;"
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"popl %%ebx;"
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: "=a" (flagsEAX), "=c" (flagsECX), "=d" (flagsEDX)
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:
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:
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"xchg %%edi, %%ebx;"
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: "+a" (*flagsEax), "=D" (*flagsEbx), "+c" (*flagsEcx), "=d" (*flagsEdx)
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);
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# endif
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#else
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# error "Unsupported compiler"
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#endif
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}
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static const int SSEBit = 1 << 25;
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static const int SSE2Bit = 1 << 26;
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static const int SSE3Bit = 1 << 0;
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static const int SSSE3Bit = 1 << 9;
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static const int SSE41Bit = 1 << 19;
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static const int SSE42Bit = 1 << 20;
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void
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CPUInfo::SetSSEVersion()
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{
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int flagsEax = 1;
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int flagsEbx = 0;
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int flagsEcx = 0;
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int flagsEdx = 0;
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ReadCPUInfo(&flagsEax, &flagsEbx, &flagsEcx, &flagsEdx);
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if (flagsECX & SSE42Bit) maxSSEVersion = SSE4_2;
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else if (flagsECX & SSE41Bit) maxSSEVersion = SSE4_1;
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else if (flagsECX & SSSE3Bit) maxSSEVersion = SSSE3;
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else if (flagsECX & SSE3Bit) maxSSEVersion = SSE3;
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else if (flagsEDX & SSE2Bit) maxSSEVersion = SSE2;
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else if (flagsEDX & SSEBit) maxSSEVersion = SSE;
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else maxSSEVersion = NoSSE;
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static constexpr int SSEBit = 1 << 25;
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static constexpr int SSE2Bit = 1 << 26;
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static constexpr int SSE3Bit = 1 << 0;
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static constexpr int SSSE3Bit = 1 << 9;
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static constexpr int SSE41Bit = 1 << 19;
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static constexpr int SSE42Bit = 1 << 20;
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if (flagsEcx & SSE42Bit) {
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maxSSEVersion = SSE4_2;
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} else if (flagsEcx & SSE41Bit) {
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maxSSEVersion = SSE4_1;
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} else if (flagsEcx & SSSE3Bit) {
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maxSSEVersion = SSSE3;
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} else if (flagsEcx & SSE3Bit) {
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maxSSEVersion = SSE3;
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} else if (flagsEdx & SSE2Bit) {
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maxSSEVersion = SSE2;
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} else if (flagsEdx & SSEBit) {
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maxSSEVersion = SSE;
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} else {
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maxSSEVersion = NoSSE;
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}
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if (maxEnabledSSEVersion != UnknownSSE) {
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maxSSEVersion = Min(maxSSEVersion, maxEnabledSSEVersion);
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}
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static const int AVXBit = 1 << 28;
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static const int XSAVEBit = 1 << 27;
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avxPresent = (flagsECX & AVXBit) && (flagsECX & XSAVEBit) && avxEnabled;
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static constexpr int AVXBit = 1 << 28;
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static constexpr int XSAVEBit = 1 << 27;
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avxPresent = (flagsEcx & AVXBit) && (flagsEcx & XSAVEBit) && avxEnabled;
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// If the hardware supports AVX, check whether the OS supports it too.
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if (avxPresent) {
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size_t xcr0EAX = ReadXGETBV();
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static const int xcr0SSEBit = 1 << 1;
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static const int xcr0AVXBit = 1 << 2;
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static constexpr int xcr0SSEBit = 1 << 1;
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static constexpr int xcr0AVXBit = 1 << 2;
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avxPresent = (xcr0EAX & xcr0SSEBit) && (xcr0EAX & xcr0AVXBit);
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}
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// CMOV instruction are supposed to be supported by all CPU which have SSE2
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// enabled. While this might be true, this is not guaranteed by any
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// documentation, nor AMD, nor Intel.
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static const int CMOVBit = 1 << 15;
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MOZ_RELEASE_ASSERT(flagsEDX & CMOVBit,
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static constexpr int CMOVBit = 1 << 15;
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MOZ_RELEASE_ASSERT(flagsEdx & CMOVBit,
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"CMOVcc instruction is not recognized by this CPU.");
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static const int POPCNTBit = 1 << 23;
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popcntPresent = (flagsECX & POPCNTBit);
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static constexpr int POPCNTBit = 1 << 23;
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popcntPresent = (flagsEcx & POPCNTBit);
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// Check if we need to work around an AMD CPU bug (see bug 1281759).
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// We check for family 20 models 0-2. Intel doesn't use family 20 at
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// this point, so this should only match AMD CPUs.
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unsigned family = ((flagsEAX >> 20) & 0xff) + ((flagsEAX >> 8) & 0xf);
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unsigned model = (((flagsEAX >> 16) & 0xf) << 4) + ((flagsEAX >> 4) & 0xf);
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unsigned family = ((flagsEax >> 20) & 0xff) + ((flagsEax >> 8) & 0xf);
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unsigned model = (((flagsEax >> 16) & 0xf) << 4) + ((flagsEax >> 4) & 0xf);
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needAmdBugWorkaround = (family == 20 && model <= 2);
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flagsEax = 0x80000001;
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ReadCPUInfo(&flagsEax, &flagsEbx, &flagsEcx, &flagsEdx);
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static constexpr int LZCNTBit = 1 << 5;
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lzcntPresent = (flagsEcx & LZCNTBit);
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flagsEax = 0x7;
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ReadCPUInfo(&flagsEax, &flagsEbx, &flagsEcx, &flagsEdx);
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static constexpr int BMI1Bit = 1 << 3;
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static constexpr int BMI2Bit = 1 << 8;
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bmi1Present = (flagsEbx & BMI1Bit);
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bmi2Present = bmi1Present && (flagsEbx & BMI2Bit);
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}
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volatile uintptr_t* blackbox = nullptr;
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@ -227,6 +227,9 @@ class CPUInfo
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static bool avxPresent;
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static bool avxEnabled;
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static bool popcntPresent;
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static bool bmi1Present;
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static bool bmi2Present;
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static bool lzcntPresent;
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static bool needAmdBugWorkaround;
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static void SetSSEVersion();
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@ -244,6 +247,9 @@ class CPUInfo
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static bool IsSSE41Present() { return GetSSEVersion() >= SSE4_1; }
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static bool IsSSE42Present() { return GetSSEVersion() >= SSE4_2; }
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static bool IsPOPCNTPresent() { return popcntPresent; }
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static bool IsBMI1Present() { return bmi1Present; }
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static bool IsBMI2Present() { return bmi2Present; }
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static bool IsLZCNTPresent() { return lzcntPresent; }
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static bool NeedAmdBugWorkaround() { return needAmdBugWorkaround; }
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static void SetSSE3Disabled() { maxEnabledSSEVersion = SSE2; avxEnabled = false; }
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@ -1109,6 +1115,9 @@ class AssemblerX86Shared : public AssemblerShared
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static bool HasSSE41() { return CPUInfo::IsSSE41Present(); }
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static bool HasSSE42() { return CPUInfo::IsSSE42Present(); }
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static bool HasPOPCNT() { return CPUInfo::IsPOPCNTPresent(); }
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static bool HasBMI1() { return CPUInfo::IsBMI1Present(); }
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static bool HasBMI2() { return CPUInfo::IsBMI2Present(); }
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static bool HasLZCNT() { return CPUInfo::IsLZCNTPresent(); }
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static bool SupportsFloatingPoint() { return CPUInfo::IsSSE2Present(); }
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static bool SupportsUnalignedAccesses() { return true; }
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static bool SupportsSimd() { return CPUInfo::IsSSE2Present(); }
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@ -177,6 +177,9 @@ CraneliftStaticEnvironment::CraneliftStaticEnvironment()
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hasSse42(Assembler::HasSSE42()),
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hasPopcnt(Assembler::HasPOPCNT()),
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hasAvx(Assembler::HasAVX()),
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hasBmi1(Assembler::HasBMI1()),
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hasBmi2(Assembler::HasBMI2()),
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hasLzcnt(Assembler::HasLZCNT()),
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#else
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hasSse2(false),
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hasSse3(false),
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@ -184,10 +187,10 @@ CraneliftStaticEnvironment::CraneliftStaticEnvironment()
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hasSse42(false),
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hasPopcnt(false),
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hasAvx(false),
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hasBmi1(false),
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hasBmi2(false),
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hasLzcnt(false),
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#endif
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hasBmi1(false), // TODO implement feature detection for bmi1
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hasBmi2(false), // TODO implement feature detection for bmi2
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hasLzcnt(false), // TODO implement feature detection for lzcnt
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staticMemoryBound(
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#ifdef WASM_HUGE_MEMORY
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// In the huge memory configuration, we always reserve the full 4 GB index
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