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Bug 1760349 - Update names and codes for Relaxed SIMD instructions. r=lth 

See https://github.com/WebAssembly/relaxed-simd/pull/66

Differential Revision: https://phabricator.services.mozilla.com/D141522
This commit is contained in:
Yury Delendik 2022-03-21 13:09:34 +00:00
Родитель 94abd3de71
Коммит ccdc66e311
13 изменённых файлов: 120 добавлений и 93 удалений
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38
js/src/jit-test/lib/wasm-binary.js
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@ -116,8 +116,6 @@ const RefFuncCode = 0xd2;
// SIMD opcodes
const V128LoadCode = 0x00;
const V128StoreCode = 0x0b;
// Experimental SIMD opcodes as of August, 2020.
const I32x4DotSI16x8Code = 0xba;
const F32x4CeilCode = 0xd8;
const F32x4FloorCode = 0xd9;
@ -133,23 +131,25 @@ const F64x2PMinCode = 0xf6;
const F64x2PMaxCode = 0xf7;
const V128Load32ZeroCode = 0xfc;
const V128Load64ZeroCode = 0xfd;
const F32x4RelaxedFmaCode = 0xaf;
const F32x4RelaxedFmsCode = 0xb0;
const F64x2RelaxedFmaCode = 0xcf;
const F64x2RelaxedFmsCode = 0xd0;
const F32x4RelaxedMin = 0xb4;
const F32x4RelaxedMax = 0xe2;
const F64x2RelaxedMin = 0xd4;
const F64x2RelaxedMax = 0xee;
const I32x4RelaxedTruncSSatF32x4 = 0xa5;
const I32x4RelaxedTruncUSatF32x4 = 0xa6;
const I32x4RelaxedTruncSatF64x2SZero = 0xc5;
const I32x4RelaxedTruncSatF64x2UZero = 0xc6;
const I8x16RelaxedSwizzle = 0xa2;
const I8x16LaneSelect = 0xb2;
const I16x8LaneSelect = 0xb3;
const I32x4LaneSelect = 0xd2;
const I64x2LaneSelect = 0xd3;
// Relaxed SIMD opcodes.
const I8x16RelaxedSwizzleCode = 0x100;
const I32x4RelaxedTruncSSatF32x4Code = 0x101;
const I32x4RelaxedTruncUSatF32x4Code = 0x102;
const I32x4RelaxedTruncSatF64x2SZeroCode = 0x103;
const I32x4RelaxedTruncSatF64x2UZeroCode = 0x104;
const F32x4RelaxedFmaCode = 0x105;
const F32x4RelaxedFmsCode = 0x106;
const F64x2RelaxedFmaCode = 0x107;
const F64x2RelaxedFmsCode = 0x108;
const I8x16RelaxedLaneSelectCode = 0x109;
const I16x8RelaxedLaneSelectCode = 0x10a;
const I32x4RelaxedLaneSelectCode = 0x10b;
const I64x2RelaxedLaneSelectCode = 0x10c;
const F32x4RelaxedMinCode = 0x10d;
const F32x4RelaxedMaxCode = 0x10e;
const F64x2RelaxedMinCode = 0x10f;
const F64x2RelaxedMaxCode = 0x110;
// SIMD wormhole opcodes.
const WORMHOLE_SELFTEST = 0;

9
js/src/jit-test/tests/wasm/binary.js
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@ -294,12 +294,17 @@ for (let i = 0; i < 256; i++) {
// done about that.
if (!wasmSimdEnabled()) {
for (let i = 0; i < 256; i++) {
for (let i = 0; i < 0x130; i++) {
checkIllegalPrefixed(SimdPrefix, i);
}
} else {
let reservedSimd = [
0x9a, 0xbb, 0xc2,
0x9a, 0xa2, 0xa5, 0xa6, 0xaf, 0xb0, 0xb2, 0xb3, 0xb4, 0xbb,
0xc2, 0xc5, 0xc6, 0xcf, 0xd0, 0xd2, 0xd3, 0xd4, 0xe2, 0xee,
0x111, 0x112, 0x113, 0x114, 0x115, 0x116, 0x117,
0x118, 0x119, 0x11a, 0x11b, 0x11c, 0x11d, 0x11e, 0x11f,
0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127,
0x128, 0x129, 0x12a, 0x12b, 0x12c, 0x12d, 0x12e, 0x12f,
];
for (let i of reservedSimd) {
checkIllegalPrefixed(SimdPrefix, i);

28
js/src/jit-test/tests/wasm/simd/experimental.js
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@ -134,7 +134,7 @@ var ins = wasmValidateAndEval(moduleWithSections([
funcBody({locals:[],
body: [...V128StoreExpr(0, [...V128Load(16),
...V128Load(32),
SimdPrefix, varU32(I8x16RelaxedSwizzle)])]})])]));
SimdPrefix, varU32(I8x16RelaxedSwizzleCode)])]})])]));
var mem = new Uint8Array(ins.exports.mem.buffer);
var test = [1, 4, 3, 7, 123, 0, 8, 222];
set(mem, 16, test);
@ -156,7 +156,7 @@ assertEq(false, WebAssembly.validate(moduleWithSections([
bodySection([
funcBody({locals:[],
body: [...V128StoreExpr(0, [...V128Load(16),
SimdPrefix, varU32(I8x16RelaxedSwizzle)])]})])])));
SimdPrefix, varU32(I8x16RelaxedSwizzleCode)])]})])])));
// Relaxed MIN/MAX, https://github.com/WebAssembly/relaxed-simd/issues/33
@ -172,8 +172,8 @@ var minMaxTests = [
];
for (let k of [4, 2]) {
const minOpcode = k == 4 ? F32x4RelaxedMin : F64x2RelaxedMin;
const maxOpcode = k == 4 ? F32x4RelaxedMax : F64x2RelaxedMax;
const minOpcode = k == 4 ? F32x4RelaxedMinCode : F64x2RelaxedMinCode;
const maxOpcode = k == 4 ? F32x4RelaxedMaxCode : F64x2RelaxedMaxCode;
var ins = wasmValidateAndEval(moduleWithSections([
sigSection([v2vSig]),
@ -238,16 +238,16 @@ var ins = wasmValidateAndEval(moduleWithSections([
bodySection([
funcBody({locals:[],
body: [...V128StoreExpr(0, [...V128Load(16),
SimdPrefix, varU32(I32x4RelaxedTruncSSatF32x4)])]}),
SimdPrefix, varU32(I32x4RelaxedTruncSSatF32x4Code)])]}),
funcBody({locals:[],
body: [...V128StoreExpr(0, [...V128Load(16),
SimdPrefix, varU32(I32x4RelaxedTruncUSatF32x4)])]}),
SimdPrefix, varU32(I32x4RelaxedTruncUSatF32x4Code)])]}),
funcBody({locals:[],
body: [...V128StoreExpr(0, [...V128Load(16),
SimdPrefix, varU32(I32x4RelaxedTruncSatF64x2SZero)])]}),
SimdPrefix, varU32(I32x4RelaxedTruncSatF64x2SZeroCode)])]}),
funcBody({locals:[],
body: [...V128StoreExpr(0, [...V128Load(16),
SimdPrefix, varU32(I32x4RelaxedTruncSatF64x2UZero)])]})])]));
SimdPrefix, varU32(I32x4RelaxedTruncSatF64x2UZeroCode)])]})])]));
var mem = ins.exports.mem.buffer;
set(new Float32Array(mem), 4, [0, 2.3, -3.4, 100000]);
@ -273,8 +273,8 @@ ins.exports.from64u();
var result = get(new Uint32Array(mem), 0, 2);
assertSame(result, [0x90000000, 0]);
for (let op of [I32x4RelaxedTruncSSatF32x4, I32x4RelaxedTruncUSatF32x4,
I32x4RelaxedTruncSatF64x2SZero, I32x4RelaxedTruncSatF64x2UZero]) {
for (let op of [I32x4RelaxedTruncSSatF32x4Code, I32x4RelaxedTruncUSatF32x4Code,
I32x4RelaxedTruncSatF64x2SZeroCode, I32x4RelaxedTruncSatF64x2UZeroCode]) {
assertEq(false, WebAssembly.validate(moduleWithSections([
sigSection([v2vSig]),
declSection([0]),
@ -287,10 +287,10 @@ for (let op of [I32x4RelaxedTruncSSatF32x4, I32x4RelaxedTruncUSatF32x4,
// Relaxed blend / laneselect, https://github.com/WebAssembly/relaxed-simd/issues/17
for (let [k, opcode, AT] of [[1, I8x16LaneSelect, Int8Array],
[2, I16x8LaneSelect, Int16Array],
[4, I32x4LaneSelect, Int32Array],
[8, I64x2LaneSelect, BigInt64Array]]) {
for (let [k, opcode, AT] of [[1, I8x16RelaxedLaneSelectCode, Int8Array],
[2, I16x8RelaxedLaneSelectCode, Int16Array],
[4, I32x4RelaxedLaneSelectCode, Int32Array],
[8, I64x2RelaxedLaneSelectCode, BigInt64Array]]) {
var ins = wasmValidateAndEval(moduleWithSections([
sigSection([v2vSig]),

2
js/src/jit/MIR.cpp
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@ -4966,7 +4966,7 @@ MDefinition* MWasmTernarySimd128::foldsTo(TempAllocator& alloc) {
}
} else if (canRelaxBitselect()) {
return MWasmTernarySimd128::New(alloc, v0(), v1(), v2(),
wasm::SimdOp::I8x16LaneSelect);
wasm::SimdOp::I8x16RelaxedLaneSelect);
}
}
return this;

10
js/src/jit/arm64/CodeGenerator-arm64.cpp
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@ -3042,10 +3042,10 @@ void CodeGenerator::visitWasmTernarySimd128(LWasmTernarySimd128* ins) {
masm.fmsFloat64x2(ToFloatRegister(ins->v1()), ToFloatRegister(ins->v2()),
ToFloatRegister(ins->v0()));
break;
case wasm::SimdOp::I8x16LaneSelect:
case wasm::SimdOp::I16x8LaneSelect:
case wasm::SimdOp::I32x4LaneSelect:
case wasm::SimdOp::I64x2LaneSelect: {
case wasm::SimdOp::I8x16RelaxedLaneSelect:
case wasm::SimdOp::I16x8RelaxedLaneSelect:
case wasm::SimdOp::I32x4RelaxedLaneSelect:
case wasm::SimdOp::I64x2RelaxedLaneSelect: {
FloatRegister lhs = ToFloatRegister(ins->v0());
FloatRegister rhs = ToFloatRegister(ins->v1());
FloatRegister maskDest = ToFloatRegister(ins->v2());
@ -3220,7 +3220,7 @@ void CodeGenerator::visitWasmBinarySimd128(LWasmBinarySimd128* ins) {
case wasm::SimdOp::I8x16Swizzle:
masm.swizzleInt8x16(lhs, rhs, dest);
break;
case wasm::SimdOp::V8x16RelaxedSwizzle:
case wasm::SimdOp::I8x16RelaxedSwizzle:
masm.swizzleInt8x16Relaxed(lhs, rhs, dest);
break;
case wasm::SimdOp::I8x16NarrowI16x8S:

8
js/src/jit/arm64/Lowering-arm64.cpp
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@ -1024,10 +1024,10 @@ void LIRGenerator::visitWasmTernarySimd128(MWasmTernarySimd128* ins) {
defineReuseInput(lir, ins, LWasmTernarySimd128::V0);
break;
}
case wasm::SimdOp::I8x16LaneSelect:
case wasm::SimdOp::I16x8LaneSelect:
case wasm::SimdOp::I32x4LaneSelect:
case wasm::SimdOp::I64x2LaneSelect: {
case wasm::SimdOp::I8x16RelaxedLaneSelect:
case wasm::SimdOp::I16x8RelaxedLaneSelect:
case wasm::SimdOp::I32x4RelaxedLaneSelect:
case wasm::SimdOp::I64x2RelaxedLaneSelect: {
auto* lir = new (alloc()) LWasmTernarySimd128(
ins->simdOp(), useRegister(ins->v0()), useRegister(ins->v1()),
useRegisterAtStart(ins->v2()));

10
js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp
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@ -2289,10 +2289,10 @@ void CodeGenerator::visitWasmTernarySimd128(LWasmTernarySimd128* ins) {
masm.fmsFloat64x2(ToFloatRegister(ins->v1()), ToFloatRegister(ins->v2()),
ToFloatRegister(ins->v0()));
break;
case wasm::SimdOp::I8x16LaneSelect:
case wasm::SimdOp::I16x8LaneSelect:
case wasm::SimdOp::I32x4LaneSelect:
case wasm::SimdOp::I64x2LaneSelect: {
case wasm::SimdOp::I8x16RelaxedLaneSelect:
case wasm::SimdOp::I16x8RelaxedLaneSelect:
case wasm::SimdOp::I32x4RelaxedLaneSelect:
case wasm::SimdOp::I64x2RelaxedLaneSelect: {
FloatRegister lhs = ToFloatRegister(ins->v0());
FloatRegister rhs = ToFloatRegister(ins->v1());
FloatRegister mask = ToFloatRegister(ins->v2());
@ -2469,7 +2469,7 @@ void CodeGenerator::visitWasmBinarySimd128(LWasmBinarySimd128* ins) {
case wasm::SimdOp::I8x16Swizzle:
masm.swizzleInt8x16(lhs, rhs, dest);
break;
case wasm::SimdOp::V8x16RelaxedSwizzle:
case wasm::SimdOp::I8x16RelaxedSwizzle:
masm.swizzleInt8x16Relaxed(lhs, rhs, dest);
break;
case wasm::SimdOp::I8x16NarrowI16x8S:

10
js/src/jit/x86-shared/Lowering-x86-shared.cpp
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@ -842,10 +842,10 @@ void LIRGenerator::visitWasmTernarySimd128(MWasmTernarySimd128* ins) {
defineReuseInput(lir, ins, LWasmTernarySimd128::V0);
break;
}
case wasm::SimdOp::I8x16LaneSelect:
case wasm::SimdOp::I16x8LaneSelect:
case wasm::SimdOp::I32x4LaneSelect:
case wasm::SimdOp::I64x2LaneSelect: {
case wasm::SimdOp::I8x16RelaxedLaneSelect:
case wasm::SimdOp::I16x8RelaxedLaneSelect:
case wasm::SimdOp::I32x4RelaxedLaneSelect:
case wasm::SimdOp::I64x2RelaxedLaneSelect: {
if (Assembler::HasAVX()) {
auto* lir = new (alloc()) LWasmTernarySimd128(
ins->simdOp(), useRegisterAtStart(ins->v0()),
@ -1047,7 +1047,7 @@ void LIRGenerator::visitWasmBinarySimd128(MWasmBinarySimd128* ins) {
case wasm::SimdOp::F64x2PMin:
case wasm::SimdOp::F64x2PMax:
case wasm::SimdOp::I8x16Swizzle:
case wasm::SimdOp::V8x16RelaxedSwizzle:
case wasm::SimdOp::I8x16RelaxedSwizzle:
case wasm::SimdOp::I8x16Eq:
case wasm::SimdOp::I8x16Ne:
case wasm::SimdOp::I8x16GtS:

10
js/src/wasm/WasmBaselineCompile.cpp
Просмотреть файл

@ -9429,10 +9429,10 @@ bool BaseCompiler::emitBody() {
}
CHECK_NEXT(dispatchTernary1(RelaxedFmsF64x2, ValType::V128));
break;
case uint32_t(SimdOp::I8x16LaneSelect):
case uint32_t(SimdOp::I16x8LaneSelect):
case uint32_t(SimdOp::I32x4LaneSelect):
case uint32_t(SimdOp::I64x2LaneSelect):
case uint32_t(SimdOp::I8x16RelaxedLaneSelect):
case uint32_t(SimdOp::I16x8RelaxedLaneSelect):
case uint32_t(SimdOp::I32x4RelaxedLaneSelect):
case uint32_t(SimdOp::I64x2RelaxedLaneSelect):
if (!moduleEnv_.v128RelaxedEnabled()) {
return iter_.unrecognizedOpcode(&op);
}
@ -9477,7 +9477,7 @@ bool BaseCompiler::emitBody() {
return iter_.unrecognizedOpcode(&op);
}
CHECK_NEXT(dispatchVectorUnary(RelaxedConvertF64x2ToUI32x4));
case uint32_t(SimdOp::V8x16RelaxedSwizzle):
case uint32_t(SimdOp::I8x16RelaxedSwizzle):
if (!moduleEnv_.v128RelaxedEnabled()) {
return iter_.unrecognizedOpcode(&op);
}

58
js/src/wasm/WasmConstants.h
Просмотреть файл

@ -664,11 +664,11 @@ enum class SimdOp {
I16x8ExtmulHighI8x16U = 0x9f,
I32x4Abs = 0xa0,
I32x4Neg = 0xa1,
V8x16RelaxedSwizzle = 0xa2,
// Unused = 0xa2
I32x4AllTrue = 0xa3,
I32x4Bitmask = 0xa4,
I32x4RelaxedTruncSSatF32x4 = 0xa5,
I32x4RelaxedTruncUSatF32x4 = 0xa6,
// Unused = 0xa5
// Unused = 0xa6
I32x4ExtendLowI16x8S = 0xa7,
I32x4ExtendHighI16x8S = 0xa8,
I32x4ExtendLowI16x8U = 0xa9,
@ -677,12 +677,12 @@ enum class SimdOp {
I32x4ShrS = 0xac,
I32x4ShrU = 0xad,
I32x4Add = 0xae,
F32x4RelaxedFma = 0xaf,
F32x4RelaxedFms = 0xb0,
// Unused = 0xaf
// Unused = 0xb0
I32x4Sub = 0xb1,
I8x16LaneSelect = 0xb2,
I16x8LaneSelect = 0xb3,
F32x4RelaxedMin = 0xb4,
// Unused = 0xb2
// Unused = 0xb3
// Unused = 0xb4
I32x4Mul = 0xb5,
I32x4MinS = 0xb6,
I32x4MinU = 0xb7,
@ -699,8 +699,8 @@ enum class SimdOp {
// AnyTrue = 0xc2
I64x2AllTrue = 0xc3,
I64x2Bitmask = 0xc4,
I32x4RelaxedTruncSatF64x2SZero = 0xc5,
I32x4RelaxedTruncSatF64x2UZero = 0xc6,
// Unused = 0xc5
// Unused = 0xc6
I64x2ExtendLowI32x4S = 0xc7,
I64x2ExtendHighI32x4S = 0xc8,
I64x2ExtendLowI32x4U = 0xc9,
@ -709,12 +709,12 @@ enum class SimdOp {
I64x2ShrS = 0xcc,
I64x2ShrU = 0xcd,
I64x2Add = 0xce,
F64x2RelaxedFma = 0xcf,
F64x2RelaxedFms = 0xd0,
// Unused = 0xcf
// Unused = 0xd0
I64x2Sub = 0xd1,
I32x4LaneSelect = 0xd2,
I64x2LaneSelect = 0xd3,
F64x2RelaxedMin = 0xd4,
// Unused = 0xd2
// Unused = 0xd3
// Unused = 0xd4
I64x2Mul = 0xd5,
I64x2Eq = 0xd6,
I64x2Ne = 0xd7,
@ -728,7 +728,7 @@ enum class SimdOp {
I64x2ExtmulHighI32x4U = 0xdf,
F32x4Abs = 0xe0,
F32x4Neg = 0xe1,
F32x4RelaxedMax = 0xe2,
// Unused = 0xe2
F32x4Sqrt = 0xe3,
F32x4Add = 0xe4,
F32x4Sub = 0xe5,
@ -740,7 +740,7 @@ enum class SimdOp {
F32x4PMax = 0xeb,
F64x2Abs = 0xec,
F64x2Neg = 0xed,
F64x2RelaxedMax = 0xee,
// Unused = 0xee
F64x2Sqrt = 0xef,
F64x2Add = 0xf0,
F64x2Sub = 0xf1,
@ -758,7 +758,29 @@ enum class SimdOp {
I32x4TruncSatF64x2UZero = 0xfd,
F64x2ConvertLowI32x4S = 0xfe,
F64x2ConvertLowI32x4U = 0xff,
// Unused = 0x100 and up
I8x16RelaxedSwizzle = 0x100,
I32x4RelaxedTruncSSatF32x4 = 0x101,
I32x4RelaxedTruncUSatF32x4 = 0x102,
I32x4RelaxedTruncSatF64x2SZero = 0x103,
I32x4RelaxedTruncSatF64x2UZero = 0x104,
F32x4RelaxedFma = 0x105,
F32x4RelaxedFms = 0x106,
F64x2RelaxedFma = 0x107,
F64x2RelaxedFms = 0x108,
I8x16RelaxedLaneSelect = 0x109,
I16x8RelaxedLaneSelect = 0x10a,
I32x4RelaxedLaneSelect = 0x10b,
I64x2RelaxedLaneSelect = 0x10c,
F32x4RelaxedMin = 0x10d,
F32x4RelaxedMax = 0x10e,
F64x2RelaxedMin = 0x10f,
F64x2RelaxedMax = 0x110,
// I16x8RelaxedQ15MulrS = 0x111
// Dot product = 0x112-0x115
// bfloat16 dot product = 0x116
// Reserved for Relaxed SIMD = 0x117-0x12f
// Unused = 0x130 and up
// Mozilla extensions, highly experimental and platform-specific
#ifdef ENABLE_WASM_SIMD_WORMHOLE

10
js/src/wasm/WasmIonCompile.cpp
Просмотреть файл

@ -6493,10 +6493,10 @@ static bool EmitBodyExprs(FunctionCompiler& f) {
case uint32_t(SimdOp::F32x4RelaxedFms):
case uint32_t(SimdOp::F64x2RelaxedFma):
case uint32_t(SimdOp::F64x2RelaxedFms):
case uint32_t(SimdOp::I8x16LaneSelect):
case uint32_t(SimdOp::I16x8LaneSelect):
case uint32_t(SimdOp::I32x4LaneSelect):
case uint32_t(SimdOp::I64x2LaneSelect): {
case uint32_t(SimdOp::I8x16RelaxedLaneSelect):
case uint32_t(SimdOp::I16x8RelaxedLaneSelect):
case uint32_t(SimdOp::I32x4RelaxedLaneSelect):
case uint32_t(SimdOp::I64x2RelaxedLaneSelect): {
if (!f.moduleEnv().v128RelaxedEnabled()) {
return f.iter().unrecognizedOpcode(&op);
}
@ -6520,7 +6520,7 @@ static bool EmitBodyExprs(FunctionCompiler& f) {
}
CHECK(EmitUnarySimd128(f, SimdOp(op.b1)));
}
case uint32_t(SimdOp::V8x16RelaxedSwizzle): {
case uint32_t(SimdOp::I8x16RelaxedSwizzle): {
if (!f.moduleEnv().v128RelaxedEnabled()) {
return f.iter().unrecognizedOpcode(&op);
}

10
js/src/wasm/WasmOpIter.cpp
Просмотреть файл

@ -498,7 +498,7 @@ OpKind wasm::Classify(OpBytes op) {
case SimdOp::F32x4RelaxedMax:
case SimdOp::F64x2RelaxedMin:
case SimdOp::F64x2RelaxedMax:
case SimdOp::V8x16RelaxedSwizzle:
case SimdOp::I8x16RelaxedSwizzle:
WASM_SIMD_OP(OpKind::Binary);
case SimdOp::I8x16Neg:
case SimdOp::I16x8Neg:
@ -604,10 +604,10 @@ OpKind wasm::Classify(OpBytes op) {
case SimdOp::F32x4RelaxedFms:
case SimdOp::F64x2RelaxedFma:
case SimdOp::F64x2RelaxedFms:
case SimdOp::I8x16LaneSelect:
case SimdOp::I16x8LaneSelect:
case SimdOp::I32x4LaneSelect:
case SimdOp::I64x2LaneSelect:
case SimdOp::I8x16RelaxedLaneSelect:
case SimdOp::I16x8RelaxedLaneSelect:
case SimdOp::I32x4RelaxedLaneSelect:
case SimdOp::I64x2RelaxedLaneSelect:
WASM_SIMD_OP(OpKind::Ternary);
# ifdef ENABLE_WASM_SIMD_WORMHOLE
case SimdOp::MozWHSELFTEST:

10
js/src/wasm/WasmValidate.cpp
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@ -1011,10 +1011,10 @@ static bool DecodeFunctionBodyExprs(const ModuleEnvironment& env,
case uint32_t(SimdOp::F32x4RelaxedFms):
case uint32_t(SimdOp::F64x2RelaxedFma):
case uint32_t(SimdOp::F64x2RelaxedFms):
case uint32_t(SimdOp::I8x16LaneSelect):
case uint32_t(SimdOp::I16x8LaneSelect):
case uint32_t(SimdOp::I32x4LaneSelect):
case uint32_t(SimdOp::I64x2LaneSelect): {
case uint32_t(SimdOp::I8x16RelaxedLaneSelect):
case uint32_t(SimdOp::I16x8RelaxedLaneSelect):
case uint32_t(SimdOp::I32x4RelaxedLaneSelect):
case uint32_t(SimdOp::I64x2RelaxedLaneSelect): {
if (!env.v128RelaxedEnabled()) {
return iter.unrecognizedOpcode(&op);
}
@ -1039,7 +1039,7 @@ static bool DecodeFunctionBodyExprs(const ModuleEnvironment& env,
}
CHECK(iter.readUnary(ValType::V128, &nothing));
}
case uint32_t(SimdOp::V8x16RelaxedSwizzle): {
case uint32_t(SimdOp::I8x16RelaxedSwizzle): {
if (!env.v128RelaxedEnabled()) {
return iter.unrecognizedOpcode(&op);
}