Bug 875916 - Fix some x86 assembly spew bugs. Also, change the order of operands in psrlq and psllq to be consistent with the operand ordering used in the rest of the file. r=sstangl

js/src/assembler/assembler/X86Assembler.h

@@ -1697,7 +1697,7 @@ public:
     
     JmpSrc movl_ripr(RegisterID dst)
     {
-        spew("movl     \?(%%rip), %s",
+        spew("movl       \?(%%rip), %s",
              nameIReg(dst));
         m_formatter.oneByteRipOp(OP_MOV_GvEv, (RegisterID)dst, 0);
         return JmpSrc(m_formatter.size());
@@ -1705,7 +1705,7 @@ public:
 
     JmpSrc movl_rrip(RegisterID src)
     {
-        spew("movl     %s, \?(%%rip)",
+        spew("movl       %s, \?(%%rip)",
              nameIReg(src));
         m_formatter.oneByteRipOp(OP_MOV_EvGv, (RegisterID)src, 0);
         return JmpSrc(m_formatter.size());
@@ -1713,7 +1713,7 @@ public:
 
     JmpSrc movq_ripr(RegisterID dst)
     {
-        spew("movl     \?(%%rip), %s",
+        spew("movl       \?(%%rip), %s",
              nameIReg(dst));
         m_formatter.oneByteRipOp64(OP_MOV_GvEv, dst, 0);
         return JmpSrc(m_formatter.size());
@@ -1949,13 +1949,13 @@ public:
     
     void jmp_m(int offset, RegisterID base)
     {
-        spew("jmp       *%d(%s)",
+        spew("jmp        *%d(%s)",
              offset, nameIReg(base));
         m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_JMPN, base, offset);
     }
 
     void jmp_m(int offset, RegisterID base, RegisterID index, int scale) {
-        spew("jmp       *%d(%s,%s,%d)",
+        spew("jmp        *%d(%s,%s,%d)",
              offset, nameIReg(base), nameIReg(index), 1<<scale);
         m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_JMPN, base, index, scale, offset);
     }
@@ -2127,7 +2127,7 @@ public:
 
     void cvtsd2ss_rr(XMMRegisterID src, XMMRegisterID dst)
     {
-        spew("cvtss2sd   %s, %s",
+        spew("cvtsd2ss   %s, %s",
              nameFPReg(src), nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_F2);
         m_formatter.twoByteOp(OP2_CVTSD2SS_VsdEd, (RegisterID)dst, (RegisterID)src);
@@ -2210,28 +2210,28 @@ public:
         m_formatter.twoByteOp(OP2_MOVD_VdEd, (RegisterID)dst, src);
     }
 
-    void psrldq_rr(XMMRegisterID dest, int shift)
+    void psrldq_ir(int shift, XMMRegisterID dest)
     {
-        spew("psrldq     %s, %d",
-             nameFPReg(dest), shift);
+        spew("psrldq      $%d, %s",
+             shift, nameFPReg(dest));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PSRLDQ_Vd, (RegisterID)3, (RegisterID)dest);
         m_formatter.immediate8(shift);
     }
 
-    void psllq_rr(XMMRegisterID dest, int shift)
+    void psllq_ir(int shift, XMMRegisterID dest)
     {
-        spew("psllq     %s, %d",
-             nameFPReg(dest), shift);
+        spew("psllq      $%d, %s",
+             shift, nameFPReg(dest));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PSRLDQ_Vd, (RegisterID)6, (RegisterID)dest);
         m_formatter.immediate8(shift);
     }
 
-    void psrlq_rr(XMMRegisterID dest, int shift)
+    void psrlq_ir(int shift, XMMRegisterID dest)
     {
-        spew("psrlq     %s, %d",
-             nameFPReg(dest), shift);
+        spew("psrlq      $%d, %s",
+             shift, nameFPReg(dest));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PSRLDQ_Vd, (RegisterID)2, (RegisterID)dest);
         m_formatter.immediate8(shift);

js/src/ion/shared/Assembler-x86-shared.h

@@ -1100,15 +1100,15 @@ class AssemblerX86Shared
     }
     void psrldq(Imm32 shift, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
-        masm.psrldq_rr(dest.code(), shift.value);
+        masm.psrldq_ir(shift.value, dest.code());
     }
     void psllq(Imm32 shift, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
-        masm.psllq_rr(dest.code(), shift.value);
+        masm.psllq_ir(shift.value, dest.code());
     }
     void psrlq(Imm32 shift, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
-        masm.psrlq_rr(dest.code(), shift.value);
+        masm.psrlq_ir(shift.value, dest.code());
     }
 
     void cvtsi2sd(const Operand &src, const FloatRegister &dest) {