Bug 875916 - Fix some x86 assembly spew bugs. Also, change the order of operands in psrlq and psllq to be consistent with the operand ordering used in the rest of the file. r=sstangl

This commit is contained in:
Dan Gohman 2013-06-05 17:10:47 -07:00
Родитель c2ded3e0bd
Коммит d2d2af3c55
2 изменённых файлов: 18 добавлений и 18 удалений

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@ -2127,7 +2127,7 @@ public:
void cvtsd2ss_rr(XMMRegisterID src, XMMRegisterID dst)
{
spew("cvtss2sd %s, %s",
spew("cvtsd2ss %s, %s",
nameFPReg(src), nameFPReg(dst));
m_formatter.prefix(PRE_SSE_F2);
m_formatter.twoByteOp(OP2_CVTSD2SS_VsdEd, (RegisterID)dst, (RegisterID)src);
@ -2210,28 +2210,28 @@ public:
m_formatter.twoByteOp(OP2_MOVD_VdEd, (RegisterID)dst, src);
}
void psrldq_rr(XMMRegisterID dest, int shift)
void psrldq_ir(int shift, XMMRegisterID dest)
{
spew("psrldq %s, %d",
nameFPReg(dest), shift);
spew("psrldq $%d, %s",
shift, nameFPReg(dest));
m_formatter.prefix(PRE_SSE_66);
m_formatter.twoByteOp(OP2_PSRLDQ_Vd, (RegisterID)3, (RegisterID)dest);
m_formatter.immediate8(shift);
}
void psllq_rr(XMMRegisterID dest, int shift)
void psllq_ir(int shift, XMMRegisterID dest)
{
spew("psllq %s, %d",
nameFPReg(dest), shift);
spew("psllq $%d, %s",
shift, nameFPReg(dest));
m_formatter.prefix(PRE_SSE_66);
m_formatter.twoByteOp(OP2_PSRLDQ_Vd, (RegisterID)6, (RegisterID)dest);
m_formatter.immediate8(shift);
}
void psrlq_rr(XMMRegisterID dest, int shift)
void psrlq_ir(int shift, XMMRegisterID dest)
{
spew("psrlq %s, %d",
nameFPReg(dest), shift);
spew("psrlq $%d, %s",
shift, nameFPReg(dest));
m_formatter.prefix(PRE_SSE_66);
m_formatter.twoByteOp(OP2_PSRLDQ_Vd, (RegisterID)2, (RegisterID)dest);
m_formatter.immediate8(shift);

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@ -1100,15 +1100,15 @@ class AssemblerX86Shared
}
void psrldq(Imm32 shift, const FloatRegister &dest) {
JS_ASSERT(HasSSE2());
masm.psrldq_rr(dest.code(), shift.value);
masm.psrldq_ir(shift.value, dest.code());
}
void psllq(Imm32 shift, const FloatRegister &dest) {
JS_ASSERT(HasSSE2());
masm.psllq_rr(dest.code(), shift.value);
masm.psllq_ir(shift.value, dest.code());
}
void psrlq(Imm32 shift, const FloatRegister &dest) {
JS_ASSERT(HasSSE2());
masm.psrlq_rr(dest.code(), shift.value);
masm.psrlq_ir(shift.value, dest.code());
}
void cvtsi2sd(const Operand &src, const FloatRegister &dest) {