зеркало из https://github.com/mozilla/gecko-dev.git
Bug 972836 - IonMonkey MIPS: Add odd float registers to the enum, but don't allocate them yet. r=froydnj,nbp
This commit is contained in:
Branislav Rankov
Родитель
17f55bc6ed
Коммит
d5b60b3e5d
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@ -113,7 +113,7 @@ class Registers
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return Names[code];
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}
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static const char *GetName(uint32_t i) {
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MOZ_ASSERT(i < Total);
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JS_ASSERT(i < Total);
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return GetName(Code(i));
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}
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@ -191,38 +191,62 @@ class Registers
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typedef uint32_t PackedRegisterMask;
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// MIPS32 uses pairs of even and odd float registers as double precision
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// registers. Example: f0 (double) is composed of f0 and f1 (single).
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// This port only uses even registers to avoid allocation problems.
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// MIPS32 can have two types of floating-point coprocessors:
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// - 32 bit floating-point coprocessor - In this case, there are 32 single
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// precision registers and pairs of even and odd float registers are used as
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// double precision registers. Example: f0 (double) is composed of
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// f0 and f1 (single).
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// - 64 bit floating-point coprocessor - In this case, there are 32 double
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// precision register which can also be used as single precision registers.
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// When using O32 ABI, floating-point coprocessor is 32 bit
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// When using N32 ABI, floating-point coprocessor is 64 bit.
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class FloatRegisters
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{
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public:
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enum FPRegisterID {
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f0 = 0, // f0, f2 - Return values
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f0 = 0,
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f1,
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f2,
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f4, // f4 - f10, f16, f18 - Temporaries
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f3,
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f4,
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f5,
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f6,
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f7,
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f8,
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f9,
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f10,
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f12, // f12, f14 - Arguments
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f11,
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f12,
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f13,
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f14,
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f15,
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f16,
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f17,
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f18,
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f20, // f20 - f30 - Saved registers
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f19,
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f20,
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f21,
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f22,
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f23,
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f24,
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f25,
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f26,
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f27,
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f28,
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f29,
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f30,
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f31,
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invalid_freg
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};
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typedef FPRegisterID Code;
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static const char *GetName(Code code) {
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static const char * const Names[] = { "f0", "f2", "f4", "f6",
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"f8", "f10", "f12", "f14",
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"f16", "f18", "f20", "f22",
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"f24", "f26", "f28", "f30"};
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static const char * const Names[] = { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13",
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"f14", "f15", "f16", "f17", "f18", "f19",
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"f20", "f21", "f22", "f23", "f24", "f25",
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"f26", "f27", "f28", "f29", "f30", "f31"};
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return Names[code];
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}
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static const char *GetName(uint32_t i) {
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@ -234,10 +258,12 @@ class FloatRegisters
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static const Code Invalid = invalid_freg;
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static const uint32_t Total = 16;
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static const uint32_t Total = 32;
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// :TODO: (Bug 972836) // Fix this once odd regs can be used as float32
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// only. For now we don't allocate odd regs for O32 ABI.
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static const uint32_t Allocatable = 14;
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static const uint32_t AllMask = 0xffff;
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static const uint32_t AllMask = 0xffffffff;
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static const uint32_t VolatileMask =
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(1 << FloatRegisters::f0) |
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@ -260,10 +286,28 @@ class FloatRegisters
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static const uint32_t WrapperMask = VolatileMask;
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// f18 and f16 are MIPS scratch float registers.
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// :TODO: (Bug 972836) // Fix this once odd regs can be used as float32
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// only. For now we don't allocate odd regs for O32 ABI.
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static const uint32_t NonAllocatableMask =
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(1 << f16) |
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(1 << f18);
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(1 << FloatRegisters::f1) |
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(1 << FloatRegisters::f3) |
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(1 << FloatRegisters::f5) |
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(1 << FloatRegisters::f7) |
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(1 << FloatRegisters::f9) |
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(1 << FloatRegisters::f11) |
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(1 << FloatRegisters::f13) |
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(1 << FloatRegisters::f15) |
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(1 << FloatRegisters::f17) |
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(1 << FloatRegisters::f19) |
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(1 << FloatRegisters::f21) |
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(1 << FloatRegisters::f23) |
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(1 << FloatRegisters::f25) |
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(1 << FloatRegisters::f27) |
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(1 << FloatRegisters::f29) |
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(1 << FloatRegisters::f31) |
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// f18 and f16 are MIPS scratch float registers.
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(1 << FloatRegisters::f16) |
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(1 << FloatRegisters::f18);
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// Registers that can be allocated without being saved, generally.
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static const uint32_t TempMask = VolatileMask & ~NonAllocatableMask;
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@ -56,16 +56,7 @@ uint32_t
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js::jit::RT(FloatRegister r)
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{
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JS_ASSERT(r.code() < FloatRegisters::Total);
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return (2 * r.code()) << RTShift;
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}
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// Use to code odd float registers.
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// :TODO: Bug 972836, It will be removed once we can use odd regs.
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uint32_t
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js::jit::RT(uint32_t regCode)
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{
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JS_ASSERT((regCode & ~RegMask) == 0);
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return regCode << RTShift;
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return r.code() << RTShift;
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}
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uint32_t
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@ -79,16 +70,7 @@ uint32_t
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js::jit::RD(FloatRegister r)
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{
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JS_ASSERT(r.code() < FloatRegisters::Total);
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return (2 * r.code()) << RDShift;
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}
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// Use to code odd float registers.
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// :TODO: Bug 972836, It will be removed once we can use odd regs.
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uint32_t
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js::jit::RD(uint32_t regCode)
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{
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JS_ASSERT((regCode & ~RegMask) == 0);
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return regCode << RDShift;
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return r.code() << RDShift;
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}
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uint32_t
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@ -102,7 +84,7 @@ uint32_t
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js::jit::SA(FloatRegister r)
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{
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JS_ASSERT(r.code() < FloatRegisters::Total);
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return (2 * r.code()) << SAShift;
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return r.code() << SAShift;
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}
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Register
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@ -973,39 +955,6 @@ Assembler::as_mfc1(Register rt, FloatRegister fs)
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return writeInst(InstReg(op_cop1, rs_mfc1, rt, fs).encode());
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}
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// :TODO: Bug 972836, Remove _Odd functions once we can use odd regs.
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BufferOffset
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Assembler::as_ls_Odd(FloatRegister fd, Register base, int32_t off)
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{
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JS_ASSERT(Imm16::isInSignedRange(off));
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// Hardcoded because it will be removed once we can use odd regs.
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return writeInst(op_lwc1 | RS(base) | RT(fd.code() * 2 + 1) | Imm16(off).encode());
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}
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BufferOffset
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Assembler::as_ss_Odd(FloatRegister fd, Register base, int32_t off)
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{
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JS_ASSERT(Imm16::isInSignedRange(off));
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// Hardcoded because it will be removed once we can use odd regs.
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return writeInst(op_swc1 | RS(base) | RT(fd.code() * 2 + 1) | Imm16(off).encode());
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}
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BufferOffset
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Assembler::as_mtc1_Odd(Register rt, FloatRegister fs)
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{
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// Hardcoded because it will be removed once we can use odd regs.
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return writeInst(op_cop1 | rs_mtc1 | RT(rt) | RD(fs.code() * 2 + 1));
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}
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BufferOffset
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Assembler::as_mfc1_Odd(Register rt, FloatRegister fs)
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{
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// Hardcoded because it will be removed once we can use odd regs.
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return writeInst(op_cop1 | rs_mfc1 | RT(rt) | RD(fs.code() * 2 + 1));
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}
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// FP convert instructions
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BufferOffset
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Assembler::as_ceilws(FloatRegister fd, FloatRegister fs)
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@ -861,16 +861,14 @@ class Assembler
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BufferOffset as_mfc1(Register rt, FloatRegister fs);
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protected:
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// These instructions should only be used to access the odd part of
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// 64-bit register pair. Do not use odd registers as 32-bit registers.
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// :TODO: Bug 972836, Remove _Odd functions once we can use odd regs.
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BufferOffset as_ls_Odd(FloatRegister fd, Register base, int32_t off);
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BufferOffset as_ss_Odd(FloatRegister fd, Register base, int32_t off);
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BufferOffset as_mtc1_Odd(Register rt, FloatRegister fs);
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public:
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// Made public because CodeGenerator uses it to check for -0
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BufferOffset as_mfc1_Odd(Register rt, FloatRegister fs);
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// This is used to access the odd regiter form the pair of single
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// precision registers that make one double register.
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FloatRegister getOddPair(FloatRegister reg) {
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JS_ASSERT(reg.code() % 2 == 0);
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return FloatRegister::FromCode(reg.code() + 1);
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}
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public:
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// FP convert instructions
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BufferOffset as_ceilws(FloatRegister fd, FloatRegister fs);
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BufferOffset as_floorws(FloatRegister fd, FloatRegister fs);
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@ -114,7 +114,7 @@ MacroAssemblerMIPS::convertDoubleToInt32(const FloatRegister &src, const Registe
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// Test and bail for -0.0, when integer result is 0
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// Move the top word of the double into the output reg, if it is
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// non-zero, then the original value was -0.0
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as_mfc1_Odd(dest, src);
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moveFromDoubleHi(src, dest);
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ma_b(dest, Imm32(INT32_MIN), fail, Assembler::Equal);
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bind(¬Zero);
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}
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@ -141,7 +141,7 @@ MacroAssemblerMIPS::convertFloat32ToInt32(const FloatRegister &src, const Regist
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// Test and bail for -0.0, when integer result is 0
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// Move the top word of the double into the output reg,
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// if it is non-zero, then the original value was -0.0
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as_mfc1_Odd(dest, src);
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moveFromDoubleHi(src, dest);
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ma_b(dest, Imm32(INT32_MIN), fail, Assembler::Equal);
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bind(¬Zero);
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}
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@ -1296,7 +1296,7 @@ MacroAssemblerMIPS::ma_lis(FloatRegister dest, float value)
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Imm32 imm(mozilla::BitwiseCast<uint32_t>(value));
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ma_li(ScratchRegister, imm);
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as_mtc1(ScratchRegister, dest);
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moveToFloat32(ScratchRegister, dest);
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}
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void
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@ -1310,41 +1310,41 @@ MacroAssemblerMIPS::ma_lid(FloatRegister dest, double value)
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// put hi part of 64 bit value into the odd register
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if (intStruct.hi == 0) {
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as_mtc1_Odd(zero, dest);
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moveToDoubleHi(zero, dest);
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} else {
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ma_li(ScratchRegister, Imm32(intStruct.hi));
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as_mtc1_Odd(ScratchRegister, dest);
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moveToDoubleHi(ScratchRegister, dest);
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}
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// put low part of 64 bit value into the even register
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if (intStruct.lo == 0) {
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as_mtc1(zero, dest);
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moveToDoubleLo(zero, dest);
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} else {
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ma_li(ScratchRegister, Imm32(intStruct.lo));
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as_mtc1(ScratchRegister, dest);
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moveToDoubleLo(ScratchRegister, dest);
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}
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}
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void
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MacroAssemblerMIPS::ma_liNegZero(FloatRegister dest)
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{
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as_mtc1(zero, dest);
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moveToDoubleLo(zero, dest);
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ma_li(ScratchRegister, Imm32(INT_MIN));
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as_mtc1_Odd(ScratchRegister, dest);
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moveToDoubleHi(ScratchRegister, dest);
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}
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void
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MacroAssemblerMIPS::ma_mv(FloatRegister src, ValueOperand dest)
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{
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as_mfc1(dest.payloadReg(), src);
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as_mfc1_Odd(dest.typeReg(), src);
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moveFromDoubleLo(src, dest.payloadReg());
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moveFromDoubleHi(src, dest.typeReg());
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}
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void
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MacroAssemblerMIPS::ma_mv(ValueOperand src, FloatRegister dest)
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{
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as_mtc1(src.payloadReg(), dest);
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as_mtc1_Odd(src.typeReg(), dest);
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moveToDoubleLo(src.payloadReg(), dest);
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moveToDoubleHi(src.typeReg(), dest);
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}
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void
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@ -1369,12 +1369,12 @@ MacroAssemblerMIPS::ma_ld(FloatRegister ft, Address address)
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int32_t off2 = address.offset + TAG_OFFSET;
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if (Imm16::isInSignedRange(address.offset) && Imm16::isInSignedRange(off2)) {
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as_ls(ft, address.base, Imm16(address.offset).encode());
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as_ls_Odd(ft, address.base, Imm16(off2).encode());
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as_ls(getOddPair(ft), address.base, Imm16(off2).encode());
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} else {
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ma_li(ScratchRegister, Imm32(address.offset));
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as_addu(ScratchRegister, address.base, ScratchRegister);
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as_ls(ft, ScratchRegister, PAYLOAD_OFFSET);
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as_ls_Odd(ft, ScratchRegister, TAG_OFFSET);
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as_ls(getOddPair(ft), ScratchRegister, TAG_OFFSET);
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}
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}
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@ -1384,12 +1384,12 @@ MacroAssemblerMIPS::ma_sd(FloatRegister ft, Address address)
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int32_t off2 = address.offset + TAG_OFFSET;
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if (Imm16::isInSignedRange(address.offset) && Imm16::isInSignedRange(off2)) {
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as_ss(ft, address.base, Imm16(address.offset).encode());
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as_ss_Odd(ft, address.base, Imm16(off2).encode());
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as_ss(getOddPair(ft), address.base, Imm16(off2).encode());
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} else {
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ma_li(ScratchRegister, Imm32(address.offset));
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as_addu(ScratchRegister, address.base, ScratchRegister);
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as_ss(ft, ScratchRegister, PAYLOAD_OFFSET);
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as_ss_Odd(ft, ScratchRegister, TAG_OFFSET);
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as_ss(getOddPair(ft), ScratchRegister, TAG_OFFSET);
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}
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}
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@ -1540,6 +1540,72 @@ MacroAssemblerMIPSCompat::freeStack(Register amount)
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as_addu(StackPointer, StackPointer, amount);
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}
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void
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MacroAssembler::PushRegsInMask(RegisterSet set)
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{
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int32_t diffF = set.fpus().size() * sizeof(double);
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int32_t diffG = set.gprs().size() * sizeof(intptr_t);
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reserveStack(diffG);
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for (GeneralRegisterBackwardIterator iter(set.gprs()); iter.more(); iter++) {
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diffG -= sizeof(intptr_t);
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storePtr(*iter, Address(StackPointer, diffG));
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}
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MOZ_ASSERT(diffG == 0);
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// Double values have to be aligned. We reserve extra space so that we can
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// start writing from the first aligned location.
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// We reserve a whole extra double so that the buffer has even size.
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ma_and(SecondScratchReg, sp, Imm32(~(StackAlignment - 1)));
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reserveStack(diffF + sizeof(double));
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for (FloatRegisterForwardIterator iter(set.fpus()); iter.more(); iter++) {
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// Use assembly s.d because we have alligned the stack.
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// :TODO: (Bug 972836) Fix this once odd regs can be used as
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// float32 only. For now we skip saving odd regs for O32 ABI.
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// :TODO: (Bug 985881) Make a switch for N32 ABI.
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if ((*iter).code() % 2 == 0)
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as_sd(*iter, SecondScratchReg, -diffF);
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diffF -= sizeof(double);
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}
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MOZ_ASSERT(diffF == 0);
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}
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void
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MacroAssembler::PopRegsInMaskIgnore(RegisterSet set, RegisterSet ignore)
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{
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int32_t diffG = set.gprs().size() * sizeof(intptr_t);
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int32_t diffF = set.fpus().size() * sizeof(double);
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const int32_t reservedG = diffG;
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const int32_t reservedF = diffF;
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// Read the buffer form the first aligned location.
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ma_addu(SecondScratchReg, sp, Imm32(reservedF + sizeof(double)));
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ma_and(SecondScratchReg, SecondScratchReg, Imm32(~(StackAlignment - 1)));
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for (FloatRegisterForwardIterator iter(set.fpus()); iter.more(); iter++) {
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// :TODO: (Bug 972836) Fix this once odd regs can be used as
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// float32 only. For now we skip loading odd regs for O32 ABI.
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// :TODO: (Bug 985881) Make a switch for N32 ABI.
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if (!ignore.has(*iter) && ((*iter).code() % 2 == 0))
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// Use assembly l.d because we have alligned the stack.
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as_ld(*iter, SecondScratchReg, -diffF);
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diffF -= sizeof(double);
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}
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freeStack(reservedF + sizeof(double));
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MOZ_ASSERT(diffF == 0);
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for (GeneralRegisterBackwardIterator iter(set.gprs()); iter.more(); iter++) {
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diffG -= sizeof(intptr_t);
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if (!ignore.has(*iter))
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loadPtr(Address(StackPointer, diffG), *iter);
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}
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freeStack(reservedG);
|
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MOZ_ASSERT(diffG == 0);
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}
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void
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MacroAssemblerMIPSCompat::add32(Register src, Register dest)
|
||||
{
|
||||
|
|
@ -2324,17 +2390,17 @@ void
|
|||
MacroAssemblerMIPSCompat::unboxDouble(const ValueOperand &operand, const FloatRegister &dest)
|
||||
{
|
||||
MOZ_ASSERT(dest != ScratchFloatReg);
|
||||
as_mtc1(operand.payloadReg(), dest);
|
||||
as_mtc1_Odd(operand.typeReg(), dest);
|
||||
moveToDoubleLo(operand.payloadReg(), dest);
|
||||
moveToDoubleHi(operand.typeReg(), dest);
|
||||
}
|
||||
|
||||
void
|
||||
MacroAssemblerMIPSCompat::unboxDouble(const Address &src, const FloatRegister &dest)
|
||||
{
|
||||
ma_lw(ScratchRegister, Address(src.base, src.offset + PAYLOAD_OFFSET));
|
||||
as_mtc1(ScratchRegister, dest);
|
||||
moveToDoubleLo(ScratchRegister, dest);
|
||||
ma_lw(ScratchRegister, Address(src.base, src.offset + TAG_OFFSET));
|
||||
as_mtc1_Odd(ScratchRegister, dest);
|
||||
moveToDoubleHi(ScratchRegister, dest);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -2380,8 +2446,8 @@ MacroAssemblerMIPSCompat::unboxPrivate(const ValueOperand &src, Register dest)
|
|||
void
|
||||
MacroAssemblerMIPSCompat::boxDouble(const FloatRegister &src, const ValueOperand &dest)
|
||||
{
|
||||
as_mfc1(dest.payloadReg(), src);
|
||||
as_mfc1_Odd(dest.typeReg(), src);
|
||||
moveFromDoubleLo(src, dest.payloadReg());
|
||||
moveFromDoubleHi(src, dest.typeReg());
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
|||
|
|
@ -234,6 +234,32 @@ class MacroAssemblerMIPS : public Assembler
|
|||
void ma_bc1d(FloatRegister lhs, FloatRegister rhs, Label *label, DoubleCondition c,
|
||||
JumpKind jumpKind = LongJump, FPConditionBit fcc = FCC0);
|
||||
|
||||
|
||||
// These fuctions abstract the access to high part of the double precision
|
||||
// float register. It is intended to work on both 32 bit and 64 bit
|
||||
// floating point coprocessor.
|
||||
// :TODO: (Bug 985881) Modify this for N32 ABI to use mthc1 and mfhc1
|
||||
void moveToDoubleHi(Register src, FloatRegister dest) {
|
||||
as_mtc1(src, getOddPair(dest));
|
||||
}
|
||||
void moveFromDoubleHi(FloatRegister src, Register dest) {
|
||||
as_mfc1(dest, getOddPair(src));
|
||||
}
|
||||
|
||||
void moveToDoubleLo(Register src, FloatRegister dest) {
|
||||
as_mtc1(src, dest);
|
||||
}
|
||||
void moveFromDoubleLo(FloatRegister src, Register dest) {
|
||||
as_mfc1(dest, src);
|
||||
}
|
||||
|
||||
void moveToFloat32(Register src, FloatRegister dest) {
|
||||
as_mtc1(src, dest);
|
||||
}
|
||||
void moveFromFloat32(FloatRegister src, Register dest) {
|
||||
as_mfc1(dest, src);
|
||||
}
|
||||
|
||||
protected:
|
||||
void branchWithCode(InstImm code, Label *label, JumpKind jumpKind);
|
||||
Condition ma_cmp(Register rd, Register lhs, Register rhs, Condition c);
|
||||
|
|
@ -993,8 +1019,8 @@ public:
|
|||
}
|
||||
|
||||
void zeroDouble(FloatRegister reg) {
|
||||
as_mtc1(zero, reg);
|
||||
as_mtc1_Odd(zero, reg);
|
||||
moveToDoubleLo(zero, reg);
|
||||
moveToDoubleHi(zero, reg);
|
||||
}
|
||||
|
||||
void clampIntToUint8(Register reg) {
|
||||
|
|
|
|||
|
|
@ -212,7 +212,7 @@ MoveEmitterMIPS::emitFloat32Move(const MoveOperand &from, const MoveOperand &to)
|
|||
} else if (to.isGeneralReg()) {
|
||||
// This should only be used when passing float parameter in a1,a2,a3
|
||||
MOZ_ASSERT(to.reg() == a1 || to.reg() == a2 || to.reg() == a3);
|
||||
masm.as_mfc1(to.reg(), from.floatReg());
|
||||
masm.moveFromFloat32(from.floatReg(), to.reg());
|
||||
} else {
|
||||
MOZ_ASSERT(to.isMemory());
|
||||
masm.storeFloat32(from.floatReg(), getAdjustedAddress(to));
|
||||
|
|
@ -248,9 +248,9 @@ MoveEmitterMIPS::emitDoubleMove(const MoveOperand &from, const MoveOperand &to)
|
|||
// Two moves are added for one double parameter by
|
||||
// MacroAssemblerMIPSCompat::passABIArg
|
||||
if(to.reg() == a2)
|
||||
masm.as_mfc1(a2, from.floatReg());
|
||||
masm.moveFromDoubleLo(from.floatReg(), a2);
|
||||
else if(to.reg() == a3)
|
||||
masm.as_mfc1_Odd(a3, from.floatReg());
|
||||
masm.moveFromDoubleHi(from.floatReg(), a3);
|
||||
else
|
||||
MOZ_ASSUME_UNREACHABLE("Invalid emitDoubleMove arguments.");
|
||||
} else {
|
||||
|
|
|
|||
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