зеркало из https://github.com/mozilla/gecko-dev.git
Bug 1455019 : [MIPS64] Add error detection for int64 <-> fp conversion in simulator; r=bbouvier
--HG-- extra : rebase_source : 2ee6f92b3ff3ce803d746f8cd9747c1ee41a2e06
This commit is contained in:
Dragan Mladjenovic
Родитель
d7aa10c574
Коммит
e5d8449944
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@ -36,6 +36,7 @@
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#include "mozilla/MathAlgorithms.h"
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#include <float.h>
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#include <limits>
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#include "jit/AtomicOperations.h"
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#include "jit/mips64/Assembler-mips64.h"
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@ -1557,6 +1558,7 @@ Simulator::testFCSRBit(uint32_t cc)
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// Sets the rounding error codes in FCSR based on the result of the rounding.
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// Returns true if the operation was invalid.
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template <typename T>
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bool
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Simulator::setFCSRRoundError(double original, double rounded)
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{
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@ -1584,7 +1586,9 @@ Simulator::setFCSRRoundError(double original, double rounded)
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ret = true;
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}
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if (rounded > INT_MAX || rounded < INT_MIN) {
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if ((long double)rounded > (long double)std::numeric_limits<T>::max() ||
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(long double)rounded < (long double)std::numeric_limits<T>::min())
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{
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setFCSRBit(kFCSROverflowFlagBit, true);
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setFCSRBit(kFCSROverflowCauseBit, true);
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// The reference is not really clear but it seems this is required:
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@ -2730,7 +2734,7 @@ Simulator::configureTypeRegister(SimInstruction* instr,
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alu_out = ~(rs | rt);
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break;
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case ff_slt:
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alu_out = I32_CHECK(rs) < I32_CHECK(rt) ? 1 : 0;
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alu_out = I64(rs) < I64(rt) ? 1 : 0;
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break;
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case ff_sltu:
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alu_out = U64(rs) < U64(rt) ? 1 : 0;
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@ -2774,7 +2778,7 @@ Simulator::configureTypeRegister(SimInstruction* instr,
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}
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break;
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case ff_ddiv:
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if (I32_CHECK(rs) == INT_MIN && I32_CHECK(rt) == -1) {
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if (I64(rs) == INT64_MIN && I64(rt) == -1) {
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i128hilo = U64(INT64_MIN);
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} else {
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uint64_t div = rs / rt;
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@ -3086,65 +3090,72 @@ Simulator::decodeTypeRegister(SimInstruction* instr)
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result--;
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}
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setFpuRegisterLo(fd_reg, result);
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if (setFCSRRoundError(fs_value, rounded)) {
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if (setFCSRRoundError<int32_t>(fs_value, rounded))
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setFpuRegisterLo(fd_reg, kFPUInvalidResult);
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}
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break;
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}
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case ff_trunc_w_fmt: { // Truncate float to word (round towards 0).
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float rounded = truncf(fs_value);
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int32_t result = I32(rounded);
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setFpuRegisterLo(fd_reg, result);
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if (setFCSRRoundError(fs_value, rounded)) {
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if (setFCSRRoundError<int32_t>(fs_value, rounded))
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setFpuRegisterLo(fd_reg, kFPUInvalidResult);
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}
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break;
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}
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case ff_floor_w_fmt: { // Round float to word towards negative infinity.
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float rounded = std::floor(fs_value);
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int32_t result = I32(rounded);
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setFpuRegisterLo(fd_reg, result);
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if (setFCSRRoundError(fs_value, rounded)) {
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if (setFCSRRoundError<int32_t>(fs_value, rounded))
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setFpuRegisterLo(fd_reg, kFPUInvalidResult);
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}
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break;
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}
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case ff_ceil_w_fmt: { // Round double to word towards positive infinity.
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float rounded = std::ceil(fs_value);
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int32_t result = I32(rounded);
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setFpuRegisterLo(fd_reg, result);
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if (setFCSRRoundError(fs_value, rounded)) {
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if (setFCSRRoundError<int32_t>(fs_value, rounded))
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setFpuRegisterLo(fd_reg, kFPUInvalidResult);
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}
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break;
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}
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case ff_cvt_l_fmt: { // Mips64r2: Truncate float to 64-bit long-word.
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float rounded = truncf(fs_value);
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i64 = I64(rounded);
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setFpuRegister(fd_reg, i64);
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break;
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}
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case ff_cvt_l_fmt: // Mips64r2: Truncate float to 64-bit long-word.
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// Rounding modes are not yet supported.
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MOZ_ASSERT((FCSR_ & 3) == 0);
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// In rounding mode 0 it should behave like ROUND.
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MOZ_FALLTHROUGH;
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case ff_round_l_fmt: { // Mips64r2 instruction.
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float rounded =
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fs_value > 0 ? std::floor(fs_value + 0.5) : std::ceil(fs_value - 0.5);
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i64 = I64(rounded);
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setFpuRegister(fd_reg, i64);
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if (setFCSRRoundError<int64_t>(fs_value, rounded))
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setFpuRegister(fd_reg, kFPUInvalidResult64);
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break;
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}
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case ff_trunc_l_fmt: { // Mips64r2 instruction.
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float rounded = truncf(fs_value);
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i64 = I64(rounded);
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setFpuRegister(fd_reg, i64);
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if (setFCSRRoundError<int64_t>(fs_value, rounded))
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setFpuRegister(fd_reg, kFPUInvalidResult64);
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break;
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}
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case ff_floor_l_fmt: // Mips64r2 instruction.
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i64 = I64(std::floor(fs_value));
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case ff_floor_l_fmt: { // Mips64r2 instruction.
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float rounded = std::floor(fs_value);
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i64 = I64(rounded);
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setFpuRegister(fd_reg, i64);
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if (setFCSRRoundError<int64_t>(fs_value, rounded))
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setFpuRegister(fd_reg, kFPUInvalidResult64);
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break;
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case ff_ceil_l_fmt: // Mips64r2 instruction.
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i64 = I64(std::ceil(fs_value));
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}
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case ff_ceil_l_fmt: { // Mips64r2 instruction.
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float rounded = std::ceil(fs_value);
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i64 = I64(rounded);
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setFpuRegister(fd_reg, i64);
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if (setFCSRRoundError<int64_t>(fs_value, rounded))
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setFpuRegister(fd_reg, kFPUInvalidResult64);
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break;
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}
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case ff_cvt_ps_s:
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case ff_c_f_fmt:
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MOZ_CRASH();
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@ -3237,7 +3248,7 @@ Simulator::decodeTypeRegister(SimInstruction* instr)
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result--;
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}
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setFpuRegisterLo(fd_reg, result);
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if (setFCSRRoundError(ds_value, rounded))
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if (setFCSRRoundError<int32_t>(ds_value, rounded))
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setFpuRegisterLo(fd_reg, kFPUInvalidResult);
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break;
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}
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@ -3245,7 +3256,7 @@ Simulator::decodeTypeRegister(SimInstruction* instr)
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double rounded = trunc(ds_value);
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int32_t result = I32(rounded);
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setFpuRegisterLo(fd_reg, result);
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if (setFCSRRoundError(ds_value, rounded))
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if (setFCSRRoundError<int32_t>(ds_value, rounded))
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setFpuRegisterLo(fd_reg, kFPUInvalidResult);
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break;
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}
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@ -3253,7 +3264,7 @@ Simulator::decodeTypeRegister(SimInstruction* instr)
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double rounded = std::floor(ds_value);
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int32_t result = I32(rounded);
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setFpuRegisterLo(fd_reg, result);
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if (setFCSRRoundError(ds_value, rounded))
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if (setFCSRRoundError<int32_t>(ds_value, rounded))
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setFpuRegisterLo(fd_reg, kFPUInvalidResult);
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break;
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}
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@ -3261,40 +3272,51 @@ Simulator::decodeTypeRegister(SimInstruction* instr)
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double rounded = std::ceil(ds_value);
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int32_t result = I32(rounded);
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setFpuRegisterLo(fd_reg, result);
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if (setFCSRRoundError(ds_value, rounded))
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if (setFCSRRoundError<int32_t>(ds_value, rounded))
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setFpuRegisterLo(fd_reg, kFPUInvalidResult);
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break;
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}
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case ff_cvt_s_fmt: // Convert double to float (single).
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setFpuRegisterFloat(fd_reg, static_cast<float>(ds_value));
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break;
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case ff_cvt_l_fmt: { // Mips64r2: Truncate double to 64-bit long-word.
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double rounded = trunc(ds_value);
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case ff_cvt_l_fmt: // Mips64r2: Truncate double to 64-bit long-word.
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// Rounding modes are not yet supported.
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MOZ_ASSERT((FCSR_ & 3) == 0);
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// In rounding mode 0 it should behave like ROUND.
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MOZ_FALLTHROUGH;
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case ff_round_l_fmt: { // Mips64r2 instruction.
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double rounded =
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ds_value > 0 ? std::floor(ds_value + 0.5) : std::ceil(ds_value - 0.5);
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i64 = I64(rounded);
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setFpuRegister(fd_reg, i64);
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if (setFCSRRoundError<int64_t>(ds_value, rounded))
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setFpuRegister(fd_reg, kFPUInvalidResult64);
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break;
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}
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case ff_trunc_l_fmt: { // Mips64r2 instruction.
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double rounded = trunc(ds_value);
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i64 = I64(rounded);
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setFpuRegister(fd_reg, i64);
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if (setFCSRRoundError<int64_t>(ds_value, rounded))
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setFpuRegister(fd_reg, kFPUInvalidResult64);
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break;
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}
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case ff_round_l_fmt: { // Mips64r2 instruction.
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double rounded =
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ds_value > 0 ? std::floor(ds_value + 0.5) : std::ceil(ds_value - 0.5);
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case ff_floor_l_fmt: { // Mips64r2 instruction.
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double rounded = std::floor(ds_value);
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i64 = I64(rounded);
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setFpuRegister(fd_reg, i64);
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if (setFCSRRoundError<int64_t>(ds_value, rounded))
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setFpuRegister(fd_reg, kFPUInvalidResult64);
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break;
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}
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case ff_floor_l_fmt: // Mips64r2 instruction.
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i64 = I64(std::floor(ds_value));
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setFpuRegister(fd_reg, i64);
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break;
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case ff_ceil_l_fmt: // Mips64r2 instruction.
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i64 = I64(std::ceil(ds_value));
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case ff_ceil_l_fmt: { // Mips64r2 instruction.
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double rounded = std::ceil(ds_value);
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i64 = I64(rounded);
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setFpuRegister(fd_reg, i64);
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if (setFCSRRoundError<int64_t>(ds_value, rounded))
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setFpuRegister(fd_reg, kFPUInvalidResult64);
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break;
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}
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case ff_c_f_fmt:
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MOZ_CRASH();
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break;
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@ -75,6 +75,7 @@ const int kNumFPURegisters = 32;
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const int kFCSRRegister = 31;
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const int kInvalidFPUControlRegister = -1;
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const uint32_t kFPUInvalidResult = static_cast<uint32_t>(1 << 31) - 1;
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const uint64_t kFPUInvalidResult64 = static_cast<uint64_t>(1ULL << 63) - 1;
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// FCSR constants.
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const uint32_t kFCSRInexactFlagBit = 2;
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@ -197,6 +198,7 @@ class Simulator {
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double getFpuRegisterDouble(int fpureg) const;
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void setFCSRBit(uint32_t cc, bool value);
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bool testFCSRBit(uint32_t cc);
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template <typename T>
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bool setFCSRRoundError(double original, double rounded);
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// Special case of set_register and get_register to access the raw PC value.
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