зеркало из https://github.com/mozilla/gecko-dev.git
Bug 1071024 - ARM simulator support for LDREX, LDREXH, LDREXB, LDREXD, STREX, STREXH, STREXB, STREXD, SXTB, SXTH, DMB, DSB, and ISB. r=mjrosenb
This commit is contained in:
Lars T Hansen
Родитель
626457013f
Коммит
e9a4b9b26c
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@ -2486,7 +2486,67 @@ Simulator::decodeType01(SimInstruction *instr)
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MOZ_CRASH();
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}
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} else {
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MOZ_CRASH(); // Not used atm.
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if (instr->bit(23)) {
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// Load-exclusive / store-exclusive.
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//
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// Bare-bones simulation: the store always succeeds, and we do not
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// execute any fences. Also, we allow readDW and writeDW to split
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// the memory transaction.
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//
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// The next step up would involve remembering the value that was
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// read with load-exclusive so that we could use compareExchange
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// for the store-exclusive, and to implement atomic doubleword
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// read and write.
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//
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// Also see DMB/DSB/ISB below.
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if (instr->bit(20)) {
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// Load-exclusive.
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int rn = instr->rnValue();
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int rt = instr->rtValue();
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int32_t address = get_register(rn);
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switch (instr->bits(22,21)) {
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case 0:
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set_register(rt, readW(address, instr));
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break;
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case 1:
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set_dw_register(rt, readDW(address));
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break;
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case 2:
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set_register(rt, readBU(address));
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break;
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case 3:
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set_register(rt, readHU(address, instr));
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break;
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}
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} else {
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// Store-exclusive.
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int rn = instr->rnValue();
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int rd = instr->rdValue();
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int rt = instr->bits(3,0);
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int32_t address = get_register(rn);
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int32_t value = get_register(rt);
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switch (instr->bits(22,21)) {
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case 0:
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writeW(address, rt, instr);
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break;
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case 1: {
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MOZ_ASSERT((rt % 2) == 0);
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int32_t value2 = get_register(rt+1);
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writeDW(address, value, value2);
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break;
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}
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case 2:
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writeB(address, (uint8_t)value);
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break;
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case 3:
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writeH(address, (uint16_t)value, instr);
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break;
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}
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set_register(rd, 0);
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}
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} else {
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MOZ_CRASH(); // Not used atm
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}
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}
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} else {
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// Extra load/store instructions.
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@ -2885,6 +2945,21 @@ Simulator::decodeType2(SimInstruction *instr)
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}
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}
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static uint32_t
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rotateBytes(uint32_t val, int32_t rotate)
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{
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switch (rotate) {
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default:
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return val;
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case 1:
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return (val >> 8) | (val << 24);
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case 2:
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return (val >> 16) | (val << 16);
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case 3:
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return (val >> 24) | (val << 8);
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}
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}
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void
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Simulator::decodeType3(SimInstruction *instr)
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{
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@ -2963,27 +3038,21 @@ Simulator::decodeType3(SimInstruction *instr)
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MOZ_CRASH();
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break;
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case 1:
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MOZ_CRASH();
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if (instr->bits(7,4) == 7 && instr->bits(19,16) == 15) {
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uint32_t rm_val = rotateBytes(get_register(instr->rmValue()), instr->bits(11, 10));
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if (instr->bit(20))
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set_register(rd, (int32_t)(int16_t)(rm_val & 0xFFFF)); // SXTH
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else
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set_register(rd, (int32_t)(int8_t)(rm_val & 0xFF)); // SXTB
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} else {
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MOZ_CRASH();
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}
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break;
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case 2:
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if ((instr->bit(20) == 0) && (instr->bits(9, 6) == 1)) {
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if (instr->bits(19, 16) == 0xF) {
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// Uxtb16.
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uint32_t rm_val = get_register(instr->rmValue());
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int32_t rotate = instr->bits(11, 10);
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switch (rotate) {
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case 0:
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break;
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case 1:
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rm_val = (rm_val >> 8) | (rm_val << 24);
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break;
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case 2:
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rm_val = (rm_val >> 16) | (rm_val << 16);
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break;
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case 3:
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rm_val = (rm_val >> 24) | (rm_val << 8);
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break;
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}
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uint32_t rm_val = rotateBytes(get_register(instr->rmValue()), instr->bits(11, 10));
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set_register(rd, (rm_val & 0xFF) | (rm_val & 0xFF0000));
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} else {
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MOZ_CRASH();
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@ -2996,40 +3065,12 @@ Simulator::decodeType3(SimInstruction *instr)
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if ((instr->bit(20) == 0) && (instr->bits(9, 6) == 1)) {
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if (instr->bits(19, 16) == 0xF) {
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// Uxtb.
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uint32_t rm_val = get_register(instr->rmValue());
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int32_t rotate = instr->bits(11, 10);
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switch (rotate) {
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case 0:
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break;
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case 1:
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rm_val = (rm_val >> 8) | (rm_val << 24);
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break;
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case 2:
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rm_val = (rm_val >> 16) | (rm_val << 16);
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break;
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case 3:
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rm_val = (rm_val >> 24) | (rm_val << 8);
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break;
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}
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uint32_t rm_val = rotateBytes(get_register(instr->rmValue()), instr->bits(11, 10));
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set_register(rd, (rm_val & 0xFF));
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} else {
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// Uxtab.
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uint32_t rn_val = get_register(rn);
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uint32_t rm_val = get_register(instr->rmValue());
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int32_t rotate = instr->bits(11, 10);
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switch (rotate) {
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case 0:
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break;
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case 1:
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rm_val = (rm_val >> 8) | (rm_val << 24);
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break;
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case 2:
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rm_val = (rm_val >> 16) | (rm_val << 16);
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break;
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case 3:
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rm_val = (rm_val >> 24) | (rm_val << 8);
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break;
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}
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uint32_t rm_val = rotateBytes(get_register(instr->rmValue()), instr->bits(11, 10));
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set_register(rd, rn_val + (rm_val & 0xFF));
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}
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} else {
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@ -3992,6 +4033,23 @@ Simulator::decodeSpecialCondition(SimInstruction *instr)
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}
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break;
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case 0xA:
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if (instr->bits(31,20) == 0xf57) {
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// Minimal simulation: do nothing.
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//
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// If/when we upgrade load-exclusive and store-exclusive (above) to do something
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// useful concurrency-wise, we should also upgrade these instructions.
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switch (instr->bits(7,4)) {
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case 5: // DMB
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case 4: // DSB
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case 6: // ISB
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break;
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default:
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MOZ_CRASH();
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}
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} else {
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MOZ_CRASH();
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}
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break;
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case 0xB:
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if (instr->bits(22, 20) == 5 && instr->bits(15, 12) == 0xf) {
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// pld: ignore instruction.
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