зеркало из https://github.com/mozilla/gecko-dev.git
Bug 538060 - nanojit: improve 64-bit loads and stores in the X64 back-end. r=gal,rreitmai,edwsmith.
--HG-- extra : convert_revision : 1fd416d0954dc667073f3a92087c01fc23e5c3aa
This commit is contained in:
Nicholas Nethercote
Родитель
1dcde024a1
Коммит
ebdd2dbd3c
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@ -659,9 +659,9 @@ FragmentAssembler::assemble_call(const string &op)
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size_t argc = mTokens.size();
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for (size_t i = 0; i < argc; ++i) {
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args[i] = ref(mTokens[mTokens.size() - (i+1)]);
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if (args[i]->isFloat()) ty = ARGSIZE_F;
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else if (args[i]->isQuad()) ty = ARGSIZE_Q;
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else ty = ARGSIZE_I;
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if (args[i]->isF64()) ty = ARGSIZE_F;
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else if (args[i]->isI64()) ty = ARGSIZE_Q;
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else ty = ARGSIZE_I;
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// Nb: i+1 because argMask() uses 1-based arg counting.
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ci->_argtypes |= argMask(ty, i+1, argc);
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}
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@ -423,22 +423,6 @@ namespace nanojit
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(offsetof(LInsSti, ins) - offsetof(LInsSti, oprnd_2)) );
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}
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bool LIns::isFloat() const {
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switch (opcode()) {
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default:
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return false;
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case LIR_fadd:
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case LIR_fsub:
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case LIR_fmul:
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case LIR_fdiv:
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case LIR_fneg:
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case LIR_fcall:
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case LIR_i2f:
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case LIR_u2f:
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return true;
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}
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}
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LIns* LirWriter::ins2i(LOpcode v, LIns* oprnd1, int32_t imm)
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{
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return ins2(v, oprnd1, insImm(imm));
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@ -492,14 +492,9 @@ namespace nanojit
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bool isop(LOpcode o) const {
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return opcode() == o;
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}
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bool isQuad() const {
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LTy ty = retTypes[opcode()];
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return ty == LTy_I64 || ty == LTy_F64;
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}
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bool isCond() const {
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return (isop(LIR_ov)) || isCmp();
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}
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bool isFloat() const; // not inlined because it contains a switch
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bool isCmp() const {
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LOpcode op = opcode();
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return (op >= LIR_eq && op <= LIR_uge) ||
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@ -550,11 +545,26 @@ namespace nanojit
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return isop(LIR_jt) || isop(LIR_jf) || isop(LIR_j) || isop(LIR_jtbl);
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}
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bool isPtr() {
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#ifdef NANOJIT_64BIT
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return retTypes[opcode()] == LTy_I64;
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#else
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bool isVoid() const {
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return retTypes[opcode()] == LTy_Void;
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}
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bool isI32() const {
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return retTypes[opcode()] == LTy_I32;
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}
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bool isI64() const {
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return retTypes[opcode()] == LTy_I64;
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}
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bool isF64() const {
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return retTypes[opcode()] == LTy_F64;
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}
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bool isQuad() const {
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return isI64() || isF64();
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}
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bool isPtr() const {
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#ifdef NANOJIT_64BIT
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return isI64();
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#else
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return isI32();
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#endif
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}
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@ -571,7 +581,7 @@ namespace nanojit
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if (isCall())
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return !isCse();
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else
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return retTypes[opcode()] == LTy_Void;
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return isVoid();
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}
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inline void* constvalp() const
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@ -774,7 +774,7 @@ namespace nanojit
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prepResultReg(div, rmask(RAX));
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Register rhsReg = findRegFor(rhs, (GpRegs ^ (rmask(RAX)|rmask(RDX))));
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Register rhsReg = findRegFor(rhs, GpRegs & ~(rmask(RAX)|rmask(RDX)));
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Register lhsReg = lhs->isUnusedOrHasUnknownReg()
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? findSpecificRegForUnallocated(lhs, RAX)
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: lhs->getReg();
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@ -1385,23 +1385,20 @@ namespace nanojit
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}
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void Assembler::asm_load64(LIns *ins) {
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Register rr, rb;
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int32_t dr;
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switch (ins->opcode()) {
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case LIR_ldq:
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case LIR_ldqc:
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regalloc_load(ins, GpRegs, rr, dr, rb);
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NanoAssert(IsGpReg(rr));
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MOVQRM(rr, dr, rb); // general 64bit load, 32bit const displacement
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break;
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case LIR_ldf:
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case LIR_ldfc:
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regalloc_load(ins, GpRegs, rr, dr, rb);
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if (IsGpReg(rr)) {
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// general 64bit load, 32bit const displacement
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MOVQRM(rr, dr, rb);
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} else {
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NanoAssert(IsFpReg(rr));
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// load 64bits into XMM. don't know if double or int64, assume double.
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MOVSDRM(rr, dr, rb);
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}
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regalloc_load(ins, FpRegs, rr, dr, rb);
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NanoAssert(IsFpReg(rr));
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MOVSDRM(rr, dr, rb); // load 64bits into XMM
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break;
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case LIR_ld32f:
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case LIR_ldc32f:
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@ -1454,58 +1451,25 @@ namespace nanojit
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NanoAssert(value->isQuad());
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Register b = getBaseReg(base, d, BaseRegs);
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Register r;
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// if we have to choose a register, use a GPR, but not the base reg
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if (value->isUnusedOrHasUnknownReg()) {
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RegisterMask allow;
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// If op is LIR_st32f and we have no reg, prefer FPR over GPR: saves an instruction later,
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// and the value is almost certainly going to operated on as FP later anyway.
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// XXX: isFloat doesn't cover float/fmod! see bug 520208.
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if (op == LIR_st32f || value->isFloat() || value->isop(LIR_float) || value->isop(LIR_fmod)) {
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allow = FpRegs;
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} else {
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allow = GpRegs;
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}
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r = findRegFor(value, allow & ~rmask(b));
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} else {
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r = value->getReg();
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}
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switch (op) {
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case LIR_stqi:
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case LIR_stfi:
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{
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if (IsGpReg(r)) {
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// gpr store
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MOVQMR(r, d, b);
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}
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else {
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// xmm store
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MOVSDMR(r, d, b);
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}
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case LIR_stqi: {
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Register r = findRegFor(value, GpRegs & ~rmask(b));
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MOVQMR(r, d, b); // gpr store
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break;
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}
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case LIR_st32f:
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{
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// need a scratch FPR reg
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case LIR_stfi: {
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Register r = findRegFor(value, FpRegs);
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MOVSDMR(r, d, b); // xmm store
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break;
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}
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case LIR_st32f: {
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Register r = findRegFor(value, FpRegs);
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Register t = registerAllocTmp(FpRegs & ~rmask(r));
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// store
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MOVSSMR(t, d, b);
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// cvt to single-precision
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if (IsGpReg(r))
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{
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CVTSD2SS(t, t);
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MOVQXR(t, r); // xmm <- gpr: use movq xmm, r/m64 (66 REX.W 0F 6E /r)
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}
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else
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{
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NanoAssert(IsFpReg(r));
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CVTSD2SS(t, r);
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}
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XORPS(t); // break dependency chains
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MOVSSMR(t, d, b); // store
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CVTSD2SS(t, r); // cvt to single-precision
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XORPS(t); // break dependency chains
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break;
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}
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default:
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@ -1516,12 +1480,9 @@ namespace nanojit
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void Assembler::asm_store32(LOpcode op, LIns *value, int d, LIns *base) {
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// quirk of x86-64: reg cannot appear to be ah/bh/ch/dh
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// for single-byte stores with REX prefix
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const RegisterMask SrcRegs =
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(op == LIR_stb) ?
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(GpRegs & ~(1<<RSP | 1<<RBP | 1<<RSI | 1<<RDI)) :
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GpRegs;
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// Quirk of x86-64: reg cannot appear to be ah/bh/ch/dh for
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// single-byte stores with REX prefix.
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const RegisterMask SrcRegs = (op == LIR_stb) ? SingleByteStoreRegs : GpRegs;
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NanoAssert(!value->isQuad());
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Register b = getBaseReg(base, d, BaseRegs);
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@ -329,6 +329,10 @@ namespace nanojit
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static const int NumSavedRegs = 5; // rbx, r12-15
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static const int NumArgRegs = 6;
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#endif
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// Warning: when talking about single byte registers, RSP/RBP/RSI/RDI are
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// actually synonyms for AH/CH/DH/BH. So this value means "any
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// single-byte GpReg except AH/CH/DH/BH".
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static const int SingleByteStoreRegs = GpRegs & ~(1<<RSP | 1<<RBP | 1<<RSI | 1<<RDI);
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static inline bool IsFpReg(Register r) {
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return ((1<<r) & FpRegs) != 0;
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@ -589,7 +589,6 @@ namespace nanojit
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}
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else
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{
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int dr = disp(ins);
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Register rb;
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if (base->isop(LIR_alloc)) {
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