зеркало из https://github.com/mozilla/gecko-dev.git
358 строки
20 KiB
Plaintext
358 строки
20 KiB
Plaintext
// -*- Mode: C++; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 2 -*-
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//
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// The contents of this file are subject to the Netscape Public
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// License Version 1.1 (the "License"); you may not use this file
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// except in compliance with the License. You may obtain a copy of
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// the License at http://www.mozilla.org/NPL/
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//
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// Software distributed under the License is distributed on an "AS
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// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
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// implied. See the License for the specific language governing
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// rights and limitations under the License.
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//
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// The Original Code is mozilla.org code.
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//
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// The Initial Developer of the Original Code is Netscape
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// Communications Corporation. Portions created by Netscape are
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// Copyright (C) 1998 Netscape Communications Corporation. All
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// Rights Reserved.
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//
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// Contributor(s):
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//
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// Here's the syntax of the PrimitiveOperations table entries expressed as a BNF grammar.
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// These entries are converted into several different tables inside DataNodeTemplates.cpp
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// and PrimitiveOperations.h.
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//
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// table-entry ::= '{' primitiveOperation ',' primitiveCategory ',' usage '}'
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//
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// usage ::= '"' outputs ':' inputs '"' | null-usage
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//
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// null-usage ::= '""' // indicates that this is not a legal primitive
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//
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// outputs ::= exception | arg | exception arg | root
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//
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// inputs ::= arg* | arg* repeat-arg | root
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//
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// repeat-arg ::= arg '*' // zero or more arguments that satisfy the given arg pattern
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//
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// arg ::= arg-origin arg-kind | short-arg
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//
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// arg-origin ::= 'V' | // variable
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// 'C' | // constant
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// 'A' // either variable or constant
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//
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// arg-kind ::= 'v' | // void
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// 'i' | // integer
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// 'l' | // long
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// 'f' | // float
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// 'd' | // double
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// 'a' | // address
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// 'c' | // condition
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// 'm' | // memory
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// 't' | // tuple
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// '@' // any of the above arg-kinds except memory or tuple
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//
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// short-arg ::= 'M' | // same as 'Vm'
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// 'T' // same as 'Vt'
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//
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// exception ::= 'E' // flag that indicates that this primitive causes exceptions
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// // (sets fnCanRaiseException and fnIsRoot)
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//
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// root ::= 'Z' // flag that indicates that this primitive is attached to a control node (sets fnIsRoot)
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//
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ARG-ORIGIN 'V' aoVariable;
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ARG-ORIGIN 'C' aoConstant;
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ARG-ORIGIN 'A' aoEither;
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ARG-KIND 'v' vkVoid;
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ARG-KIND 'i' vkInt;
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ARG-KIND 'l' vkLong;
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ARG-KIND 'f' vkFloat;
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ARG-KIND 'd' vkDouble;
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ARG-KIND 'a' vkAddr;
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ARG-KIND 'c' vkCond;
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ARG-KIND 'm' vkMemory;
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ARG-KIND 't' vkTuple;
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SHORT-ARG 'M' vkMemory;
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SHORT-ARG 'T' vkTuple;
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{poNone, pcNone, ""}
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{poPhi_I, pcPhi, "Vi:Ai*"} // 32-bit integer phi node Aint ... Aint -> Vint
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{poPhi_L, pcPhi, "Vl:Al*"} // 64-bit integer phi node Along ... Along -> Vlong
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{poPhi_F, pcPhi, "Vf:Af*"} // 32-bit float phi node Afloat ... Afloat -> Vfloat
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{poPhi_D, pcPhi, "Vd:Ad*"} // 64-bit float phi node Adouble ... Adouble -> Vdouble
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{poPhi_A, pcPhi, "Va:Aa*"} // Pointer phi node Aaddr ... Aaddr -> Vaddr
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{poPhi_C, pcPhi, "Vc:Ac*"} // Condition phi node Acond ... Acond -> Vcond
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{poPhi_M, pcPhi, "M:M*"} // Memory phi node M ... M -> M
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{poConst_I, pcConst, "Vi:Ci"} // 32-bit integer constant Cint -> Vint
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{poConst_L, pcConst, "Vl:Cl"} // 64-bit integer constant Clong -> Vlong
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{poConst_F, pcConst, "Vf:Cf"} // 32-bit float constant Cfloat -> Vfloat
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{poConst_D, pcConst, "Vd:Cd"} // 64-bit float constant Cdouble -> Vdouble
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{poConst_A, pcConst, "Va:Ca"} // Pointer constant Caddr -> Vaddr
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{poConst_C, pcConst, "Vc:Cc"} // Condition constant Ccond -> Vcond
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{poConst_M, pcConst, "M:Cm"} // Memory constant Cmemory -> M
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{poProj_I, pcProj, "Vi:T"} // 32-bit integer extracted from tuple T -> Vint
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{poProj_L, pcProj, "Vl:T"} // 64-bit integer extracted from tuple T -> Vlong
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{poProj_F, pcProj, "Vf:T"} // 32-bit float extracted from tuple T -> Vfloat
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{poProj_D, pcProj, "Vd:T"} // 64-bit float extracted from tuple T -> Vdouble
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{poProj_A, pcProj, "Va:T"} // Pointer extracted from tuple T -> Vaddr
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{poProj_C, pcNone, ""} // Condition extracted from tuple T -> Vcond (not used)
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{poProj_M, pcProj, "M:T"} // Memory extracted from tuple T -> M
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{poDebug, pcDebug, "M:MA@*"} // Breakpoint M, ... -> M
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{poBreak, pcDebug, "M:MA@*"} // Breakpoint M, ... -> M
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{poArg_I, pcArg, "Vi:Z"} // 32-bit integer argument -> Vint
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{poArg_L, pcArg, "Vl:Z"} // 64-bit integer argument -> Vlong
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{poArg_F, pcArg, "Vf:Z"} // 32-bit float argument -> Vfloat
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{poArg_D, pcArg, "Vd:Z"} // 64-bit float argument -> Vdouble
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{poArg_A, pcArg, "Va:Z"} // Pointer argument -> Vaddr
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{poArg_C, pcNone, ""} // Condition argument -> Vcond (not used)
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{poArg_M, pcArg, "M:Z"} // Argument representing all of memory -> M
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{poResult_I, pcResult, "Z:Ai"} // 32-bit integer result Aint ->
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{poResult_L, pcResult, "Z:Al"} // 64-bit integer result Along ->
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{poResult_F, pcResult, "Z:Af"} // 32-bit float result Afloat ->
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{poResult_D, pcResult, "Z:Ad"} // 64-bit float result Adouble ->
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{poResult_A, pcResult, "Z:Aa"} // Pointer result Aaddr ->
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{poResult_C, pcNone, ""} // Condition result Acond -> (not used)
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{poResult_M, pcResult, "Z:M"} // Result representing all of memory M ->
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// Cond lt eq gt un
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{poIfLt, pcIfCond, "Z:Vc"} // If condition 1 0 0 0 Vcond ->
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{poIfEq, pcIfCond, "Z:Vc"} // If condition 0 1 0 0 Vcond ->
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{poIfLe, pcIfCond, "Z:Vc"} // If condition 1 1 0 0 Vcond ->
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{poIfGt, pcIfCond, "Z:Vc"} // If condition 0 0 1 0 Vcond ->
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{poIfLgt, pcIfCond, "Z:Vc"} // If condition 1 0 1 0 Vcond ->
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{poIfGe, pcIfCond, "Z:Vc"} // If condition 0 1 1 0 Vcond ->
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{poIfOrd, pcIfCond, "Z:Vc"} // If condition 1 1 1 0 Vcond ->
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{poIfUnord, pcIfCond, "Z:Vc"} // If condition 0 0 0 1 Vcond ->
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{poIfULt, pcIfCond, "Z:Vc"} // If condition 1 0 0 1 Vcond ->
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{poIfUEq, pcIfCond, "Z:Vc"} // If condition 0 1 0 1 Vcond ->
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{poIfULe, pcIfCond, "Z:Vc"} // If condition 1 1 0 1 Vcond ->
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{poIfUGt, pcIfCond, "Z:Vc"} // If condition 0 0 1 1 Vcond ->
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{poIfNe, pcIfCond, "Z:Vc"} // If condition 1 0 1 1 Vcond ->
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{poIfUGe, pcIfCond, "Z:Vc"} // If condition 0 1 1 1 Vcond ->
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{poSwitch, pcSwitch, "Z:Vi"} // Switch index node Vint ->
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{poCatch, pcCatch, "Va:Z"} // Catch exception producer -> Vaddr
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{poAnd_I, pcGeneric, "Vi:ViAi"} // Logical AND Vint & Aint -> Vint
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{poAnd_L, pcGeneric, "Vl:VlAl"} // Logical AND Vlong & Along -> Vlong
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{poOr_I, pcGeneric, "Vi:ViAi"} // Logical OR Vint | Aint -> Vint
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{poOr_L, pcGeneric, "Vl:VlAl"} // Logical OR Vlong | Along -> Vlong
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{poXor_I, pcGeneric, "Vi:ViAi"} // Logical XOR Vint ^ Aint -> Vint
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{poXor_L, pcGeneric, "Vl:VlAl"} // Logical XOR Vlong ^ Along -> Vlong
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{poAdd_I, pcGeneric, "Vi:ViAi"} // Add Vint + Aint -> Vint
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{poAdd_L, pcGeneric, "Vl:VlAl"} // Add Vlong + Along -> Vlong
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{poAdd_A, pcGeneric, "Va:AaAi"} // Add Aaddr + exts(Aint) -> Vaddr
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{poAddU_A, pcGeneric, "Va:AaAi"} // Add Aaddr + extu(Aint) -> Vaddr
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{poSub_I, pcGeneric, "Vi:AiVi"} // Subtract Aint - Vint -> Vint
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{poSub_L, pcGeneric, "Vl:AlVl"} // Subtract Along - Vlong -> Vlong
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{poSub_A, pcGeneric, "Va:AaVi"} // Subtract Aaddr - exts(Vint) -> Vaddr
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{poSubU_A, pcGeneric, "Va:AaVi"} // Subtract Aaddr - extu(Vint) -> Vaddr
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{poSubA_I, pcGeneric, "Vi:AaAa"} // Subtract addresses Aaddr - Aaddr -> Vint
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{poMul_I, pcGeneric, "Vi:ViAi"} // Multiply Vint * Aint -> Vint
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{poMul_L, pcGeneric, "Vl:VlAl"} // Multiply Vlong * Along -> Vlong
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{poDiv_I, pcDivMod, "Vi:AiAi"} // Divide signed Aint /s Aint -> Vint
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{poDiv_L, pcDivMod, "Vl:AlAl"} // Divide signed Along /s Along -> Vlong
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{poDivE_I, pcDivMod, "EVi:AiVi"} // Divide signed exc Aint /s Vint -> Vint, E
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{poDivE_L, pcDivMod, "EVl:AlVl"} // Divide signed exc Along /s Vlong -> Vlong, E
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{poDivU_I, pcDivMod, "Vi:AiAi"} // Divide unsigned Aint /u Aint -> Vint
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{poDivU_L, pcDivMod, "Vl:AlAl"} // Divide unsigned Along /u Along -> Vlong
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{poDivUE_I, pcDivMod, "EVi:AiVi"} // Divide unsigned exc Aint /u Vint -> Vint, E
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{poDivUE_L, pcDivMod, "EVl:AlVl"} // Divide unsigned exc Along /u Vlong -> Vlong, E
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{poMod_I, pcDivMod, "Vi:AiAi"} // Modulo signed Aint %s Aint -> Vint
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{poMod_L, pcDivMod, "Vl:AlAl"} // Modulo signed Along %s Along -> Vlong
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{poModE_I, pcDivMod, "EVi:AiVi"} // Modulo signed exc Aint %s Vint -> Vint, E
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{poModE_L, pcDivMod, "EVl:AlVl"} // Modulo signed exc Along %s Vlong -> Vlong, E
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{poModU_I, pcDivMod, "Vi:AiAi"} // Modulo unsigned Aint %u Aint -> Vint
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{poModU_L, pcDivMod, "Vl:AlAl"} // Modulo unsigned Along %u Along -> Vlong
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{poModUE_I, pcDivMod, "EVi:AiVi"} // Modulo unsigned exc Aint %u Vint -> Vint, E
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{poModUE_L, pcDivMod, "EVl:AlVl"} // Modulo unsigned exc Along %u Vlong -> Vlong, E
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{poShl_I, pcShift, "Vi:AiAi"} // Shift left Aint << Aint -> Vint
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{poShl_L, pcShift, "Vl:AlAi"} // Shift left Along << Aint -> Vlong
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{poShr_I, pcShift, "Vi:AiAi"} // Shift right signed Aint >>s Aint -> Vint
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{poShr_L, pcShift, "Vl:AlAi"} // Shift right signed Along >>s Aint -> Vlong
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{poShrU_I, pcShift, "Vi:AiAi"} // Shift right unsigned Aint >>u Aint -> Vint
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{poShrU_L, pcShift, "Vl:AlAi"} // Shift right unsigned Along >>u Aint -> Vlong
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{poExt_I, pcExt, "Vi:ViCi"} // Signed field extract Vint, Cint -> Vint
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{poExt_L, pcExt, "Vl:VlCi"} // Signed field extract Vlong, Cint -> Vlong
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{poFAdd_F, pcFGeneric, "Vf:VfAf"} // FP add Vfloat + Afloat -> Vfloat
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{poFAdd_D, pcFGeneric, "Vd:VdAd"} // FP add Vdouble + Adouble -> Vdouble
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{poFSub_F, pcFGeneric, "Vf:AfVf"} // FP subtract Afloat - Vfloat -> Vfloat
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{poFSub_D, pcFGeneric, "Vd:AdVd"} // FP subtract Adouble - Vdouble -> Vdouble
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{poFMul_F, pcFGeneric, "Vf:VfAf"} // FP multiply Vfloat * Afloat -> Vfloat
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{poFMul_D, pcFGeneric, "Vd:VdAd"} // FP multiply Vdouble * Adouble -> Vdouble
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{poFDiv_F, pcFGeneric, "Vf:AfAf"} // FP divide Afloat / Afloat -> Vfloat
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{poFDiv_D, pcFGeneric, "Vd:AdAd"} // FP divide Adouble / Adouble -> Vdouble
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{poFRem_F, pcFGeneric, "Vf:AfAf"} // FP Java remainder Afloat rem Afloat -> Vfloat
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{poFRem_D, pcFGeneric, "Vd:AdAd"} // FP Java remainder Adouble rem Adouble -> Vdouble
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{poConvI_L, pcConv, "Vi:Vl"} // Convert Vlong -> Vint
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{poConvL_I, pcConv, "Vl:Vi"} // Convert exts(Vint) -> Vlong
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{poFConvI_F, pcFConv, "Vi:Vf"} // FP convert Vfloat -> Vint
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{poFConvI_D, pcFConv, "Vi:Vd"} // FP convert Vdouble -> Vint
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{poFConvL_F, pcFConv, "Vl:Vf"} // FP convert Vfloat -> Vlong
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{poFConvL_D, pcFConv, "Vl:Vd"} // FP convert Vdouble -> Vlong
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{poFConvF_I, pcFConv, "Vf:Vi"} // FP convert Vint -> Vfloat
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{poFConvF_L, pcFConv, "Vf:Vl"} // FP convert Vlong -> Vfloat
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{poFConvF_D, pcFConv, "Vf:Vd"} // FP convert Vdouble -> Vfloat
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{poFConvD_I, pcFConv, "Vd:Vi"} // FP convert Vint -> Vdouble
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{poFConvD_L, pcFConv, "Vd:Vl"} // FP convert Vlong -> Vdouble
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{poFConvD_F, pcFConv, "Vd:Vf"} // FP convert Vfloat -> Vdouble
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{poCmp_I, pcCmp, "Vc:ViAi"} // Compare signed Vint ?s Aint -> Vcond
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{poCmp_L, pcCmp, "Vc:VlAl"} // Compare signed Vlong ?s Along -> Vcond
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{poCmpU_I, pcCmp, "Vc:ViAi"} // Compare unsigned Vint ?u Aint -> Vcond
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{poCmpU_L, pcCmp, "Vc:VlAl"} // Compare unsigned Vlong ?u Along -> Vcond
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{poCmpU_A, pcCmp, "Vc:VaAa"} // Compare unsigned Vaddr ?u Aaddr -> Vcond
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{poFCmp_F, pcFCmp, "Vc:VfAf"} // FP compare Vfloat ? Afloat -> Vcond
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{poFCmp_D, pcFCmp, "Vc:VdAd"} // FP compare Vdouble ? Adouble -> Vcond
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// Cond lt eq gt un
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{poLt_I, pcCond, "Vi:Vc"} // conditional 1 0 0 0 Vcond -> Vint
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{poEq_I, pcCond, "Vi:Vc"} // conditional 0 1 0 0 Vcond -> Vint
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{poLe_I, pcCond, "Vi:Vc"} // conditional 1 1 0 0 Vcond -> Vint
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{poGt_I, pcCond, "Vi:Vc"} // conditional 0 0 1 0 Vcond -> Vint
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{poLgt_I, pcCond, "Vi:Vc"} // conditional 1 0 1 0 Vcond -> Vint
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{poGe_I, pcCond, "Vi:Vc"} // conditional 0 1 1 0 Vcond -> Vint
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{poOrd_I, pcCond, "Vi:Vc"} // conditional 1 1 1 0 Vcond -> Vint
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{poUnord_I, pcCond, "Vi:Vc"} // conditional 0 0 0 1 Vcond -> Vint
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{poULt_I, pcCond, "Vi:Vc"} // conditional 1 0 0 1 Vcond -> Vint
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{poUEq_I, pcCond, "Vi:Vc"} // conditional 0 1 0 1 Vcond -> Vint
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{poULe_I, pcCond, "Vi:Vc"} // conditional 1 1 0 1 Vcond -> Vint
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{poUGt_I, pcCond, "Vi:Vc"} // conditional 0 0 1 1 Vcond -> Vint
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{poNe_I, pcCond, "Vi:Vc"} // conditional 1 0 1 1 Vcond -> Vint
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{poUGe_I, pcCond, "Vi:Vc"} // conditional 0 1 1 1 Vcond -> Vint
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// Cond3 lt eq gt un
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{poCatL_I, pcCond3, "Vi:Vc"} // conditional -1 0 1 -1 Vcond -> Vint
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{poCatG_I, pcCond3, "Vi:Vc"} // conditional -1 0 1 1 Vcond -> Vint
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{poCatCL_I, pcCond3, "Vi:Vc"} // conditional 1 0 -1 -1 Vcond -> Vint
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{poCatCG_I, pcCond3, "Vi:Vc"} // conditional 1 0 -1 1 Vcond -> Vint
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{poChkNull, pcCheck1, "E:Va"} // Throw NullPointerException if null Vaddr -> E
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{poChkCast_I, pcCheck2, "E:ViAi"} // Throw ClassCastException if != Vint, Aint -> E
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{poChkCast_A, pcCheck2, "E:VaAa"} // Throw ClassCastException if != Vaddr, Aaddr -> E
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{poLimit, pcCheck2, "E:AiAi"} // Throw ArrayIndexOutOfBounds if >=u Aint, Aint -> E
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{poLimCast, pcCheck2, "E:ViCi"} // Throw ClassCastException if < Vint, Cint -> E
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{poLd_I, pcLd, "Vi:AmAa"} // Load M, *Aaddr -> Vint
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{poLd_L, pcLd, "Vl:AmAa"} // Load M, *Aaddr -> Vlong
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{poLd_F, pcLd, "Vf:AmAa"} // Load M, *Aaddr -> Vfloat
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{poLd_D, pcLd, "Vd:AmAa"} // Load M, *Aaddr -> Vdouble
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{poLd_A, pcLd, "Va:AmAa"} // Load M, *Aaddr -> Vaddr
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{poLdE_I, pcLd, "EVi:AmVa"} // Load checked M, *Vaddr -> Vint, E
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{poLdE_L, pcLd, "EVl:AmVa"} // Load checked M, *Vaddr -> Vlong, E
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{poLdE_F, pcLd, "EVf:AmVa"} // Load checked M, *Vaddr -> Vfloat, E
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{poLdE_D, pcLd, "EVd:AmVa"} // Load checked M, *Vaddr -> Vdouble, E
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{poLdE_A, pcLd, "EVa:AmVa"} // Load checked M, *Vaddr -> Vaddr, E
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{poLdS_B, pcLd, "Vi:AmAa"} // Load signed byte M, exts(*Aaddr) -> Vint
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{poLdS_H, pcLd, "Vi:AmAa"} // Load signed halfword M, exts(*Aaddr) -> Vint
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{poLdSE_B, pcLd, "EVi:AmVa"} // Load signed checked byte M, exts(*Vaddr) -> Vint, E
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{poLdSE_H, pcLd, "EVi:AmVa"} // Load signed checked halfword M, exts(*Vaddr) -> Vint, E
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{poLdU_B, pcLd, "Vi:AmAa"} // Load unsigned byte M, extu(*Aaddr) -> Vint
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{poLdU_H, pcLd, "Vi:AmAa"} // Load unsigned halfword M, extu(*Aaddr) -> Vint
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{poLdUE_B, pcLd, "EVi:AmVa"} // Load unsigned checked byte M, extu(*Vaddr) -> Vint, E
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{poLdUE_H, pcLd, "EVi:AmVa"} // Load unsigned checked halfword M, extu(*Vaddr) -> Vint, E
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{poLdV_I, pcLd, "T:MAa"} // Load volatile M, *Aaddr -> M, Vint
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{poLdV_L, pcLd, "T:MAa"} // Load volatile M, *Aaddr -> M, Vlong
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{poLdV_F, pcLd, "T:MAa"} // Load volatile M, *Aaddr -> M, Vfloat
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{poLdV_D, pcLd, "T:MAa"} // Load volatile M, *Aaddr -> M, Vdouble
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{poLdV_A, pcLd, "T:MAa"} // Load volatile M, *Aaddr -> M, Vaddr
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{poLdVE_I, pcLd, "ET:MVa"} // Load volatile checked M, *Vaddr -> M, Vint, E
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{poLdVE_L, pcLd, "ET:MVa"} // Load volatile checked M, *Vaddr -> M, Vlong, E
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{poLdVE_F, pcLd, "ET:MVa"} // Load volatile checked M, *Vaddr -> M, Vfloat, E
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{poLdVE_D, pcLd, "ET:MVa"} // Load volatile checked M, *Vaddr -> M, Vdouble, E
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{poLdVE_A, pcLd, "ET:MVa"} // Load volatile checked M, *Vaddr -> M, Vaddr, E
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{poLdVS_B, pcLd, "T:MAa"} // Load volatile signed byte M, exts(*Aaddr) -> M, Vint
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{poLdVS_H, pcLd, "T:MAa"} // Load volatile signed halfword M, exts(*Aaddr) -> M, Vint
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{poLdVSE_B, pcLd, "ET:MVa"} // Load volatile signed checked byte M, exts(*Vaddr) -> M, Vint, E
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{poLdVSE_H, pcLd, "ET:MVa"} // Load volatile signed checked hfwrd M, exts(*Vaddr) -> M, Vint, E
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{poLdVU_B, pcLd, "T:MAa"} // Load volatile unsigned byte M, extu(*Aaddr) -> M, Vint
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{poLdVU_H, pcLd, "T:MAa"} // Load volatile unsigned halfword M, extu(*Aaddr) -> M, Vint
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{poLdVUE_B, pcLd, "ET:MVa"} // Load volatile unsigned checked byte M, extu(*Vaddr) -> M, Vint, E
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{poLdVUE_H, pcLd, "ET:MVa"} // Load volatile unsigned checked hfwrd M, extu(*Vaddr) -> M, Vint, E
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{poSt_B, pcSt, "M:MAaAi"} // Store byte M, Aaddr, Aint -> M
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{poSt_H, pcSt, "M:MAaAi"} // Store halfword M, Aaddr, Aint -> M
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{poSt_I, pcSt, "M:MAaAi"} // Store M, Aaddr, Aint -> M
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{poSt_L, pcSt, "M:MAaAl"} // Store M, Aaddr, Along -> M
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{poSt_F, pcSt, "M:MAaAf"} // Store M, Aaddr, Afloat -> M
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{poSt_D, pcSt, "M:MAaAd"} // Store M, Aaddr, Adouble -> M
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{poSt_A, pcSt, "M:MAaAa"} // Store M, Aaddr, Aaddr -> M
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{poStE_B, pcSt, "EM:MVaAi"} // Store byte checked M, Vaddr, Aint -> M, E
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{poStE_H, pcSt, "EM:MVaAi"} // Store halfword checked M, Vaddr, Aint -> M, E
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{poStE_I, pcSt, "EM:MVaAi"} // Store checked M, Vaddr, Aint -> M, E
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{poStE_L, pcSt, "EM:MVaAl"} // Store checked M, Vaddr, Along -> M, E
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{poStE_F, pcSt, "EM:MVaAf"} // Store checked M, Vaddr, Afloat -> M, E
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{poStE_D, pcSt, "EM:MVaAd"} // Store checked M, Vaddr, Adouble -> M, E
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{poStE_A, pcSt, "EM:MVaAa"} // Store checked M, Vaddr, Aaddr -> M, E
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{poStV_B, pcSt, "M:MAaAi"} // Store volatile byte M, Aaddr, Aint -> M
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{poStV_H, pcSt, "M:MAaAi"} // Store volatile halfword M, Aaddr, Aint -> M
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{poStV_I, pcSt, "M:MAaAi"} // Store volatile M, Aaddr, Aint -> M
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{poStV_L, pcSt, "M:MAaAl"} // Store volatile M, Aaddr, Along -> M
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{poStV_F, pcSt, "M:MAaAf"} // Store volatile M, Aaddr, Afloat -> M
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{poStV_D, pcSt, "M:MAaAd"} // Store volatile M, Aaddr, Adouble -> M
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{poStV_A, pcSt, "M:MAaAa"} // Store volatile M, Aaddr, Aaddr -> M
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{poStVE_B, pcSt, "EM:MVaAi"} // Store volatile byte checked M, Vaddr, Aint -> M, E
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{poStVE_H, pcSt, "EM:MVaAi"} // Store volatile halfword checked M, Vaddr, Aint -> M, E
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{poStVE_I, pcSt, "EM:MVaAi"} // Store volatile checked M, Vaddr, Aint -> M, E
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{poStVE_L, pcSt, "EM:MVaAl"} // Store volatile checked M, Vaddr, Along -> M, E
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{poStVE_F, pcSt, "EM:MVaAf"} // Store volatile checked M, Vaddr, Afloat -> M, E
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{poStVE_D, pcSt, "EM:MVaAd"} // Store volatile checked M, Vaddr, Adouble -> M, E
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{poStVE_A, pcSt, "EM:MVaAa"} // Store volatile checked M, Vaddr, Aaddr -> M, E
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{poMEnter, pcMonitor, "EM:MAa"} // Acquire a monitor M, Aaddr -> M, E
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{poMExit, pcMonitor, "M:MAa"} // Release a monitor M, Aaddr -> M
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{poSync, pcSync, "M:M"} // Memory barrier M -> M
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{poSysCall, pcSysCall, "T:MA@*"} // System call M, ... -> V@
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{poSysCallV, pcSysCall, "T:MA@*"} // Volatile system call M, ... -> M, V@
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{poSysCallC, pcSysCall, "T:A@*"} // Constant system call ... -> V@
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{poSysCallE, pcSysCall, "ET:MA@*"} // System call exc M, ... -> V@, E
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{poSysCallEV, pcSysCall, "ET:MA@*"} // Volatile system call exc M, ... -> M, V@, E
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{poSysCallEC, pcSysCall, "ET:A@*"} // Constant system call exc ... -> V@, E
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{poCall, pcCall, "ET:MAaA@*"} // Function call M, Va, ... -> M, V@, E
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// code generator specific primitives
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{coReg_V, pcNone, ""} // fake register (doesn't exist)
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{coReg_I, pcNone, "Vi:"} // fake register ... -> Vint
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{coReg_L, pcNone, "Vl:"} // fake register ... -> Vlong
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{coReg_F, pcNone, "Vf:"} // fake register ... -> Vfloat
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{coReg_D, pcNone, "Vd:"} // fake register ... -> Vdouble
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{coReg_A, pcNone, "Va:"} // fake register ... -> Vaddr
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{coReg_C, pcNone, "Vc:"} // fake register ... -> Vcond
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{coReg_M, pcNone, "M:"} // fake register ... -> M
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{coReg_T, pcNone, ""} // fake register (doesn't exist)
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