зеркало из https://github.com/mozilla/gecko-dev.git
1299 строки
43 KiB
C++
1299 строки
43 KiB
C++
/* -*- Mode: C++; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*-
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*
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* The contents of this file are subject to the Netscape Public
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* License Version 1.1 (the "License"); you may not use this file
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* except in compliance with the License. You may obtain a copy of
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* the License at http://www.mozilla.org/NPL/
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*
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* Software distributed under the License is distributed on an "AS
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* IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
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* implied. See the License for the specific language governing
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* rights and limitations under the License.
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*
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* The Original Code is mozilla.org code.
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*
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* The Initial Developer of the Original Code is Netscape
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* Communications Corporation. Portions created by Netscape are
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* Copyright (C) 1998 Netscape Communications Corporation. All
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* Rights Reserved.
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*
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* Contributor(s):
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*/
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#define INCLUDE_EMITTER
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#include "CpuInfo.h"
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#include "Fundamentals.h"
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#include "RegisterAllocator.h"
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#include "RegisterAssigner.h"
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#include "Spilling.h"
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#include "InstructionEmitter.h"
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#include "ControlGraph.h"
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#include "Primitives.h"
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#include "VirtualRegister.h"
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#include "FastBitMatrix.h"
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#include "FastBitSet.h"
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#include "CpuInfo.h"
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#include "Attributes.h"
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UT_DEFINE_LOG_MODULE(RegisterAllocator);
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#ifdef DEBUG_LOG
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void printGraph(Uint32 nNodes, ControlNode** dfsList)
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{
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for (Uint32 m = 0; m < nNodes; m++) {
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ControlNode& node = *dfsList[m];
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node.printRef(UT_LOG_MODULE(RegisterAllocator));
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UT_LOG(RegisterAllocator, PR_LOG_ALWAYS, ("\n"));
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DoublyLinkedList<PhiNode>& phiNodes = node.getPhiNodes();
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for (DoublyLinkedList<PhiNode>::iterator p = phiNodes.begin(); !phiNodes.done(p); p = phiNodes.advance(p)) {
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PhiNode& phiNode = phiNodes.get(p);
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ValueKind kind = phiNode.getKind();
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if (isStorableKind(kind))
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if (isDoublewordKind(kind)) {
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UT_LOG(RegisterAllocator, PR_LOG_ALWAYS, ("PhiNode: (%d,%d) <- ", phiNode.getLowVirtualRegisterAnnotation()->getRegisterIndex(),
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phiNode.getHighVirtualRegisterAnnotation()->getRegisterIndex()));
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for (DataConsumer *consumer = phiNode.getInputsBegin(); consumer < phiNode.getInputsEnd(); consumer++)
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UT_LOG(RegisterAllocator, PR_LOG_ALWAYS, ("%d ", consumer->getVariable().getVirtualRegisterAnnotation()->getRegisterIndex()));
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} else {
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UT_LOG(RegisterAllocator, PR_LOG_ALWAYS, ("PhiNode: %d <- ", phiNode.getVirtualRegisterAnnotation()->getRegisterIndex()));
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for (DataConsumer *consumer = phiNode.getInputsBegin(); consumer < phiNode.getInputsEnd(); consumer++)
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UT_LOG(RegisterAllocator, PR_LOG_ALWAYS, ("%d ", consumer->getVariable().getVirtualRegisterAnnotation()->getRegisterIndex()));
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}
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UT_LOG(RegisterAllocator, PR_LOG_ALWAYS, ("\n"));
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}
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InstructionList& instructions = node.getInstructions();
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#ifdef DEBUG_LOG
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for(InstructionList::iterator i = instructions.begin(); !instructions.done(i); i = instructions.advance(i)) {
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instructions.get(i).printDebug(UT_LOG_MODULE(RegisterAllocator));
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UT_LOG(RegisterAllocator, PR_LOG_ALWAYS, ("\n"));
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}
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#endif
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}
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}
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#endif
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/*
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*-------------------------RegisterAllocator.cpp-------------------------
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*
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* RegisterAllocator::allocateRegisters --
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*
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* Register allocation main loop.
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*
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* 1- calculate the interference graph.
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* 2- coalesce the registers (remove uneeded copy instructions).
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* 3- assign a color to each VirtualRegister.
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* 4- spill some VirtualRegisters if (3) failed.
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* 5- goto (1) if (3) failed.
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*
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*-----------------------------------------------------------------------
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*/
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void RegisterAllocator::
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allocateRegisters()
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{
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PRUint32 nVirtualRegisters = vRegManager.count();
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if (nVirtualRegisters == 0)
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{
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// DEBUG_ONLY(UT_LOG(RegisterAllocator, PR_LOG_ALWAYS, ("**** No register allocation needed ****\n");))
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return;
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}
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// DEBUG_ONLY(PRUint32 loopCounter = 0);
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// DEBUG_ONLY(UT_LOG(RegisterAllocator, PR_LOG_ALWAYS, ("**** Allocate Registers ****\n");))
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// Check if all phiNodes have an allocated VirtualRegister for each outgoing edge.
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checkPhiNodesAnnotation();
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// Resolve any VirtualRegister class conflicts.
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checkRegisterClassConflicts();
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do
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{
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while(true)
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{
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// DEBUG_ONLY(UT_LOG(RegisterAllocator, PR_LOG_ALWAYS, ("-- loop %d --\n", ++loopCounter)));
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// We are compacting the VirtualRegister array to minimize the number of bits in the BitSets.
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vRegManager.compactMemory();
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// Build the interference matrix.
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buildInterferenceGraph();
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// remove as many copy instructions as possible.
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coalesce();
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// If we compile a DEBUG target, we want to be sure that the register coalescing
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// didn't forget any register interference.
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DEBUG_ONLY(FastBitMatrix backupMatrix = interferenceMatrix);
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buildInterferenceGraph();
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#ifdef DEBUG
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if (backupMatrix != interferenceMatrix)
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{
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#ifdef DEBUG_LOG
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UT_LOG(RegisterAllocator, PR_LOG_ALWAYS, ("!!!! interference matrix is <> after a 2nd register interference analysis !!!!\n"));
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// backupMatrix.printDiff(stdout, interferenceMatrix);
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#endif
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}
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#endif
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// Reset the registers.
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for (VirtualRegisterManager::iterator i = vRegManager.begin(); !vRegManager.done(i); i = vRegManager.advance(i))
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{
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VirtualRegister& vReg = vRegManager.getVirtualRegister(i);
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vReg.resetColoringInfo();
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FastBitSet inter(interferenceMatrix.getRow(i), nVirtualRegisters);
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vReg.colorInfo.interferenceDegree = inter.countOnes();
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}
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// Calculate each register's spill cost.
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calculateSpillCosts();
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if (!registerAssigner.assignRegisters(interferenceMatrix))
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{
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spilling.insertSpillCode(dfsList, nNodes);
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spillPhiNodes();
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}
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else
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break;
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}
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}
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while (removePhiNodes());
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// Update the info in the LocalVariableEntry mappings
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updateLocalVariableTable();
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// DEBUG_ONLY(printRegisterDebug(stdout, true));
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}
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/*
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*-------------------------RegisterAllocator.cpp-------------------------
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*
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* RegisterAllocator::checkPhiNodesAnnotation --
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*
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* Check if the phi nodes have valid register annotations.
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*
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*-----------------------------------------------------------------------
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*/
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void RegisterAllocator::
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checkPhiNodesAnnotation()
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{
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for (PRUint32 n = 0; n < nNodes; n++)
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{
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ControlNode& node = *dfsList[n];
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DoublyLinkedList<PhiNode>& phiNodes = node.getPhiNodes();
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for (DoublyLinkedList<PhiNode>::iterator i = phiNodes.begin(); !phiNodes.done(i); i = phiNodes.advance(i))
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{
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PhiNode& phiNode = phiNodes.get(i);
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ValueKind kind = phiNode.getKind();
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if (isStorableKind(kind))
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{
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DataNode& producer = phiNode;
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if (isDoublewordKind(kind)) {
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// Check the outgoing edge.
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if (producer.getLowVirtualRegisterAnnotation() == NULL)
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producer.annotateLow(vRegManager.newVirtualRegister(), vrcInteger /* FIXME */);
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if (producer.getHighVirtualRegisterAnnotation() == NULL)
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producer.annotateHigh(vRegManager.newVirtualRegister(), vrcInteger /* FIXME */);
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// Check the incoming edges.
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DataConsumer* limit = phiNode.getInputsEnd();
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for (DataConsumer *consumer = phiNode.getInputsBegin(); consumer < limit; consumer++)
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{
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DataNode& p = consumer->getVariable();
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if (p.getLowVirtualRegisterAnnotation() == NULL)
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p.annotateLow(vRegManager.newVirtualRegister(), vrcInteger /* FIXME */);
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if (p.getHighVirtualRegisterAnnotation() == NULL)
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p.annotateHigh(vRegManager.newVirtualRegister(), vrcInteger /* FIXME */);
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}
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} else {
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// Check the outgoing edge.
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if (producer.getVirtualRegisterAnnotation() == NULL)
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producer.annotate(vRegManager.newVirtualRegister(), vrcInteger /* FIXME */);
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// Check the incoming edges.
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DataConsumer* limit = phiNode.getInputsEnd();
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for (DataConsumer *consumer = phiNode.getInputsBegin(); consumer < limit; consumer++)
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{
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DataNode& p = consumer->getVariable();
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if (p.getVirtualRegisterAnnotation() == NULL)
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p.annotate(vRegManager.newVirtualRegister(), vrcInteger /* FIXME */);
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}
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}
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}
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}
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}
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}
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/*
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*-------------------------RegisterAllocator.cpp-------------------------
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*
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* RegisterAllocator::checkRegisterClassConflicts --
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*
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* Check that each instruction will get the correct kind of register.
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*
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*-----------------------------------------------------------------------
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*/
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void RegisterAllocator::
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checkRegisterClassConflicts()
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{
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#if GENERATE_FOR_HPPA
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// FIXME
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// Reset all equivalents registers for the VirtualRegisters.
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for (VirtualRegisterManager::iterator i = vRegManager.begin(); !vRegManager.done(i); i = vRegManager.advance(i))
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fill_n(vRegManager.getVirtualRegister(i).equivalentRegister, nVRClass, (VirtualRegister *) 0);
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for (PRUint32 n = 0; n < nNodes; n++)
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{
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ControlNode& node = *dfsList[n];
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InstructionList& instructions = node.getInstructions();
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for (InstructionList::iterator i = instructions.end(); !instructions.done(i); i = instructions.retreat(i))
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{
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Instruction& instruction = instructions.get(i);
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InstructionUse* useBegin = instruction.getInstructionUseBegin();
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InstructionUse* useEnd = instruction.getInstructionUseEnd();
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InstructionUse* usePtr;
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for (usePtr = useBegin; usePtr < useEnd; usePtr++)
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if (usePtr->isVirtualRegister())
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{
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VirtualRegister& vReg = usePtr->getVirtualRegister();
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VirtualRegisterPtr& vRegPtr = usePtr->getVirtualRegisterPtr();
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VRClass wanted = vRegPtr.getClassConstraint();
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VRClass current = vReg.getClass();
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if (wanted != current)
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{
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if (vReg.equivalentRegister[wanted] == NULL)
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{
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Instruction& definingInstruction = *vReg.getDefiningInstruction();
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vReg.equivalentRegister[wanted] = &vRegManager.newVirtualRegister(wanted);
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instructionEmitter.emitCopyAfter(*definingInstruction.getPrimitive(), &definingInstruction.getLinks(),
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vReg, *vReg.equivalentRegister[wanted]);
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}
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vRegPtr.initialize(*vReg.equivalentRegister[wanted], wanted);
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}
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}
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}
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}
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#endif
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}
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/*
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*-------------------------RegisterAllocator.cpp-------------------------
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*
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* RegisterAllocator::buildInterferenceGraph --
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*
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* Build the interferenceMatrix. Each bit in the interferenceMatrix
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* corresponds to a register interference.
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*
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*-----------------------------------------------------------------------
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*/
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void RegisterAllocator::
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buildInterferenceGraph()
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{
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PRUint32 nVirtualRegisters = vRegManager.count();
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// Reset the Bitsets in each ControlNode.
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for (PRUint32 n = 0; n < nNodes; n++)
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{
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dfsList[n]->liveAtBegin.sizeToAndClear(nVirtualRegisters);
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dfsList[n]->liveAtEnd.sizeToAndClear(nVirtualRegisters);
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dfsList[n]->hasNewLiveAtEnd = true;
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dfsList[n]->liveAtBeginIsValid = false;
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}
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// Reset the liveness info.
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for (VirtualRegisterManager::iterator i = vRegManager.begin(); !vRegManager.done(i); i = vRegManager.advance(i)) {
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VirtualRegister& vReg = vRegManager.getVirtualRegister(i);
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vReg.liveness.sizeToAndClear(nNodes);
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if (vReg.hasSpecialInterference) {
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vReg.specialInterference.clear();;
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}
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}
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// Reset the interference matrix.
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interferenceMatrix.sizeToAndClear(nVirtualRegisters, nVirtualRegisters);
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// Bitset of the VirtualRegisters currently alive.
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FastBitSet currentLive(nVirtualRegisters);
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// Bitset of the VirtualRegisters alive at the end of a node.
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FastBitSet liveAtEnd(nVirtualRegisters);
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for (bool loop = true; loop;)
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{
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loop = false;
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for (PRInt32 n = (nNodes - 1); n >= 0; n--)
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{
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ControlNode& node = *dfsList[n];
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bool hasPhiNodes = !node.getPhiNodes().empty();
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// If liveAtEnd didn't change there's no new interferences to find. Just skip this node.
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if ((!node.hasNewLiveAtEnd) && node.liveAtBeginIsValid)
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continue;
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node.hasNewLiveAtEnd = false;
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currentLive = node.liveAtEnd;
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// All the virtual registers in currentLive are alive in this node.
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for (PRInt32 k = currentLive.firstOne(); k != -1; k = currentLive.nextOne(k))
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vRegManager.getVirtualRegister(k).liveness.set(n);
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// We walk backward all the instructions defined in this node.
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// A register becomes alive with its last use (first found), interfere with
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// all the registers alive at its definition, and is killed by its definition.
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InstructionList& instructions = node.getInstructions();
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for (InstructionList::iterator i = instructions.end(); !instructions.done(i);
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i = instructions.retreat(i))
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{
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Instruction& instruction = instructions.get(i);
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InstructionUse* useBegin = instruction.getInstructionUseBegin();
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InstructionUse* useEnd = instruction.getInstructionUseEnd();
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InstructionUse* usePtr;
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InstructionDefine* defBegin = instruction.getInstructionDefineBegin();
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InstructionDefine* defEnd = instruction.getInstructionDefineEnd();
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InstructionDefine* defPtr;
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InstructionFlags flags = instruction.getFlags();
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if (flags & ifCopy)
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{
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// Move is handled specially to avoid adding an interference between the
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// source and the destination. If an interference exists between these
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// registers another instruction will set it. For now the source register
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// and the destination register will contain the same value.
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PR_ASSERT(useBegin[0].isVirtualRegister());
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currentLive.clear(useBegin[0].getRegisterIndex());
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}
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// Registers are defined. This definition has an interference with all the
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// registers currently alive.
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for (defPtr = defBegin; defPtr < defEnd; defPtr++)
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if (defPtr->isVirtualRegister())
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{
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VirtualRegister& defReg = defPtr->getVirtualRegister();
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PRUint32 defRegIndex = defReg.getRegisterIndex();
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interferenceMatrix.orRow(defRegIndex, currentLive);
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// We use the definition of this register to update the precoloring information.
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// In a program we can have different VirtualRegisters precolored to the same color.
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// During the register coalescing we need to know if a non-precolored register can
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// be coalesced with a precolored to C. It is possible to do so only if the non
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// precolored register has no interference with any other register also precolored to C.
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// For this reason the VirtualRegisterManager will create a PseudoVirtualRegister corresponding
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// to one machine register. As the Pseudo VirtualRegister is never seen by the interference graph
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// algorithm we can use the row corresponding to its index to store the index of all VirtualRegisters
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// precolored to the color C.
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if (defReg.isPreColored())
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interferenceMatrix.set(defReg.colorInfo.preColoredRegisterIndex, defRegIndex);
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}
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// The definition just killed these registers.
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for (defPtr = defBegin; defPtr < defEnd; defPtr++)
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if (defPtr->isVirtualRegister())
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currentLive.clear(defPtr->getRegisterIndex());
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// If this instruction is a Call instruction, we want all the caller-save
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// registers to interfere with the current live registers. We do not want an
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// interference with the callee-save registers because the call will save &
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// restore these registers.
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if (flags & ifCall)
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{
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for (PRInt32 r = currentLive.firstOne(); r != -1; r = currentLive.nextOne(r))
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{
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VirtualRegister& vReg = vRegManager.getVirtualRegister(r);
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if (!vReg.hasSpecialInterference)
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{
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vReg.specialInterference.sizeToAndClear(NUMBER_OF_REGISTERS);
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vReg.hasSpecialInterference = true;
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}
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vReg.specialInterference.set(FIRST_CALLER_SAVED_GR, LAST_CALLER_SAVED_GR);
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#if NUMBER_OF_FPREGISTERS != 0
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vReg.specialInterference.set(FIRST_CALLER_SAVED_FPR, LAST_CALLER_SAVED_FPR);
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#endif
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}
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}
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#if FIXME
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if (flags & ifSpecialCall)
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{
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}
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#endif
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// Each use of a register makes it alive.
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for (usePtr = useBegin; usePtr < useEnd; usePtr++)
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if (usePtr->isVirtualRegister())
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{
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VirtualRegister& vReg = usePtr->getVirtualRegister();
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currentLive.set(vReg.getRegisterIndex());
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vReg.liveness.set(n);
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}
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}
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if (currentLive != node.liveAtBegin)
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{
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const DoublyLinkedList<ControlEdge>& predecessors = node.getPredecessors();
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PRUint32 edgeIndex = 0;
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for (DoublyLinkedList<ControlEdge>::iterator i = predecessors.begin(); !predecessors.done(i); i = predecessors.advance(i), edgeIndex++)
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{
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ControlNode& predecessor = predecessors.get(i).getSource();
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if (hasPhiNodes)
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{
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// Add liveness information for the phi nodes.
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liveAtEnd = currentLive;
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DoublyLinkedList<PhiNode>& phiNodes = node.getPhiNodes();
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for (DoublyLinkedList<PhiNode>::iterator p = phiNodes.end(); !phiNodes.done(p); p = phiNodes.retreat(p)) {
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PhiNode& phiNode = phiNodes.get(p);
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ValueKind kind = phiNode.getKind();
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if (isStorableKind(kind)) {
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PRUint32 in = phiNode.nthInput(edgeIndex).getVariable().getVirtualRegisterAnnotation()->getRegisterIndex();
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PRUint32 out = phiNode.getVirtualRegisterAnnotation()->getRegisterIndex();
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if (in != out) {
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// Handled like a Copy Instruction.
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liveAtEnd.clear(in);
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interferenceMatrix.orRow(out, liveAtEnd);
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liveAtEnd.clear(out);
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liveAtEnd.set(in);
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VirtualRegister& outVR = *phiNode.getVirtualRegisterAnnotation();
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if (outVR.isPreColored())
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interferenceMatrix.set(outVR.colorInfo.preColoredRegisterIndex, out);
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}
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if (isDoublewordKind(kind)) {
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in = phiNode.nthInput(edgeIndex).getVariable().getHighVirtualRegisterAnnotation()->getRegisterIndex();
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out = phiNode.getHighVirtualRegisterAnnotation()->getRegisterIndex();
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if (in != out) {
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// Handled like a Copy Instruction.
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liveAtEnd.clear(in);
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interferenceMatrix.orRow(out, liveAtEnd);
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||
liveAtEnd.clear(out);
|
||
liveAtEnd.set(in);
|
||
|
||
VirtualRegister& outVR = *phiNode.getHighVirtualRegisterAnnotation();
|
||
if (outVR.isPreColored())
|
||
interferenceMatrix.set(outVR.colorInfo.preColoredRegisterIndex, out);
|
||
}
|
||
}
|
||
}
|
||
}
|
||
bool changed = predecessor.liveAtEnd.setAndTest(liveAtEnd);
|
||
predecessor.hasNewLiveAtEnd |= changed;
|
||
loop |= changed;
|
||
} else { /* !hasPhiNodes */
|
||
bool changed = predecessor.liveAtEnd.setAndTest(currentLive);
|
||
predecessor.hasNewLiveAtEnd |= changed;
|
||
loop |= changed;
|
||
}
|
||
}
|
||
}
|
||
node.liveAtBegin = currentLive;
|
||
node.liveAtBeginIsValid = true;
|
||
}
|
||
}
|
||
|
||
FastBitSet gReg(regAllocPool, nVirtualRegisters);
|
||
FastBitSet fpReg(regAllocPool, nVirtualRegisters);
|
||
FastBitSet ssReg(regAllocPool, nVirtualRegisters);
|
||
VirtualRegisterManager::iterator r;
|
||
|
||
for (r = vRegManager.begin(); !vRegManager.done(r); r = vRegManager.advance(r))
|
||
{
|
||
VirtualRegister& vReg = vRegManager.getVirtualRegister(r);
|
||
switch (vReg.getClass())
|
||
{
|
||
case vrcInteger:
|
||
gReg.set(r);
|
||
break;
|
||
case vrcFloatingPoint:
|
||
case vrcFixedPoint:
|
||
fpReg.set(r);
|
||
break;
|
||
case vrcStackSlot:
|
||
ssReg.set(r);
|
||
break;
|
||
default:
|
||
PR_ASSERT(false);
|
||
}
|
||
}
|
||
for (r = vRegManager.begin(); !vRegManager.done(r); r = vRegManager.advance(r))
|
||
{
|
||
VirtualRegister& vReg = vRegManager.getVirtualRegister(r);
|
||
switch (vReg.getClass())
|
||
{
|
||
case vrcInteger:
|
||
interferenceMatrix.andRow(r, gReg);
|
||
break;
|
||
case vrcFloatingPoint:
|
||
case vrcFixedPoint:
|
||
interferenceMatrix.andRow(r, fpReg);
|
||
break;
|
||
case vrcStackSlot:
|
||
interferenceMatrix.andRow(r, ssReg);
|
||
break;
|
||
default:
|
||
PR_ASSERT(false);
|
||
}
|
||
}
|
||
|
||
FastBitMatrix trans(regAllocPool, nVirtualRegisters, nVirtualRegisters);
|
||
for (r = vRegManager.begin(); !vRegManager.done(r); r = vRegManager.advance(r))
|
||
{
|
||
interferenceMatrix.clear(r, r);
|
||
FastBitSet row(interferenceMatrix.getRow(r), nVirtualRegisters);
|
||
for (PRInt32 i = row.firstOne(); i != -1; i = row.nextOne(i))
|
||
trans.set(i, r);
|
||
}
|
||
for (r = vRegManager.begin(); !vRegManager.done(r); r = vRegManager.advance(r))
|
||
{
|
||
FastBitSet row(trans.getRow(r), nVirtualRegisters);
|
||
interferenceMatrix.orRow(r, row);
|
||
}
|
||
|
||
}
|
||
|
||
|
||
/*
|
||
*-------------------------RegisterAllocator.cpp-------------------------
|
||
*
|
||
* RegisterAllocator::canCoalesceRegisters --
|
||
*
|
||
* Return true if it is possible to coalesce inVr & outVr. If it is
|
||
* from & to will contain the register indexes to coalesce.
|
||
*
|
||
*-----------------------------------------------------------------------
|
||
*/
|
||
bool RegisterAllocator::
|
||
canCoalesceRegisters(VirtualRegister& inVR, VirtualRegister& outVR, PRUint32& from, PRUint32& to)
|
||
{
|
||
// We dont have to check the register class because if a Copy instruction
|
||
// is emitted then in & out have the same register class.
|
||
|
||
from = inVR.getRegisterIndex();
|
||
to = outVR.getRegisterIndex();
|
||
bool inIsPreColored = inVR.isPreColored();
|
||
bool outIsPreColored = outVR.isPreColored();
|
||
|
||
if (inIsPreColored && outIsPreColored)
|
||
{
|
||
// The only case where we can remove this copy is if this two registers
|
||
// have the same color.
|
||
if ((inVR.getPreColor() == outVR.getPreColor()) && !interferenceMatrix.test(from, to))
|
||
{
|
||
if (from != to)
|
||
interferenceMatrix.clear(inVR.colorInfo.preColoredRegisterIndex, from);
|
||
return true;
|
||
}
|
||
}
|
||
else if (inIsPreColored) // && (!outIsPreColored)
|
||
{
|
||
// outVR is not precolored but cannot have an interference with any registers preColored to inPreColor.
|
||
if (outVR.hasSpecialInterference)
|
||
if (outVR.specialInterference.test(inVR.getPreColor()))
|
||
return false;
|
||
|
||
if (!interferenceMatrix.test(to, interferenceMatrix.getRow(inVR.colorInfo.preColoredRegisterIndex)))
|
||
{
|
||
// We must swap in & out, because inVR must stay preColored.
|
||
PRUint32 tmp = to; to = from; from = tmp;
|
||
return true;
|
||
}
|
||
}
|
||
else if (outIsPreColored) // && (!inIsPreColored)
|
||
{
|
||
if (inVR.hasSpecialInterference)
|
||
if (inVR.specialInterference.test(outVR.getPreColor()))
|
||
return false;
|
||
|
||
// inVR is not precolored but cannot have an interference with any registers preColored to outPreColor.
|
||
if (!interferenceMatrix.test(from, interferenceMatrix.getRow(outVR.colorInfo.preColoredRegisterIndex)))
|
||
return true;
|
||
}
|
||
else // (!inIsPreColored && !outIsPreColored)
|
||
{
|
||
if ((from == to) || !interferenceMatrix.test(from, to))
|
||
return true;
|
||
}
|
||
return false;
|
||
}
|
||
|
||
|
||
/*
|
||
*-------------------------RegisterAllocator.cpp-------------------------
|
||
*
|
||
* RegisterAllocator::coalesceRegisters --
|
||
*
|
||
* Coalesce registers at indexes in & out. Update the interference
|
||
* matrix.
|
||
*
|
||
*-----------------------------------------------------------------------
|
||
*/
|
||
inline void RegisterAllocator::
|
||
coalesceRegisters(PRUint32 from, PRUint32 to)
|
||
{
|
||
PRUint32 nVirtualRegisters = vRegManager.count();
|
||
FastBitSet row(interferenceMatrix.getRow(from), nVirtualRegisters);
|
||
for (PRInt32 r = row.firstOne(); r != -1; r = row.nextOne(r))
|
||
{
|
||
interferenceMatrix.clear(r, from);
|
||
interferenceMatrix.set(r, to);
|
||
}
|
||
interferenceMatrix.orRow(to, row);
|
||
DEBUG_ONLY(interferenceMatrix.clearRow(from));
|
||
|
||
// update the liveness info.
|
||
VirtualRegister& fromVR = vRegManager.getVirtualRegister(from);
|
||
VirtualRegister& toVR = vRegManager.getVirtualRegister(to);
|
||
|
||
FastBitSet& liveness = fromVR.liveness;
|
||
for (PRInt32 i = liveness.firstOne(); i != -1; i = liveness.nextOne(i))
|
||
{
|
||
dfsList[i]->liveAtEnd.clear(from);
|
||
dfsList[i]->liveAtEnd.set(to);
|
||
}
|
||
toVR.liveness |= liveness;
|
||
|
||
if (fromVR.hasSpecialInterference) {
|
||
if (toVR.hasSpecialInterference)
|
||
toVR.specialInterference |= fromVR.specialInterference;
|
||
else {
|
||
toVR.specialInterference.sizeTo(NUMBER_OF_REGISTERS);
|
||
toVR.specialInterference = fromVR.specialInterference;
|
||
}
|
||
toVR.hasSpecialInterference = true;
|
||
}
|
||
|
||
vRegManager.moveVirtualRegister(from, to);
|
||
}
|
||
|
||
|
||
/*
|
||
*-------------------------RegisterAllocator.cpp-------------------------
|
||
*
|
||
* RegisterAllocator::coalesce --
|
||
*
|
||
* Check all Copy instructions & phiNodes for possible register
|
||
* coalescing. If two registers are coalesced there's no need to
|
||
* keep the instruction (or the phiNode). The ControlFlow graph
|
||
* is analysed from the most executed node to the least.
|
||
*
|
||
* TODO: loop nesting depth is not good enough (should analyse
|
||
* the program regions instead).
|
||
*
|
||
*-----------------------------------------------------------------------
|
||
*/
|
||
void
|
||
RegisterAllocator::coalesce()
|
||
{
|
||
for (PRInt32 n = nNodes - 1; n >= 0; n--)
|
||
{
|
||
ControlNode& node = *lndList[n];
|
||
|
||
InstructionList& instructions = node.getInstructions();
|
||
InstructionList::iterator i = instructions.begin();
|
||
|
||
// Check the instructions in this node.
|
||
while(!instructions.done(i))
|
||
{
|
||
Instruction& insn = instructions.get(i);
|
||
// We might remove this instruction. It is necessary to advance the iterator
|
||
// before the remove.
|
||
i = instructions.advance(i);
|
||
|
||
if (insn.getFlags() & ifCopy)
|
||
{
|
||
PR_ASSERT(insn.getInstructionUseBegin()[0].isVirtualRegister() && insn.getInstructionDefineBegin()[0].isVirtualRegister());
|
||
|
||
VirtualRegister& inVR = insn.getInstructionUseBegin()[0].getVirtualRegister();
|
||
VirtualRegister& outVR = insn.getInstructionDefineBegin()[0].getVirtualRegister();
|
||
PRUint32 from, to;
|
||
|
||
if (canCoalesceRegisters(inVR, outVR, from, to))
|
||
{
|
||
if (from != to)
|
||
coalesceRegisters(from, to);
|
||
|
||
// Before removing the instruction, we unitialize the VirtualRegisterPtrs in its annotations.
|
||
insn.unlinkRegisters();
|
||
insn.remove();
|
||
}
|
||
}
|
||
}
|
||
|
||
// Check the phiNodes in this node.
|
||
DoublyLinkedList<PhiNode>& phiNodes = node.getPhiNodes();
|
||
for (DoublyLinkedList<PhiNode>::iterator p = phiNodes.end(); !phiNodes.done(p);)
|
||
{
|
||
PhiNode& phiNode = phiNodes.get(p);
|
||
ValueKind kind = phiNode.getKind();
|
||
p = phiNodes.retreat(p);
|
||
|
||
if (isStorableKind(kind))
|
||
{
|
||
bool removePhiNode = true;
|
||
DataConsumer* limit = phiNode.getInputsEnd();
|
||
|
||
for (DataConsumer *consumer = phiNode.getInputsBegin(); consumer < limit; consumer++)
|
||
{
|
||
VirtualRegister* inVR = consumer->getVariable().getVirtualRegisterAnnotation();
|
||
VirtualRegister* outVR = phiNode.getVirtualRegisterAnnotation();
|
||
PRUint32 from, to;
|
||
|
||
if (inVR->getClass() == outVR->getClass()) {
|
||
if (inVR != outVR) {
|
||
if (canCoalesceRegisters(*inVR, *outVR, from, to))
|
||
coalesceRegisters(from, to);
|
||
else
|
||
removePhiNode = false;
|
||
}
|
||
} else
|
||
removePhiNode = false;
|
||
|
||
if (isDoublewordKind(kind)) {
|
||
inVR = consumer->getVariable().getHighVirtualRegisterAnnotation();
|
||
outVR = phiNode.getHighVirtualRegisterAnnotation();
|
||
|
||
if (inVR->getClass() == outVR->getClass()) {
|
||
if (inVR != outVR) {
|
||
if (canCoalesceRegisters(*inVR, *outVR, from, to))
|
||
coalesceRegisters(from, to);
|
||
else
|
||
removePhiNode = false;
|
||
}
|
||
} else
|
||
removePhiNode = false;
|
||
}
|
||
}
|
||
if (removePhiNode)
|
||
phiNode.remove();
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
|
||
/*
|
||
*-------------------------RegisterAllocator.cpp-------------------------
|
||
*
|
||
* RegisterAllocator::spillPhiNodes --
|
||
*
|
||
* Replace the phiNodes spilled VirtualRegisters by their StackSlot
|
||
* equivalent.
|
||
*
|
||
*-----------------------------------------------------------------------
|
||
*/
|
||
void RegisterAllocator::
|
||
spillPhiNodes()
|
||
{
|
||
for (PRUint32 n = 0; n < nNodes; n++)
|
||
{
|
||
ControlNode& node = *dfsList[n];
|
||
DoublyLinkedList<PhiNode>& phiNodes = node.getPhiNodes();
|
||
|
||
for (DoublyLinkedList<PhiNode>::iterator i = phiNodes.begin(); !phiNodes.done(i); i = phiNodes.advance(i))
|
||
{
|
||
PhiNode& phiNode = phiNodes.get(i);
|
||
ValueKind kind = phiNode.getKind();
|
||
if (isStorableKind(kind))
|
||
{
|
||
DataNode& producer = phiNode;
|
||
|
||
if (isDoublewordKind(kind)) {
|
||
VirtualRegister& lowOutVR = *producer.getLowVirtualRegisterAnnotation();
|
||
VirtualRegister& highOutVR = *producer.getHighVirtualRegisterAnnotation();
|
||
|
||
// Check the outgoing edge.
|
||
if (lowOutVR.spillInfo.willSpill)
|
||
producer.getLowVirtualRegisterPtrAnnotation().initialize(*lowOutVR.equivalentRegister[vrcStackSlot]);
|
||
if (highOutVR.spillInfo.willSpill)
|
||
producer.getHighVirtualRegisterPtrAnnotation().initialize(*highOutVR.equivalentRegister[vrcStackSlot]);
|
||
|
||
// Check the incoming edges.
|
||
DataConsumer* limit = phiNode.getInputsEnd();
|
||
for (DataConsumer *consumer = phiNode.getInputsBegin(); consumer < limit; consumer++)
|
||
{
|
||
VirtualRegister& lowInVR = *consumer->getVariable().getLowVirtualRegisterAnnotation();
|
||
VirtualRegister& highInVR = *consumer->getVariable().getHighVirtualRegisterAnnotation();
|
||
if (lowInVR.spillInfo.willSpill)
|
||
consumer->getVariable().getLowVirtualRegisterPtrAnnotation().initialize(*lowInVR.equivalentRegister[vrcStackSlot]);
|
||
if (highInVR.spillInfo.willSpill)
|
||
consumer->getVariable().getHighVirtualRegisterPtrAnnotation().initialize(*highInVR.equivalentRegister[vrcStackSlot]);
|
||
}
|
||
} else {
|
||
VirtualRegister& outVR = *producer.getVirtualRegisterAnnotation();
|
||
|
||
// Check the outgoing edge.
|
||
if (outVR.spillInfo.willSpill)
|
||
producer.getVirtualRegisterPtrAnnotation().initialize(*outVR.equivalentRegister[vrcStackSlot]);
|
||
|
||
// Check the incoming edges.
|
||
DataConsumer* limit = phiNode.getInputsEnd();
|
||
for (DataConsumer *consumer = phiNode.getInputsBegin(); consumer < limit; consumer++)
|
||
{
|
||
VirtualRegister& inVR = *consumer->getVariable().getVirtualRegisterAnnotation();
|
||
if (inVR.spillInfo.willSpill)
|
||
consumer->getVariable().getVirtualRegisterPtrAnnotation().initialize(*inVR.equivalentRegister[vrcStackSlot]);
|
||
}
|
||
}
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
|
||
/*
|
||
*-------------------------RegisterAllocator.cpp-------------------------
|
||
*
|
||
* RegisterAllocator::removePhiNodes --
|
||
*
|
||
* Replace the phiNodes by copy instructions.
|
||
*
|
||
*-----------------------------------------------------------------------
|
||
*/
|
||
bool RegisterAllocator::
|
||
removePhiNodes()
|
||
{
|
||
bool addedNode = false;
|
||
bool needsRebuild = false;
|
||
|
||
for (PRUint32 n = 0; n < nNodes; n++)
|
||
{
|
||
ControlNode& node = *dfsList[n];
|
||
DoublyLinkedList<PhiNode>& phiNodes = node.getPhiNodes();
|
||
|
||
if (phiNodes.empty())
|
||
continue;
|
||
|
||
const DoublyLinkedList<ControlEdge>& predecessors = node.getPredecessors();
|
||
bool hasOneInput = predecessors.lengthIs(1);
|
||
|
||
DoublyLinkedList<PhiNode>::iterator i;
|
||
// If this node has only one predecessor, it is possible to insert the copy instruction
|
||
// at the begininig of this node. To respect the interference order, we have to append
|
||
// each phiNode in the same order they are in the linked list.
|
||
for (i = hasOneInput ? phiNodes.end() : phiNodes.begin(); !phiNodes.done(i);)
|
||
{
|
||
PhiNode& phiNode = phiNodes.get(i);
|
||
ValueKind kind = phiNode.getKind();
|
||
i = hasOneInput ? phiNodes.retreat(i) : phiNodes.advance(i);
|
||
|
||
if (isStorableKind(kind))
|
||
{
|
||
VirtualRegister* lowOutVR = phiNode.getVirtualRegisterAnnotation();
|
||
VirtualRegister* highOutVR = isDoublewordKind(kind) ? phiNode.getHighVirtualRegisterAnnotation() : (VirtualRegister *) 0;
|
||
DoublyLinkedList<ControlEdge>::iterator e = predecessors.begin();
|
||
|
||
DataConsumer* limit = phiNode.getInputsEnd();
|
||
for (DataConsumer *consumer = phiNode.getInputsBegin(); consumer < limit; consumer++)
|
||
{
|
||
// For each consumer.
|
||
ControlEdge& edge = predecessors.get(e);
|
||
e = predecessors.advance(e);
|
||
|
||
for (int w = 1; w <= 2; w++) {
|
||
if (w == 2 && highOutVR == NULL)
|
||
break;
|
||
|
||
VirtualRegister* inVR = (w == 1) ? consumer->getVariable().getLowVirtualRegisterAnnotation() :
|
||
consumer->getVariable().getHighVirtualRegisterAnnotation();
|
||
VirtualRegister* outVR = (w == 1) ? lowOutVR : highOutVR;
|
||
|
||
if (inVR != outVR)
|
||
{
|
||
// We have to emit a Copy from inVR to outVR.
|
||
|
||
InstructionList::iterator place; // where to append the copyInstruction.
|
||
|
||
if (hasOneInput)
|
||
{
|
||
// append at the begining of this node.
|
||
place = node.getInstructions().begin()->prev;
|
||
}
|
||
else
|
||
{
|
||
ControlNode& source = edge.getSource();
|
||
if (source.nSuccessors() != 1)
|
||
{
|
||
// This predecessor has more than one outgoing edge. We need to add
|
||
// a new control Block to insert the copy instruction.
|
||
ControlNode& cn = edge.getSource().controlGraph.newControlNode();
|
||
cn.setControlBlock();
|
||
ControlEdge& newEdge = cn.getNormalSuccessor();
|
||
|
||
newEdge.substituteTarget(edge);
|
||
cn.addPredecessor(edge);
|
||
|
||
// append at the begin of this new node.
|
||
place = cn.getInstructions().begin();
|
||
addedNode = true;
|
||
}
|
||
else
|
||
{
|
||
// append at the end of the corresponding predecessor node.
|
||
place = edge.getSource().getInstructions().end();
|
||
}
|
||
}
|
||
|
||
VRClass inClass = inVR->getClass();
|
||
VRClass outClass = outVR->getClass();
|
||
|
||
if ((inClass == vrcStackSlot) && ((outClass == vrcStackSlot)))
|
||
{
|
||
// Both register are spilled. We have to load the value in memory and then
|
||
// store it at its destination. To do this we need to create a new temporary
|
||
// VirtualRegister. It might create some new interferences, so we have to
|
||
// do one more register allocation loop.
|
||
VirtualRegister& vReg = vRegManager.newVirtualRegister();
|
||
instructionEmitter.emitStoreAfter(phiNode, place, vReg, *outVR);
|
||
instructionEmitter.emitLoadAfter(phiNode, place, vReg, *inVR);
|
||
needsRebuild = true;
|
||
}
|
||
else if (inClass == vrcStackSlot)
|
||
// outVR needs to be loaded.
|
||
instructionEmitter.emitLoadAfter(phiNode, place, *outVR, *inVR);
|
||
else if (outClass == vrcStackSlot)
|
||
// inVR needs to be stored.
|
||
instructionEmitter.emitStoreAfter(phiNode, place, *inVR, *outVR);
|
||
else
|
||
// None of them are spilled, it's a regular copy
|
||
// (!!! inVR & outVR might not have the same register class)
|
||
needsRebuild |= instructionEmitter.emitCopyAfter(phiNode, place, *inVR, *outVR);
|
||
}
|
||
}
|
||
}
|
||
phiNode.remove();
|
||
}
|
||
}
|
||
}
|
||
|
||
if (addedNode)
|
||
{
|
||
ControlGraph& cg = dfsList[0]->controlGraph;
|
||
cg.dfsSearch();
|
||
|
||
if (needsRebuild) {
|
||
nNodes = cg.nNodes;
|
||
dfsList = cg.dfsList;
|
||
cg.lndSearch();
|
||
lndList = cg.lndList;
|
||
}
|
||
}
|
||
|
||
return needsRebuild;
|
||
}
|
||
|
||
|
||
/*
|
||
*-------------------------RegisterAllocator.cpp-------------------------
|
||
*
|
||
* RegisterAllocator::calculateSpillCost --
|
||
*
|
||
* In order to do a graph coloring, we need to get the spill cost of
|
||
* each VirtualRegister used in this program.
|
||
*
|
||
*-----------------------------------------------------------------------
|
||
*/
|
||
void
|
||
RegisterAllocator::calculateSpillCosts()
|
||
{
|
||
PRUint32 nVirtualRegisters = vRegManager.count();
|
||
FastBitSet needLoad(nVirtualRegisters);
|
||
FastBitSet currentLive(nVirtualRegisters);
|
||
FastBitSet mustSpill(nVirtualRegisters);
|
||
|
||
for (PRInt32 n = nNodes - 1; n >=0; n--)
|
||
{
|
||
ControlNode& node = *dfsList[n];
|
||
|
||
needLoad.clear();
|
||
currentLive = node.liveAtEnd;
|
||
mustSpill = currentLive;
|
||
|
||
// Get the copy information about the phiNodes in this node.
|
||
DoublyLinkedList<PhiNode>& phiNodes = node.getPhiNodes();
|
||
for (DoublyLinkedList<PhiNode>::iterator i = phiNodes.begin(); !phiNodes.done(i); i = phiNodes.advance(i))
|
||
{
|
||
PhiNode& phiNode = phiNodes.get(i);
|
||
ValueKind kind = phiNode.getKind();
|
||
|
||
if (isStorableKind(kind))
|
||
{
|
||
// FIXME: This should be more accurate by taking into account the register class of each register.
|
||
// vrcStackSlot -> vrcInteger, vrcFloatingPoint, vrcFixedPoint is a load.
|
||
// vrcInteger, vrcFloatingPoint, vrcFixedPoint -> vrcStackSlot is a store.
|
||
// vrcInteger -> vrcFloatingPoint, vrcFixedPoint (is md)
|
||
|
||
VirtualRegister* outVR = phiNode.getVirtualRegisterAnnotation();
|
||
if (outVR->getClass() != vrcStackSlot)
|
||
{
|
||
DataConsumer* limit = phiNode.getInputsEnd();
|
||
for (DataConsumer *consumer = phiNode.getInputsBegin(); consumer < limit; consumer++)
|
||
{
|
||
VirtualRegister* inVR = consumer->getVariable().getVirtualRegisterAnnotation();
|
||
if (inVR != outVR)
|
||
if (inVR->getClass() != vrcStackSlot)
|
||
inVR->spillInfo.nCopies += node.nVisited;
|
||
}
|
||
}
|
||
if (isDoublewordKind(kind)) {
|
||
outVR = phiNode.getHighVirtualRegisterAnnotation();
|
||
if (outVR->getClass() != vrcStackSlot)
|
||
{
|
||
DataConsumer* limit = phiNode.getInputsEnd();
|
||
for (DataConsumer *consumer = phiNode.getInputsBegin(); consumer < limit; consumer++)
|
||
{
|
||
VirtualRegister* inVR = consumer->getVariable().getHighVirtualRegisterAnnotation();
|
||
if (inVR != outVR)
|
||
if (inVR->getClass() != vrcStackSlot)
|
||
inVR->spillInfo.nCopies += node.nVisited;
|
||
}
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
// The instructions in this node.
|
||
InstructionList& instructions = node.getInstructions();
|
||
for (InstructionList::iterator j = instructions.end(); !instructions.done(j); j = instructions.retreat(j))
|
||
{
|
||
Instruction& instruction = instructions.get(j);
|
||
|
||
InstructionUse* useBegin = instruction.getInstructionUseBegin();
|
||
InstructionUse* useEnd = instruction.getInstructionUseEnd();
|
||
InstructionUse* usePtr;
|
||
InstructionDefine* defBegin = instruction.getInstructionDefineBegin();
|
||
InstructionDefine* defEnd = instruction.getInstructionDefineEnd();
|
||
InstructionDefine* defPtr;
|
||
|
||
// Check copy insn
|
||
if (instruction.getFlags() & ifCopy)
|
||
{
|
||
PR_ASSERT(useBegin[0].isVirtualRegister());
|
||
useBegin[0].getVirtualRegister().spillInfo.nCopies += node.nVisited;
|
||
}
|
||
|
||
// Handle definitions
|
||
for (defPtr = defBegin; defPtr < defEnd; defPtr++)
|
||
if (defPtr->isVirtualRegister())
|
||
{
|
||
VirtualRegister& vReg = defPtr->getVirtualRegister();
|
||
if (vReg.getClass() != vrcStackSlot)
|
||
{
|
||
PRUint32 registerIndex = vReg.getRegisterIndex();
|
||
if (needLoad.test(registerIndex))
|
||
{
|
||
needLoad.clear(registerIndex);
|
||
if (!mustSpill.test(registerIndex))
|
||
vReg.spillInfo.infiniteSpillCost = true;
|
||
}
|
||
vReg.spillInfo.nStores += node.nVisited;
|
||
currentLive.clear(registerIndex);
|
||
}
|
||
}
|
||
|
||
// Check for deaths
|
||
for (usePtr = useBegin; usePtr < useEnd; usePtr++)
|
||
if (usePtr->isVirtualRegister())
|
||
{
|
||
VirtualRegister& vReg = usePtr->getVirtualRegister();
|
||
if (vReg.getClass() != vrcStackSlot)
|
||
{
|
||
if (!currentLive.test(vReg.getRegisterIndex()))
|
||
{
|
||
for (PRInt32 nl = needLoad.firstOne(); nl != -1; nl = needLoad.nextOne(nl))
|
||
{
|
||
vRegManager.getVirtualRegister(nl).spillInfo.nLoads += node.nVisited;
|
||
mustSpill.set(nl);
|
||
}
|
||
needLoad.clear();
|
||
}
|
||
}
|
||
}
|
||
|
||
// Handle uses
|
||
for (usePtr = useBegin; usePtr < useEnd; usePtr++)
|
||
if (usePtr->isVirtualRegister())
|
||
{
|
||
VirtualRegister& vReg = usePtr->getVirtualRegister();
|
||
if (vReg.getClass() != vrcStackSlot)
|
||
{
|
||
PRUint32 registerIndex = vReg.getRegisterIndex();
|
||
currentLive.set(registerIndex);
|
||
needLoad.set(registerIndex);
|
||
}
|
||
}
|
||
|
||
// All the registers in currentLive just lived one more cycle.
|
||
for (PRInt32 registerIndex = currentLive.firstOne(); registerIndex != -1; registerIndex = currentLive.nextOne(registerIndex))
|
||
{
|
||
VirtualRegister& vReg = vRegManager.getVirtualRegister(registerIndex);
|
||
if (vReg.getClass() != vrcStackSlot)
|
||
vReg.spillInfo.liveLength++;
|
||
}
|
||
}
|
||
|
||
// All the registers left in needLoad will be loaded.
|
||
for (PRInt32 nl = needLoad.firstOne(); nl != -1; nl = needLoad.nextOne(nl))
|
||
vRegManager.getVirtualRegister(nl).spillInfo.nLoads += node.nVisited;
|
||
}
|
||
|
||
// Summarize
|
||
for (VirtualRegisterManager::iterator j = vRegManager.begin(); !vRegManager.done(j); j = vRegManager.advance(j))
|
||
{
|
||
VirtualRegister& vReg = vRegManager.getVirtualRegister(j);
|
||
if (vReg.getClass() != vrcStackSlot)
|
||
{
|
||
if (!vReg.spillInfo.infiniteSpillCost)
|
||
{
|
||
// It may be good to take into account the size of the live range and to
|
||
// weight differently a load/store and a copy.
|
||
vReg.spillInfo.spillCost = (2 * (vReg.spillInfo.nLoads + vReg.spillInfo.nStores) - vReg.spillInfo.nCopies) /
|
||
(((Flt32)vReg.spillInfo.liveLength));
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
|
||
|
||
// asharma
|
||
void
|
||
RegisterAllocator::updateLocalVariableTable()
|
||
{
|
||
for (Uint32 m = 0; m < nNodes; m++) {
|
||
ControlNode& node = *dfsList[m];
|
||
DoublyLinkedList<Primitive> &primitives = node.getPrimitives();
|
||
for (DoublyLinkedList<Primitive>::iterator i = primitives.begin();
|
||
!primitives.done(i);
|
||
i = primitives.advance(i)) {
|
||
Primitive &p = primitives.get(i);
|
||
// We're not interested in primitives that are not the values of
|
||
// certain local variables
|
||
if (!p.mapping)
|
||
continue;
|
||
switch(p.getKind()) {
|
||
case vkCond:
|
||
case vkMemory:
|
||
break;
|
||
default:
|
||
VirtualRegister *vr = p.getVirtualRegisterAnnotation();
|
||
if (vr) {
|
||
VariableLocation loc(true, vr->getColor());
|
||
p.mapping->setVariableLocation(loc);
|
||
}
|
||
break;
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
|
||
/*
|
||
*-------------------------RegisterAllocator.cpp-------------------------
|
||
*
|
||
* RegisterAllocator::printRegisterDebug --
|
||
*
|
||
* Print informations about valid registers.
|
||
*
|
||
*-----------------------------------------------------------------------
|
||
*/
|
||
#ifdef DEBUG_LOG
|
||
void RegisterAllocator::
|
||
printRegisterDebug(LogModuleObject &f, bool verbose)
|
||
{
|
||
for (VirtualRegisterManager::iterator i = vRegManager.begin(); !vRegManager.done(i); i = vRegManager.advance(i))
|
||
{
|
||
VirtualRegister& vReg = vRegManager.getVirtualRegister(i);
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("%d: ", i));
|
||
|
||
// print the class info.
|
||
PRUint8 classChar;
|
||
switch (vReg.getClass())
|
||
{
|
||
case vrcInteger:
|
||
classChar = 'I';
|
||
break;
|
||
case vrcFixedPoint:
|
||
classChar = 'f';
|
||
break;
|
||
case vrcFloatingPoint:
|
||
classChar = 'F';
|
||
break;
|
||
case vrcStackSlot:
|
||
classChar = 'S';
|
||
break;
|
||
default:
|
||
classChar = '?';
|
||
break;
|
||
}
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("%c ", classChar));
|
||
|
||
// print the register.
|
||
if (vReg.isPreColored())
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("r%d ", vReg.getPreColor()));
|
||
else
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("vr%d ", i));
|
||
|
||
// print his interference.
|
||
if (verbose)
|
||
{
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("interferes w/ ( "));
|
||
FastBitSet inter(interferenceMatrix.getRow(i), vRegManager.count());
|
||
for (PRInt32 j = inter.firstOne(); j != -1; j = inter.nextOne(j))
|
||
{
|
||
VirtualRegister& vr = vRegManager.getVirtualRegister(j);
|
||
if (vr.isPreColored())
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("r%d ", vr.getPreColor()));
|
||
else
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("vr%d ", j));
|
||
}
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, (" - "));
|
||
FastBitSet& special = vReg.specialInterference;
|
||
for (PRInt32 k = special.firstOne(); k != -1; k = special.nextOne(k))
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("r%d ", k));
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, (") "));
|
||
}
|
||
|
||
// print the liveness info
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("alive in nodes ( "));
|
||
for (PRInt32 k = vReg.liveness.firstOne(); k != -1; k = vReg.liveness.nextOne(k))
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("%d ", k));
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, (") "));
|
||
|
||
// print the interference degree
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("nInter=%d ", vReg.colorInfo.interferenceDegree));
|
||
|
||
// print the spill cost
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("spillcost="));
|
||
if (vReg.spillInfo.infiniteSpillCost)
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("infinite "));
|
||
else
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("%.2f ", vReg.spillInfo.spillCost));
|
||
|
||
// done.
|
||
UT_OBJECTLOG(f, PR_LOG_ALWAYS, ("\n"));
|
||
}
|
||
}
|
||
#endif
|