зеркало из https://github.com/mozilla/gecko-dev.git
225 строки
7.1 KiB
C++
225 строки
7.1 KiB
C++
/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1/GPL 2.0/LGPL 2.1
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*
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* The contents of this file are subject to the Mozilla Public License Version 1.1 (the
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* "License"); you may not use this file except in compliance with the License. You may obtain
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* a copy of the License at http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis, WITHOUT
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* WARRANTY OF ANY KIND, either express or implied. See the License for the specific
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* language governing rights and limitations under the License.
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*
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* The Original Code is [Open Source Virtual Machine.]
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*
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* The Initial Developer of the Original Code is Adobe System Incorporated. Portions created
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* by the Initial Developer are Copyright (C)[ 2004-2006 ] Adobe Systems Incorporated. All Rights
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* Reserved.
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*
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* Contributor(s): Adobe AS3 Team
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*
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* Alternatively, the contents of this file may be used under the terms of either the GNU
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* General Public License Version 2 or later (the "GPL"), or the GNU Lesser General Public
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* License Version 2.1 or later (the "LGPL"), in which case the provisions of the GPL or the
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* LGPL are applicable instead of those above. If you wish to allow use of your version of this
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* file only under the terms of either the GPL or the LGPL, and not to allow others to use your
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* version of this file under the terms of the MPL, indicate your decision by deleting provisions
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* above and replace them with the notice and other provisions required by the GPL or the
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* LGPL. If you do not delete the provisions above, a recipient may use your version of this file
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* under the terms of any one of the MPL, the GPL or the LGPL.
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*
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***** END LICENSE BLOCK ***** */
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#ifndef __avmplus_ArmAssembler__
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#define __avmplus_ArmAssembler__
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namespace avmplus
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{
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class ArmAssembler
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{
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public:
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/* ARM registers */
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typedef enum
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{
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R0 = 0,
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R1 = 1,
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R2 = 2,
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R3 = 3,
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R4 = 4,
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R5 = 5,
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R6 = 6,
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R7 = 7,
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R8 = 8,
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R9 = 9,
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R10 = 10,
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FP = 11,
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IP = 12,
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SP = 13,
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LR = 14,
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PC = 15,
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// Pseudo-register for floating point
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F0 = 0,
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Unknown = -1
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}
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Register;
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/* ARM registers */
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typedef enum
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{
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R0_mask = (1<<0),
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R1_mask = (1<<1),
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R2_mask = (1<<2),
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R3_mask = (1<<3),
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R4_mask = (1<<4),
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R5_mask = (1<<5),
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R6_mask = (1<<6),
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R7_mask = (1<<7),
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R8_mask = (1<<8),
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R9_mask = (1<<9),
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R10_mask = (1<<10),
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FP_mask = (1<<11),
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IP_mask = (1<<12),
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SP_mask = (1<<13),
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LR_mask = (1<<14),
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PC_mask = (1<<15)
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}
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RegisterMask;
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/* ARM condition codes */
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typedef enum
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{
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EQ = 0x0, // Equal
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NE = 0x1, // Not Equal
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CS = 0x2, // Carry Set (or HS)
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CC = 0x3, // Carry Clear (or LO)
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MI = 0x4, // MInus
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PL = 0x5, // PLus
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VS = 0x6, // oVerflow Set
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VC = 0x7, // oVerflow Clear
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HI = 0x8, // HIgher
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LS = 0x9, // Lower or Same
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GE = 0xA, // Greater or Equal
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LT = 0xB, // Less Than
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GT = 0xC, // Greater Than
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LE = 0xD, // Less or Equal
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AL = 0xE, // ALways
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NV = 0xF // NeVer
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}
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ConditionCode;
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/* --- Data Processing Instructions --- */
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/* Values for operator "a" */
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typedef enum
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{
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AND_op = 0x0, // Boolean And Rd = Rn AND Op2
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EOR_op = 0x1, // Boolean Eor Rd = Rn EOR Op2
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SUB_op = 0x2, // Subtract Rd = Rn - Op2
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RSB_op = 0x3, // Reverse Subtract Rd = Op2 - Rn
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ADD_op = 0x4, // Addition Rd = Rn + Op2
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ADC_op = 0x5, // Add with Carry Rd = Rn + Op2 + C
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SBC_op = 0x6, // Subtract with Carry Rd = Rn - Op2 - (1-C)
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RSC_op = 0x7, // Reverse Subtract with Carry Rd - Op2 - Rn - (1-C)
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TST_op = 0x8, // Test bit Rn AND Op2
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TEQ_op = 0x9, // Test equality Rn EOR Op2
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CMP_op = 0xA, // Compare Rn - Op2
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CMN_op = 0xB, // Compare Negative Rn + Op2
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ORR_op = 0xC, // Boolean Or Rd = Rn OR Op2
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MOV_op = 0xD, // Move value Rd = Op2
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BIC_op = 0xE, // Bit Clear Rd = Rn AND NOT Op2
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MVN_op = 0xF // Move Not Rd = NOT Op2
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}
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Operator;
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/* Values for operand "t" */
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typedef enum
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{
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LSL_imm = 0, // LSL #c - Logical Shift Left
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LSL_reg = 1, // LSL Rc - Logical Shift Left
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LSR_imm = 2, // LSR #c - Logical Shift Right
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LSR_reg = 3, // LSR Rc - Logical Shift Right
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ASR_imm = 4, // ASR #c - Arithmetic Shift Right
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ASR_reg = 5, // ASR Rc - Arithmetic Shift Right
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ROR_imm = 6, // Rotate Right (c != 0)
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RRX = 6, // Rotate Right one bit with extend (c == 0)
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ROR_reg = 7 // Rotate Right
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}
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ShiftOperator;
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typedef uint32 MDInstruction;
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/* Instruction pointer */
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MDInstruction *mip;
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MDInstruction *mipStart;
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int mInstructionCount; // number of machine instructions
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#define incInstructionCount() mInstructionCount++
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/* Current condition code */
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ConditionCode conditionCode;
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ArmAssembler();
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void SET_CONDITION_CODE(ConditionCode conditionCode);
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void IMM32(int value);
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void MOV(Register dst, Register src);
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void STMFD_bang(Register dst, int mask);
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void SUB_imm8(Register dst, Register src, int imm8);
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void RSB_imm8(Register dst, Register src, int imm8);
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void B(int offset24);
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void BL(int offset24);
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void LDR(Register dst, int offset, Register base);
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void BIC_imm8(Register dst, Register src, int imm8);
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void MOV_imm8(Register dst, int imm8);
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void MOV_imm16(Register dst, int imm16);
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void CMP_imm8(Register src, int imm8);
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void ADD(Register dst, Register src1, Register src2);
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void SUB(Register dst, Register src1, Register src2);
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void AND(Register dst, Register src1, Register src2);
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void ORR(Register dst, Register src1, Register src2);
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void EOR(Register dst, Register src1, Register src2);
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void MUL(Register dst, Register src1, Register src2);
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void CMP(Register Rn, Register Rm);
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void LSL(Register dst, Register src, Register rShift);
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void LSR(Register dst, Register src, Register rShift);
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void ASR(Register dst, Register src, Register rShift);
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void LSL_i(Register dst, Register src, int iShift);
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void LSR_i(Register dst, Register src, int iShift);
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void ASR_i(Register dst, Register src, int iShift);
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void STR(Register src, int offset, Register base);
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void ADD_imm8(Register dst, Register src, int imm8);
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void ADD_imm8_hi(Register dst, Register src, int imm8);
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void ADD_imm16(Register dst, Register src, int imm16);
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void AND_imm8(Register dst, Register src, int imm8);
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void ORR_imm8(Register dst, Register src, int imm8);
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void EOR_imm8(Register dst, Register src, int imm8);
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void LDMFD(Register src, int mask);
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void LDMFD_bang(Register src, int mask);
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// Cheeseball way of doing imm32.
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void MOV_imm32(Register dst, int imm32);
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void flushDataCache(void *start, int len);
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// Set if verbose output desired
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#ifdef AVMPLUS_VERBOSE
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bool verboseFlag;
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#endif
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PrintWriter *console;
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// Immediate pool
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MDInstruction *immediatePool;
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int immediatePoolCount;
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const static int kImmediatePoolMax = 16;
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static const char* const regNames[];
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#define gpregNames regNames
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static const char* const conditionCodes[];
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};
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}
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#endif /* __avmplus_ArmAssembler__ */
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