зеркало из https://github.com/mozilla/gecko-dev.git
370 строки
11 KiB
NASM
370 строки
11 KiB
NASM
;******************************************************************************
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;* x86-SIMD-optimized IDCT for prores
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;* this is identical to "simple" IDCT written by Michael Niedermayer
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;* except for the clip range
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;*
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;* Copyright (c) 2011 Ronald S. Bultje <rsbultje@gmail.com>
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* 51, Inc., Foundation Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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; add SECTION_RODATA and proper include before including this file!
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%if ARCH_X86_64
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%macro define_constants 1
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%undef w4_plus_w2
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%undef w4_min_w2
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%undef w4_plus_w6
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%undef w4_min_w6
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%undef w1_plus_w3
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%undef w3_min_w1
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%undef w7_plus_w3
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%undef w3_min_w7
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%define w4_plus_w2 w4_plus_w2%1
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%define w4_min_w2 w4_min_w2%1
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%define w4_plus_w6 w4_plus_w6%1
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%define w4_min_w6 w4_min_w6%1
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%define w1_plus_w3 w1_plus_w3%1
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%define w3_min_w1 w3_min_w1%1
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%define w7_plus_w3 w7_plus_w3%1
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%define w3_min_w7 w3_min_w7%1
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%endmacro
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; interleave data while maintaining source
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; %1=type, %2=dstlo, %3=dsthi, %4=src, %5=interleave
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%macro SBUTTERFLY3 5
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punpckl%1 m%2, m%4, m%5
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punpckh%1 m%3, m%4, m%5
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%endmacro
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; %1/%2=src1/dst1, %3/%4=dst2, %5/%6=src2, %7=shift
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; action: %3/%4 = %1/%2 - %5/%6; %1/%2 += %5/%6
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; %1/%2/%3/%4 >>= %7; dword -> word (in %1/%3)
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%macro SUMSUB_SHPK 7
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psubd %3, %1, %5 ; { a0 - b0 }[0-3]
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psubd %4, %2, %6 ; { a0 - b0 }[4-7]
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paddd %1, %5 ; { a0 + b0 }[0-3]
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paddd %2, %6 ; { a0 + b0 }[4-7]
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psrad %1, %7
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psrad %2, %7
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psrad %3, %7
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psrad %4, %7
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packssdw %1, %2 ; row[0]
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packssdw %3, %4 ; row[7]
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%endmacro
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; %1 = initial bias ("" if nop)
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; %2 = number of bits to shift at the end
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; %3 = qmat (for prores)
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%macro IDCT_1D 2-3
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; a0 = (W4 * row[0]) + (1 << (15 - 1));
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; a1 = a0;
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; a2 = a0;
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; a3 = a0;
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; a0 += W2 * row[2];
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; a1 += W6 * row[2];
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; a2 -= W6 * row[2];
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; a3 -= W2 * row[2];
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%ifstr %1
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mova m15, [pd_round_ %+ %2]
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%else
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paddw m10, [%1]
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%endif
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SBUTTERFLY3 wd, 0, 1, 10, 8 ; { row[0], row[2] }[0-3]/[4-7]
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pmaddwd m2, m0, [w4_plus_w6]
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pmaddwd m3, m1, [w4_plus_w6]
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pmaddwd m4, m0, [w4_min_w6]
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pmaddwd m5, m1, [w4_min_w6]
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pmaddwd m6, m0, [w4_min_w2]
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pmaddwd m7, m1, [w4_min_w2]
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pmaddwd m0, [w4_plus_w2]
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pmaddwd m1, [w4_plus_w2]
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%ifstr %1
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; Adding 1<<(%2-1) for >=15 bits values
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paddd m2, m15
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paddd m3, m15
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paddd m4, m15
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paddd m5, m15
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paddd m6, m15
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paddd m7, m15
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paddd m0, m15
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paddd m1, m15
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%endif
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; a0: -1*row[0]-1*row[2]
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; a1: -1*row[0]
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; a2: -1*row[0]
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; a3: -1*row[0]+1*row[2]
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; a0 += W4*row[4] + W6*row[6]; i.e. -1*row[4]
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; a1 -= W4*row[4] + W2*row[6]; i.e. -1*row[4]-1*row[6]
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; a2 -= W4*row[4] - W2*row[6]; i.e. -1*row[4]+1*row[6]
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; a3 += W4*row[4] - W6*row[6]; i.e. -1*row[4]
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SBUTTERFLY3 wd, 8, 9, 13, 12 ; { row[4], row[6] }[0-3]/[4-7]
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pmaddwd m10, m8, [w4_plus_w6]
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pmaddwd m11, m9, [w4_plus_w6]
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paddd m0, m10 ; a0[0-3]
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paddd m1, m11 ; a0[4-7]
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pmaddwd m10, m8, [w4_min_w6]
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pmaddwd m11, m9, [w4_min_w6]
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paddd m6, m10 ; a3[0-3]
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paddd m7, m11 ; a3[4-7]
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pmaddwd m10, m8, [w4_min_w2]
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pmaddwd m11, m9, [w4_min_w2]
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pmaddwd m8, [w4_plus_w2]
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pmaddwd m9, [w4_plus_w2]
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psubd m4, m10 ; a2[0-3] intermediate
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psubd m5, m11 ; a2[4-7] intermediate
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psubd m2, m8 ; a1[0-3] intermediate
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psubd m3, m9 ; a1[4-7] intermediate
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; load/store
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mova [blockq+ 0], m0
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mova [blockq+ 32], m2
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mova [blockq+ 64], m4
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mova [blockq+ 96], m6
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mova m10,[blockq+ 16] ; { row[1] }[0-7]
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mova m8, [blockq+ 48] ; { row[3] }[0-7]
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mova m13,[blockq+ 80] ; { row[5] }[0-7]
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mova m14,[blockq+112] ; { row[7] }[0-7]
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mova [blockq+ 16], m1
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mova [blockq+ 48], m3
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mova [blockq+ 80], m5
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mova [blockq+112], m7
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%if %0 == 3
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pmullw m10,[%3+ 16]
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pmullw m8, [%3+ 48]
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pmullw m13,[%3+ 80]
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pmullw m14,[%3+112]
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%endif
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; b0 = MUL(W1, row[1]);
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; MAC(b0, W3, row[3]);
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; b1 = MUL(W3, row[1]);
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; MAC(b1, -W7, row[3]);
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; b2 = MUL(W5, row[1]);
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; MAC(b2, -W1, row[3]);
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; b3 = MUL(W7, row[1]);
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; MAC(b3, -W5, row[3]);
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SBUTTERFLY3 wd, 0, 1, 10, 8 ; { row[1], row[3] }[0-3]/[4-7]
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pmaddwd m2, m0, [w3_min_w7]
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pmaddwd m3, m1, [w3_min_w7]
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pmaddwd m4, m0, [w5_min_w1]
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pmaddwd m5, m1, [w5_min_w1]
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pmaddwd m6, m0, [w7_min_w5]
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pmaddwd m7, m1, [w7_min_w5]
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pmaddwd m0, [w1_plus_w3]
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pmaddwd m1, [w1_plus_w3]
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; b0: +1*row[1]+2*row[3]
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; b1: +2*row[1]-1*row[3]
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; b2: -1*row[1]-1*row[3]
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; b3: +1*row[1]+1*row[3]
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; MAC(b0, W5, row[5]);
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; MAC(b0, W7, row[7]);
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; MAC(b1, -W1, row[5]);
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; MAC(b1, -W5, row[7]);
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; MAC(b2, W7, row[5]);
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; MAC(b2, W3, row[7]);
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; MAC(b3, W3, row[5]);
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; MAC(b3, -W1, row[7]);
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SBUTTERFLY3 wd, 8, 9, 13, 14 ; { row[5], row[7] }[0-3]/[4-7]
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; b0: -1*row[5]+1*row[7]
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; b1: -1*row[5]+1*row[7]
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; b2: +1*row[5]+2*row[7]
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; b3: +2*row[5]-1*row[7]
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pmaddwd m10, m8, [w1_plus_w5]
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pmaddwd m11, m9, [w1_plus_w5]
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pmaddwd m12, m8, [w5_plus_w7]
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pmaddwd m13, m9, [w5_plus_w7]
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psubd m2, m10 ; b1[0-3]
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psubd m3, m11 ; b1[4-7]
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paddd m0, m12 ; b0[0-3]
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paddd m1, m13 ; b0[4-7]
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pmaddwd m12, m8, [w7_plus_w3]
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pmaddwd m13, m9, [w7_plus_w3]
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pmaddwd m8, [w3_min_w1]
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pmaddwd m9, [w3_min_w1]
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paddd m4, m12 ; b2[0-3]
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paddd m5, m13 ; b2[4-7]
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paddd m6, m8 ; b3[0-3]
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paddd m7, m9 ; b3[4-7]
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; row[0] = (a0 + b0) >> 15;
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; row[7] = (a0 - b0) >> 15;
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; row[1] = (a1 + b1) >> 15;
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; row[6] = (a1 - b1) >> 15;
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; row[2] = (a2 + b2) >> 15;
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; row[5] = (a2 - b2) >> 15;
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; row[3] = (a3 + b3) >> 15;
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; row[4] = (a3 - b3) >> 15;
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mova m8, [blockq+ 0] ; a0[0-3]
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mova m9, [blockq+16] ; a0[4-7]
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SUMSUB_SHPK m8, m9, m10, m11, m0, m1, %2
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mova m0, [blockq+32] ; a1[0-3]
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mova m1, [blockq+48] ; a1[4-7]
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SUMSUB_SHPK m0, m1, m9, m11, m2, m3, %2
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mova m1, [blockq+64] ; a2[0-3]
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mova m2, [blockq+80] ; a2[4-7]
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SUMSUB_SHPK m1, m2, m11, m3, m4, m5, %2
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mova m2, [blockq+96] ; a3[0-3]
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mova m3, [blockq+112] ; a3[4-7]
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SUMSUB_SHPK m2, m3, m4, m5, m6, m7, %2
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%endmacro
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; void ff_prores_idct_put_10_<opt>(uint8_t *pixels, ptrdiff_t stride,
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; int16_t *block, const int16_t *qmat);
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; %1 = row shift
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; %2 = row bias macro
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; %3 = column shift
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; %4 = column bias macro
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; %5 = final action (nothing, "store", "put", "add")
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; %6 = min pixel value
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; %7 = max pixel value
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; %8 = qmat (for prores)
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%macro IDCT_FN 4-8
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; for (i = 0; i < 8; i++)
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; idctRowCondDC(block + i*8);
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mova m10,[blockq+ 0] ; { row[0] }[0-7]
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mova m8, [blockq+32] ; { row[2] }[0-7]
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mova m13,[blockq+64] ; { row[4] }[0-7]
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mova m12,[blockq+96] ; { row[6] }[0-7]
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%if %0 == 8
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pmullw m10,[%8+ 0]
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pmullw m8, [%8+32]
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pmullw m13,[%8+64]
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pmullw m12,[%8+96]
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IDCT_1D %1, %2, %8
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%elif %2 == 11
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; This copies the DC-only shortcut. When there is only a DC coefficient the
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; C shifts the value and splats it to all coeffs rather than multiplying and
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; doing the full IDCT. This causes a difference on 8-bit because the
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; coefficient is 16383 rather than 16384 (which you can get with shifting).
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por m1, m8, m13
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por m1, m12
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por m1, [blockq+ 16] ; { row[1] }[0-7]
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por m1, [blockq+ 48] ; { row[3] }[0-7]
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por m1, [blockq+ 80] ; { row[5] }[0-7]
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por m1, [blockq+112] ; { row[7] }[0-7]
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pxor m2, m2
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pcmpeqw m1, m2
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psllw m2, m10, 3
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pand m2, m1
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pcmpeqb m3, m3
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pxor m1, m3
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mova [rsp], m1
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mova [rsp+16], m2
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IDCT_1D %1, %2
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mova m5, [rsp]
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mova m6, [rsp+16]
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pand m8, m5
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por m8, m6
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pand m0, m5
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por m0, m6
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pand m1, m5
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por m1, m6
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pand m2, m5
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por m2, m6
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pand m4, m5
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por m4, m6
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pand m11, m5
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por m11, m6
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pand m9, m5
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por m9, m6
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pand m10, m5
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por m10, m6
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%else
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IDCT_1D %1, %2
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%endif
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; transpose for second part of IDCT
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TRANSPOSE8x8W 8, 0, 1, 2, 4, 11, 9, 10, 3
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mova [blockq+ 16], m0
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mova [blockq+ 48], m2
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mova [blockq+ 80], m11
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mova [blockq+112], m10
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SWAP 8, 10
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SWAP 1, 8
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SWAP 4, 13
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SWAP 9, 12
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; for (i = 0; i < 8; i++)
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; idctSparseColAdd(dest + i, line_size, block + i);
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IDCT_1D %3, %4
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; clip/store
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%if %0 >= 5
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%ifidn %5,"store"
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; No clamping, means pure idct
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mova [blockq+ 0], m8
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mova [blockq+ 16], m0
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mova [blockq+ 32], m1
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mova [blockq+ 48], m2
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mova [blockq+ 64], m4
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mova [blockq+ 80], m11
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mova [blockq+ 96], m9
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mova [blockq+112], m10
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%elifidn %5,"put"
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%ifidn %6, 0
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pxor m3, m3
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%else
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mova m3, [%6]
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%endif ; ifidn %6, 0
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mova m5, [%7]
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pmaxsw m8, m3
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pmaxsw m0, m3
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pmaxsw m1, m3
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pmaxsw m2, m3
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pmaxsw m4, m3
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pmaxsw m11, m3
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pmaxsw m9, m3
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pmaxsw m10, m3
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pminsw m8, m5
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pminsw m0, m5
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pminsw m1, m5
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pminsw m2, m5
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pminsw m4, m5
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pminsw m11, m5
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pminsw m9, m5
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pminsw m10, m5
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lea r2, [r1*3]
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mova [r0 ], m8
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mova [r0+r1 ], m0
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mova [r0+r1*2], m1
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mova [r0+r2 ], m2
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lea r0, [r0+r1*4]
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mova [r0 ], m4
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mova [r0+r1 ], m11
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mova [r0+r1*2], m9
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mova [r0+r2 ], m10
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%endif ; %5 action
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%endif; if %0 >= 5
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%endmacro
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%endif
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