зеркало из https://github.com/mozilla/pjs.git
Bug 601914 - XPCOM does not work with ARM hardfp ABI. r=Jacob.Bramley a=blocking-fennec
This commit is contained in:
Siarhei Siamashka
Родитель
f08efb3976
Коммит
0bf3214567
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@ -21,6 +21,7 @@
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*
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* Contributor(s):
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* Mike Hommey <mh@glandium.org>
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* Siarhei Siamashka <siarhei.siamashka@nokia.com>
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*
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* Alternatively, the contents of this file may be used under the terms of
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* either of the GNU General Public License Version 2 or later (the "GPL"),
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@ -44,6 +45,13 @@
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#error "This code is for Linux ARM only. Check that it works on your system, too.\nBeware that this code is highly compiler dependent."
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#endif
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#if defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)) \
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&& defined(__ARM_EABI__) && !defined(__ARM_PCS_VFP) && !defined(__ARM_PCS)
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#error "Can't identify floating point calling conventions.\nPlease ensure that your toolchain defines __ARM_PCS or __ARM_PCS_VFP."
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#endif
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#ifndef __ARM_PCS_VFP
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/* This function copies a 64-bits word from dw to the given pointer in
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* a buffer delimited by start and end, possibly wrapping around the
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* buffer boundaries, and/or properly aligning the data at 64-bits word
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@ -189,3 +197,252 @@ NS_InvokeByIndex(nsISupports* that, PRUint32 methodIndex,
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stack_space[base_size * 2 - 2],
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stack_space[base_size * 2 - 1]);
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}
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#else /* __ARM_PCS_VFP */
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/* "Procedure Call Standard for the ARM Architecture" document, sections
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* "5.5 Parameter Passing" and "6.1.2 Procedure Calling" contain all the
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* needed information.
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*
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* http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/IHI0042D_aapcs.pdf
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*/
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#if defined(__thumb__) && !defined(__thumb2__)
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#error "Thumb1 is not supported"
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#endif
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#ifndef __ARMEL__
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#error "Only little endian compatibility was tested"
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#endif
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/*
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* Allocation of integer function arguments initially to registers r1-r3
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* and then to stack. Handling of 'this' argument which goes to r0 registers
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* is handled separately and does not belong to these two inline functions.
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*
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* The doubleword arguments are allocated to even:odd
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* register pairs or get aligned at 8-byte boundary on stack. The "holes"
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* which may appear as a result of this realignment remain unused.
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*
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* 'ireg_args' - pointer to the current position in the buffer,
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* corresponding to the register arguments
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* 'stack_args' - pointer to the current position in the buffer,
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* corresponding to the arguments on stack
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* 'end' - pointer to the end of the registers argument
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* buffer (it is guaranteed to be 8-bytes aligned)
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*/
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static inline void copy_word(PRUint32* &ireg_args,
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PRUint32* &stack_args,
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PRUint32* end,
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PRUint32 data)
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{
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if (ireg_args < end) {
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*ireg_args = data;
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ireg_args++;
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} else {
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*stack_args = data;
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stack_args++;
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}
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}
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static inline void copy_dword(PRUint32* &ireg_args,
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PRUint32* &stack_args,
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PRUint32* end,
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PRUint64 data)
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{
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if (ireg_args + 1 < end) {
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if ((PRUint32)ireg_args & 4) {
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ireg_args++;
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}
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*(PRUint64 *)ireg_args = data;
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ireg_args += 2;
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} else {
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if ((PRUint32)stack_args & 4) {
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stack_args++;
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}
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*(PRUint64 *)stack_args = data;
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stack_args += 2;
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}
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}
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/*
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* Allocation of floating point arguments to VFP registers (s0-s15, d0-d7).
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*
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* Unlike integer registers allocation, "back-filling" needs to be
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* supported. For example, the third floating point argument in the
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* following function is going to be allocated to s1 register, back-filling
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* the "hole":
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* void f(float s0, double d1, float s1)
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*
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* Refer to the "Procedure Call Standard for the ARM Architecture" document
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* for more details.
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*
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* 'vfp_s_args' - pointer to the current position in the buffer with
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* the next unallocated single precision register
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* 'vfp_d_args' - pointer to the current position in the buffer with
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* the next unallocated double precision register,
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* it has the same value as 'vfp_s_args' when back-filling
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* is not used
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* 'end' - pointer to the end of the vfp registers argument
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* buffer (it is guaranteed to be 8-bytes aligned)
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*
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* Mozilla bugtracker has a test program attached which be used for
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* experimenting with VFP registers allocation code and testing its
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* correctness:
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* https://bugzilla.mozilla.org/show_bug.cgi?id=601914#c19
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*/
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static inline bool copy_vfp_single(float* &vfp_s_args, double* &vfp_d_args,
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float* end, float data)
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{
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if (vfp_s_args >= end)
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return false;
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*vfp_s_args = data;
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vfp_s_args++;
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if (vfp_s_args < (float *)vfp_d_args) {
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// It was the case of back-filling, now the next free single precision
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// register should overlap with the next free double precision register
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vfp_s_args = (float *)vfp_d_args;
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} else if (vfp_s_args > (float *)vfp_d_args) {
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// also update the pointer to the next free double precision register
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vfp_d_args++;
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}
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return true;
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}
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static inline bool copy_vfp_double(float* &vfp_s_args, double* &vfp_d_args,
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float* end, double data)
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{
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if (vfp_d_args >= (double *)end) {
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// The back-filling continues only so long as no VFP CPRC has been
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// allocated to a slot on the stack. Basically no VFP registers can
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// be allocated after this point.
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vfp_s_args = end;
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return false;
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}
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if (vfp_s_args == (float *)vfp_d_args) {
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// also update the pointer to the next free single precision register
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vfp_s_args += 2;
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}
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*vfp_d_args = data;
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vfp_d_args++;
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return true;
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}
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static void
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invoke_copy_to_stack(PRUint32* stk, PRUint32 *end,
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PRUint32 paramCount, nsXPTCVariant* s)
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{
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PRUint32 *ireg_args = end - 3;
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float *vfp_s_args = (float *)end;
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double *vfp_d_args = (double *)end;
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float *vfp_end = vfp_s_args + 16;
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for (PRUint32 i = 0; i < paramCount; i++, s++) {
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if (s->IsPtrData()) {
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copy_word(ireg_args, stk, end, (PRUint32)s->ptr);
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continue;
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}
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// According to the ARM EABI, integral types that are smaller than a word
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// are to be sign/zero-extended to a full word and treated as 4-byte values
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switch (s->type)
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{
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case nsXPTType::T_FLOAT:
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if (!copy_vfp_single(vfp_s_args, vfp_d_args, vfp_end, s->val.f)) {
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copy_word(end, stk, end, reinterpret_cast<PRUint32&>(s->val.f));
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}
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break;
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case nsXPTType::T_DOUBLE:
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if (!copy_vfp_double(vfp_s_args, vfp_d_args, vfp_end, s->val.d)) {
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copy_dword(end, stk, end, reinterpret_cast<PRUint64&>(s->val.d));
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}
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break;
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case nsXPTType::T_I8: copy_word(ireg_args, stk, end, s->val.i8); break;
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case nsXPTType::T_I16: copy_word(ireg_args, stk, end, s->val.i16); break;
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case nsXPTType::T_I32: copy_word(ireg_args, stk, end, s->val.i32); break;
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case nsXPTType::T_I64: copy_dword(ireg_args, stk, end, s->val.i64); break;
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case nsXPTType::T_U8: copy_word(ireg_args, stk, end, s->val.u8); break;
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case nsXPTType::T_U16: copy_word(ireg_args, stk, end, s->val.u16); break;
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case nsXPTType::T_U32: copy_word(ireg_args, stk, end, s->val.u32); break;
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case nsXPTType::T_U64: copy_dword(ireg_args, stk, end, s->val.u64); break;
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case nsXPTType::T_BOOL: copy_word(ireg_args, stk, end, s->val.b); break;
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case nsXPTType::T_CHAR: copy_word(ireg_args, stk, end, s->val.c); break;
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case nsXPTType::T_WCHAR: copy_word(ireg_args, stk, end, s->val.wc); break;
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default:
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// all the others are plain pointer types
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copy_word(ireg_args, stk, end, reinterpret_cast<PRUint32>(s->val.p));
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break;
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}
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}
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}
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typedef PRUint32 (*vtable_func)(nsISupports *, PRUint32, PRUint32, PRUint32);
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EXPORT_XPCOM_API(nsresult)
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NS_InvokeByIndex(nsISupports* that, PRUint32 methodIndex,
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PRUint32 paramCount, nsXPTCVariant* params)
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{
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vtable_func *vtable = *reinterpret_cast<vtable_func **>(that);
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#if defined(__GXX_ABI_VERSION) && __GXX_ABI_VERSION >= 100 /* G++ V3 ABI */
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vtable_func func = vtable[methodIndex];
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#else /* non G++ V3 ABI */
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vtable_func func = vtable[2 + methodIndex];
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#endif
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// 'register PRUint32 result asm("r0")' could be used here, but it does not
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// seem to be reliable in all cases: http://gcc.gnu.org/PR46164
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PRUint32 result;
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asm (
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"mov %[stack_space_size], %[param_count_plus_2], lsl #3\n"
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"tst sp, #4\n" /* check stack alignment */
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"add %[stack_space_size], #(4 * 16)\n" /* space for VFP registers */
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"mov r3, %[params]\n"
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"it ne\n"
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"addne %[stack_space_size], %[stack_space_size], #4\n"
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"sub r0, sp, %[stack_space_size]\n" /* allocate space on stack */
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"sub r2, %[param_count_plus_2], #2\n"
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"mov sp, r0\n"
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"add r1, r0, %[param_count_plus_2], lsl #3\n"
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"blx %[invoke_copy_to_stack]\n"
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"add ip, sp, %[param_count_plus_2], lsl #3\n"
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"mov r0, %[that]\n"
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"ldmdb ip, {r1, r2, r3}\n"
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"vldm ip, {d0, d1, d2, d3, d4, d5, d6, d7}\n"
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"blx %[func]\n"
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"add sp, sp, %[stack_space_size]\n" /* cleanup stack */
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"mov %[stack_space_size], r0\n" /* it's actually 'result' variable */
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: [stack_space_size] "=&r" (result)
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: [func] "r" (func),
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[that] "r" (that),
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[params] "r" (params),
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[param_count_plus_2] "r" (paramCount + 2),
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[invoke_copy_to_stack] "r" (invoke_copy_to_stack)
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: "cc", "memory",
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// Mark all the scratch registers as clobbered because they may be
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// modified by the functions, called from this inline assembly block
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"r0", "r1", "r2", "r3", "ip", "lr",
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"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
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// Also unconditionally mark d16-d31 registers as clobbered even though
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// they actually don't exist in vfpv2 and vfpv3-d16 variants. There is
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// no way to identify VFP variant using preprocessor at the momemnt
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// (see http://gcc.gnu.org/PR46128 for more details), but fortunately
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// current versions of gcc do not seem to complain about these registers
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// even when this code is compiled with '-mfpu=vfpv3-d16' option.
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// If gcc becomes more strict in the future and/or provides a way to
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// identify VFP variant, the following d16-d31 registers list needs
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// to be wrapped into some #ifdef
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"d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
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"d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"
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);
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return result;
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}
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#endif
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