зеркало из https://github.com/mozilla/pjs.git
Bug 551165 - Unable to compile MIPS nanojit backend (r=edwsmith+)
--HG-- extra : convert_revision : 7d9635ba36b214f707cf426b7b414cde99738048
This commit is contained in:
Chris Dearman
Родитель
25a0becd86
Коммит
533c36d125
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@ -133,11 +133,11 @@ namespace nanojit
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// the exact code generated to be determined at runtime
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//
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// cpu_has_fpu CPU has fpu
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// cpu_has_movn CPU has movn
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// cpu_has_cmov CPU has movf/movn instructions
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// cpu_has_lsdc1 CPU has ldc1/sdc1 instructions
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// cpu_has_lsxdc1 CPU has ldxc1/sdxc1 instructions
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// cpu_has_fpuhazard hazard between c.xx.xx & bc1[tf]
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// cpu_has_movn CPU has movn
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// cpu_has_cmov CPU has movf/movn instructions
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// cpu_has_lsdc1 CPU has ldc1/sdc1 instructions
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// cpu_has_lsxdc1 CPU has ldxc1/sdxc1 instructions
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// cpu_has_fpuhazard hazard between c.xx.xx & bc1[tf]
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//
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// Currently the values are initialised bases on preprocessor definitions
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@ -148,7 +148,7 @@ namespace nanojit
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#define _CONST const
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#endif
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#ifdef NJ_SOFTFLOAT
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#if NJ_SOFTFLOAT_SUPPORTED
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_CONST bool cpu_has_fpu = false;
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#else
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_CONST bool cpu_has_fpu = true;
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@ -470,9 +470,11 @@ namespace nanojit
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{
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// The stack offset always be at least aligned to 4 bytes.
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NanoAssert((stkd & 3) == 0);
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// The only use for this function when we are using soft floating-point
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// is for LIR_qjoin.
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NanoAssert(cpu_has_fpu || arg->isop(LIR_qjoin));
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#if NJ_SOFTFLOAT_SUPPORTED
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NanoAssert(arg->isop(LIR_qjoin));
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#else
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NanoAssert(cpu_has_fpu);
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#endif
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// O32 ABI requires that 64-bit arguments are aligned on even-numbered
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// registers, as A0:A1/FA0 or A2:A3/FA1. Use the stack offset to keep track
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@ -579,22 +581,6 @@ namespace nanojit
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TAG("asm_u2f(ins=%p{%s})", ins, lirNames[ins->opcode()]);
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}
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void Assembler::asm_qjoin(LIns *ins)
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{
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int d = findMemFor(ins);
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NanoAssert(d && isS16(d));
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LIns* lo = ins->oprnd1();
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LIns* hi = ins->oprnd2();
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Register r = findRegFor(hi, GpRegs);
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SW(r, d+mswoff(), FP);
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r = findRegFor(lo, GpRegs); // okay if r gets recycled.
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SW(r, d+lswoff(), FP);
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deprecated_freeRsrcOf(ins); // if we had a reg in use, flush it to mem
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TAG("asm_qjoin(ins=%p{%s})", ins, lirNames[ins->opcode()]);
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}
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void Assembler::asm_fop(LIns *ins)
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{
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NanoAssert(cpu_has_fpu);
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@ -654,6 +640,7 @@ namespace nanojit
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TAG("asm_immf(ins=%p{%s})", ins, lirNames[ins->opcode()]);
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}
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#ifdef NANOJIT_64BIT
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void
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Assembler::asm_q2i(LIns *)
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{
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@ -666,6 +653,7 @@ namespace nanojit
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TODO(asm_promote);
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TAG("asm_promote(ins=%p{%s})", ins, lirNames[ins->opcode()]);
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}
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#endif
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void Assembler::asm_load64(LIns *ins)
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{
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@ -718,19 +706,15 @@ namespace nanojit
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{
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Register r = deprecated_prepResultReg(ins, GpRegs);
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LOpcode op = ins->opcode();
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LIns *a = ins->oprnd1();
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LIns *b = ins->oprnd2();
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asm_cmp(op, a, b, r);
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// LIR_ov uses the flags set by arithmetic ops
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if (op == LIR_ov) {
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ovreg = r;
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}
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else {
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LIns *a = ins->oprnd1();
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LIns *b = ins->oprnd2();
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asm_cmp(op, a, b, r);
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}
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TAG("asm_cond(ins=%p{%s})", ins, lirNames[ins->opcode()]);
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}
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#if NJ_SOFTFLOAT_SUPPORTED
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void Assembler::asm_qhi(LIns *ins)
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{
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Register rr = deprecated_prepResultReg(ins, GpRegs);
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@ -749,6 +733,24 @@ namespace nanojit
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TAG("asm_qlo(ins=%p{%s})", ins, lirNames[ins->opcode()]);
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}
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void Assembler::asm_qjoin(LIns *ins)
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{
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int d = findMemFor(ins);
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NanoAssert(d && isS16(d));
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LIns* lo = ins->oprnd1();
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LIns* hi = ins->oprnd2();
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Register r = findRegFor(hi, GpRegs);
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SW(r, d+mswoff(), FP);
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r = findRegFor(lo, GpRegs); // okay if r gets recycled.
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SW(r, d+lswoff(), FP);
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deprecated_freeRsrcOf(ins); // if we had a reg in use, flush it to mem
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TAG("asm_qjoin(ins=%p{%s})", ins, lirNames[ins->opcode()]);
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}
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#endif
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void Assembler::asm_neg_not(LIns *ins)
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{
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LOpcode op = ins->opcode();
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@ -848,7 +850,6 @@ namespace nanojit
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releaseRegisters();
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assignSavedRegs();
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ovreg = deprecated_UnknownReg;
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LIns *value = ins->oprnd1();
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if (ins->isop(LIR_ret)) {
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@ -856,14 +857,13 @@ namespace nanojit
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}
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else {
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NanoAssert(ins->isop(LIR_fret));
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if (cpu_has_fpu)
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findSpecificRegFor(value, FV0);
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else {
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NanoAssert(value->isop(LIR_qjoin));
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// FIXME: endianess?
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findSpecificRegFor(value->oprnd1(), V0); // lo
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findSpecificRegFor(value->oprnd2(), V1); // hi
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}
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#if NJ_SOFTFLOAT_SUPPORTED
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NanoAssert(value->isop(LIR_qjoin));
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findSpecificRegFor(value->oprnd1(), V0); // lo
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findSpecificRegFor(value->oprnd2(), V1); // hi
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#else
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findSpecificRegFor(value, FV0);
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#endif
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}
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TAG("asm_ret(ins=%p{%s})", ins, lirNames[ins->opcode()]);
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}
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@ -940,7 +940,7 @@ namespace nanojit
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// If this is the last use of lhs in reg, we can re-use the result reg.
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// Else, lhs already has a register assigned.
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Register ra = !lhs->isInReg() ? findSpecificRegFor(lhs, rr) : lhs->deprecated_getReg();
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Register rb;
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Register rb, t;
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// Don't re-use the registers we've already allocated.
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NanoAssert(deprecated_isKnownReg(rr));
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@ -953,19 +953,27 @@ namespace nanojit
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if (isS16(rhsc)) {
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// MIPS arith immediate ops sign-extend the imm16 value
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switch (op) {
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case LIR_add:
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if (ovreg != deprecated_UnknownReg)
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SLT(ovreg, rr, ra);
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case LIR_addxov:
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SLT(AT, rr, ra);
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ADDIU(rr, ra, rhsc);
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goto done;
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case LIR_sub:
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case LIR_add:
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ADDIU(rr, ra, rhsc);
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goto done;
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case LIR_subxov:
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if (isS16(-rhsc)) {
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if (ovreg != deprecated_UnknownReg)
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SLT(ovreg, ra, rr);
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SLT(AT, ra, rr);
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ADDIU(rr, ra, -rhsc);
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goto done;
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}
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break;
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case LIR_sub:
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if (isS16(-rhsc)) {
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ADDIU(rr, ra, -rhsc);
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goto done;
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}
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break;
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case LIR_mulxov:
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case LIR_mul:
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// FIXME: optimise constant multiply by 2^n
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// if ((rhsc & (rhsc-1)) == 0)
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@ -1012,11 +1020,14 @@ namespace nanojit
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// general case, put rhs in register
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rb = (rhs == lhs) ? ra : findRegFor(rhs, allow);
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NanoAssert(deprecated_isKnownReg(rb));
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allow &= ~rmask(rb);
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switch (op) {
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case LIR_addxov:
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SLT(AT, rr, ra);
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ADDU(rr, ra, rb);
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break;
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case LIR_add:
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if (ovreg != deprecated_UnknownReg)
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SLT(ovreg,rr,ra);
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ADDU(rr, ra, rb);
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break;
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case LIR_and:
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@ -1028,9 +1039,11 @@ namespace nanojit
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case LIR_xor:
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XOR(rr, ra, rb);
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break;
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case LIR_subxov:
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SLT(AT,ra,rr);
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SUBU(rr, ra, rb);
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break;
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case LIR_sub:
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if (ovreg != deprecated_UnknownReg)
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SLT(ovreg,ra,rr);
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SUBU(rr, ra, rb);
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break;
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case LIR_lsh:
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@ -1045,46 +1058,69 @@ namespace nanojit
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SRLV(rr, ra, rb);
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ANDI(rb, rb, 31);
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break;
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case LIR_mul:
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if (ovreg != deprecated_UnknownReg) {
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// Overflow indication required
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// Do a 32x32 signed multiply generating a 64 bit result
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// Compare bit31 of the result with the high order bits
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// mult $ra,$rb
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// mflo $rr # result to $rr
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// sra $at,$rr,31 # $at = 0x00000000 or 0xffffffff
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// mfhi $ovreg
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// xor $ovreg,$ovreg,$at # sets $ovreg to nonzero if overflow
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// sltu $ovreg,$0,$ovreg # sets $ovreg to 1 if overflow
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SLTU(ovreg,ZERO,ovreg);
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XOR(ovreg,ovreg,AT);
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MFHI(ovreg);
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SRA(AT,rr,31);
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MFLO(rr);
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MULT(ra, rb);
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}
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else
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MUL(rr, ra, rb);
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case LIR_mulxov:
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t = registerAllocTmp(allow);
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// Overflow indication required
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// Do a 32x32 signed multiply generating a 64 bit result
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// Compare bit31 of the result with the high order bits
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// mult $ra,$rb
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// mflo $rr # result to $rr
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// sra $t,$rr,31 # $t = 0x00000000 or 0xffffffff
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// mfhi $at
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// xor $at,$at,$t # sets $at to nonzero if overflow
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XOR(AT, AT, t);
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MFHI(AT);
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SRA(t, rr, 31);
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MFLO(rr);
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MULT(ra, rb);
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break;
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case LIR_mul:
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MUL(rr, ra, rb);
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break;
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case LIR_div:
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case LIR_mod:
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default:
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BADOPCODE(op);
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}
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done:
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ovreg = deprecated_UnknownReg; // Potential overflow has been handled
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TAG("asm_arith(ins=%p{%s})", ins, lirNames[ins->opcode()]);
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}
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void Assembler::asm_store64(LOpcode op, LIns *value, int dr, LIns *base)
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{
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Register rbase;
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// NanoAssert((dr & 7) == 0);
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#if NANOJIT_64BIT
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NanoAssert (op == LIR_stqi || op == LIR_st32f || op == LIR_stfi);
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#else
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NanoAssert (op == LIR_st32f || op == LIR_stfi);
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#endif
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switch (op) {
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case LIR_stfi:
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// handled by mainline code below for now
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if (cpu_has_fpu) {
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Register rbase = findRegFor(base, GpRegs);
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if (value->isconstf())
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asm_store_imm64(value, dr, rbase);
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else {
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Register fr = findRegFor(value, FpRegs);
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asm_ldst64(true, fr, dr, rbase);
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}
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}
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else {
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Register rbase = findRegFor(base, GpRegs);
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// *(uint64_t*)(rb+dr) = *(uint64_t*)(FP+da)
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int ds = findMemFor(value);
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// lw $at,ds(FP)
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// sw $at,dr($rbase)
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// lw $at,ds+4(FP)
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// sw $at,dr+4($rbase)
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SW(AT, dr+4, rbase);
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LW(AT, ds+4, FP);
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SW(AT, dr, rbase);
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LW(AT, ds, FP);
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}
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break;
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case LIR_st32f:
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NanoAssertMsg(0, "NJ_EXPANDED_LOADSTORE_SUPPORTED not yet supported for this architecture");
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@ -1094,41 +1130,6 @@ namespace nanojit
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return;
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}
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if (op == LIR_stfi) {
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if (base->isop(LIR_alloc)) {
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rbase = FP;
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dr += findMemFor(base);
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}
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else
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rbase = findRegFor(base, GpRegs);
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if (value->isconstf())
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asm_store_imm64(value, dr, rbase);
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else if (!cpu_has_fpu || value->isop(LIR_ldq)) {
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int ds = findMemFor(value);
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// lw $at,ds(FP)
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// sw $at,dr($rbase)
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// lw $at,ds+4(FP)
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// sw $at,dr+4($rbase)
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SW(AT, dr+4, rbase);
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LW(AT, ds+4, FP);
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SW(AT, dr, rbase);
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LW(AT, ds, FP);
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}
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else {
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NanoAssert (cpu_has_fpu);
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// if value is already in a reg, use that, otherwise
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// allocate an FPU register
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Register fr = !value->isInReg() ?
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findRegFor(value, FpRegs) : value->getReg();
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asm_ldst64(true, fr, dr, rbase);
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}
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}
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else
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BADOPCODE(op);
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TAG("asm_store64(value=%p{%s}, dr=%d, base=%p{%s})",
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value, lirNames[value->opcode()], dr, base, lirNames[base->opcode()]);
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}
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|
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@ -1231,19 +1232,17 @@ namespace nanojit
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#define SEG(addr) (uint32_t(addr) & 0xf0000000)
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#define SEGOFFS(addr) (uint32_t(addr) & 0x0fffffff)
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NIns* Assembler::asm_branch(bool branchOnFalse, LIns *cond, NIns * const targ)
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// Check that the branch target is in range
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// Generate a trampoline if it isn't
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// Emits the branch delay slot instruction
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NIns* Assembler::asm_branchtarget(NIns * const targ)
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{
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LOpcode condop = cond->opcode();
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NanoAssert(cond->isCond());
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bool inrange;
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RegisterMask allow = isFCmpOpcode(condop) ? FpRegs : GpRegs;
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LIns *a = cond->oprnd1();
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LIns *b = cond->oprnd2();
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Register ra = findRegFor(a, allow);
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Register rb = (b==a) ? ra : findRegFor(b, allow & ~rmask(ra));
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NIns *btarg = targ;
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// do initial underrun check here to ensure that inrange test is correct
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// allow
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if (targ)
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underrunProtect(2 * 4); // branch + delay slot
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|
|
@ -1260,57 +1259,78 @@ namespace nanojit
|
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// If the branch target is known and in range we can just generate a branch
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// Otherwise generate a branch to a trampoline that will be stored in the
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// literal area
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if (inrange) {
|
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if (inrange)
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NOP();
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}
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else {
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underrunProtect(5 * 4); // worst case: branch;lui and ori,jr,nop
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NIns *tramp = _nSlot;
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if (targ) {
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// Can the target be reached by a jump instruction?
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if (SEG(targ) == SEG(tramp)) {
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// bxxx trampoline
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// nop
|
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// ...
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// [linkedinstructions]
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// bxxx trampoline
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// nop
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// ...
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// trampoline:
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// j targ
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// nop
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// NB trampoline code is emitted in the correct order!
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tramp = _nSlot;
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trampJ(targ);
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trampNOP(); // delay slot
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||||
// j targ
|
||||
// nop
|
||||
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underrunProtect(4 * 4); // keep bxx and trampoline together
|
||||
|
||||
NOP(); // delay slot
|
||||
|
||||
// NB trampoline code is emitted in the correct order
|
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trampJ(targ);
|
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trampNOP(); // trampoline delay slot
|
||||
|
||||
NOP(); // delay slot
|
||||
}
|
||||
else {
|
||||
// bxxx trampoline
|
||||
// lui $at,((targ)>>16) & 0xffff
|
||||
// ...
|
||||
// [linkedinstructions]
|
||||
// bxxx trampoline
|
||||
// lui $at,%hi(targ)
|
||||
// ...
|
||||
// trampoline:
|
||||
// ori $at,targ & 0xffff
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// jr $at
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// nop
|
||||
tramp = _nSlot;
|
||||
trampADDIU(AT,AT,lo(uint32_t(targ)));
|
||||
trampJR(AT);
|
||||
trampNOP(); // delay slot
|
||||
// addiu $at,%lo(targ)
|
||||
// jr $at
|
||||
// nop
|
||||
|
||||
underrunProtect(5 * 4); // keep bxx and trampoline together
|
||||
|
||||
LUI(AT,hi(uint32_t(targ))); // delay slot
|
||||
|
||||
// NB trampoline code is emitted in the correct order
|
||||
trampADDIU(AT, AT, lo(uint32_t(targ)));
|
||||
trampJR(AT);
|
||||
trampNOP(); // trampoline delay slot
|
||||
|
||||
LUI(AT,hi(uint32_t(targ))); // delay slot
|
||||
}
|
||||
}
|
||||
else {
|
||||
// Worst case is lui;ori;jr;nop as above
|
||||
// Best case is branch to trampoline can be replaced with branch to target
|
||||
// Worst case is bxxx,lui addiu;jr;nop as above
|
||||
// Best case is branch to trampoline can be replaced
|
||||
// with branch to target in which case the trampoline will be abandoned
|
||||
// Fixup handled in nPatchBranch
|
||||
|
||||
underrunProtect(5 * 4); // keep bxx and trampoline together
|
||||
|
||||
NOP(); // delay slot
|
||||
|
||||
trampNOP();
|
||||
trampNOP();
|
||||
trampNOP();
|
||||
|
||||
NOP();
|
||||
}
|
||||
btarg = tramp;
|
||||
}
|
||||
|
||||
return btarg;
|
||||
}
|
||||
|
||||
|
||||
NIns* Assembler::asm_bxx(bool branchOnFalse, LOpcode condop, Register ra, Register rb, NIns * const targ)
|
||||
{
|
||||
NIns *patch = NULL;
|
||||
NIns *btarg = asm_branchtarget(targ);
|
||||
|
||||
if (cpu_has_fpu && isFCmpOpcode(condop)) {
|
||||
// c.xx.d $ra,$rb
|
||||
// bc1x btarg
|
||||
|
|
@ -1323,7 +1343,7 @@ namespace nanojit
|
|||
patch = _nIns;
|
||||
if (cpu_has_fpuhazard)
|
||||
NOP();
|
||||
C_EQ_D(ra,rb);
|
||||
C_EQ_D(ra, rb);
|
||||
break;
|
||||
case LIR_flt:
|
||||
if (branchOnFalse)
|
||||
|
|
@ -1333,7 +1353,7 @@ namespace nanojit
|
|||
patch = _nIns;
|
||||
if (cpu_has_fpuhazard)
|
||||
NOP();
|
||||
C_LT_D(ra,rb);
|
||||
C_LT_D(ra, rb);
|
||||
break;
|
||||
case LIR_fgt:
|
||||
if (branchOnFalse)
|
||||
|
|
@ -1343,7 +1363,7 @@ namespace nanojit
|
|||
patch = _nIns;
|
||||
if (cpu_has_fpuhazard)
|
||||
NOP();
|
||||
C_LT_D(rb,ra);
|
||||
C_LT_D(rb, ra);
|
||||
break;
|
||||
case LIR_fle:
|
||||
if (branchOnFalse)
|
||||
|
|
@ -1353,7 +1373,7 @@ namespace nanojit
|
|||
patch = _nIns;
|
||||
if (cpu_has_fpuhazard)
|
||||
NOP();
|
||||
C_LE_D(ra,rb);
|
||||
C_LE_D(ra, rb);
|
||||
break;
|
||||
case LIR_fge:
|
||||
if (branchOnFalse)
|
||||
|
|
@ -1363,7 +1383,7 @@ namespace nanojit
|
|||
patch = _nIns;
|
||||
if (cpu_has_fpuhazard)
|
||||
NOP();
|
||||
C_LE_D(rb,ra);
|
||||
C_LE_D(rb, ra);
|
||||
break;
|
||||
default:
|
||||
BADOPCODE(condop);
|
||||
|
|
@ -1379,91 +1399,115 @@ namespace nanojit
|
|||
// special case
|
||||
// b(ne|eq) $ra,$rb,btarg
|
||||
if (branchOnFalse)
|
||||
BNE(ra,rb,btarg);
|
||||
BNE(ra, rb, btarg);
|
||||
else
|
||||
BEQ(ra,rb,btarg);
|
||||
BEQ(ra, rb, btarg);
|
||||
patch = _nIns;
|
||||
break;
|
||||
case LIR_lt:
|
||||
if (branchOnFalse)
|
||||
BEQ(AT,ZERO,btarg);
|
||||
BEQ(AT, ZERO, btarg);
|
||||
else
|
||||
BNE(AT,ZERO,btarg);
|
||||
BNE(AT, ZERO, btarg);
|
||||
patch = _nIns;
|
||||
SLT(AT,ra,rb);
|
||||
SLT(AT, ra, rb);
|
||||
break;
|
||||
case LIR_gt:
|
||||
if (branchOnFalse)
|
||||
BEQ(AT,ZERO,btarg);
|
||||
BEQ(AT, ZERO, btarg);
|
||||
else
|
||||
BNE(AT,ZERO,btarg);
|
||||
BNE(AT, ZERO, btarg);
|
||||
patch = _nIns;
|
||||
SLT(AT,rb,ra);
|
||||
SLT(AT, rb, ra);
|
||||
break;
|
||||
case LIR_le:
|
||||
if (branchOnFalse)
|
||||
BNE(AT,ZERO,btarg);
|
||||
BNE(AT, ZERO, btarg);
|
||||
else
|
||||
BEQ(AT,ZERO,btarg);
|
||||
BEQ(AT, ZERO, btarg);
|
||||
patch = _nIns;
|
||||
SLT(AT,rb,ra);
|
||||
SLT(AT, rb, ra);
|
||||
break;
|
||||
case LIR_ge:
|
||||
if (branchOnFalse)
|
||||
BNE(AT,ZERO,btarg);
|
||||
BNE(AT, ZERO, btarg);
|
||||
else
|
||||
BEQ(AT,ZERO,btarg);
|
||||
BEQ(AT, ZERO, btarg);
|
||||
patch = _nIns;
|
||||
SLT(AT,ra,rb);
|
||||
SLT(AT, ra, rb);
|
||||
break;
|
||||
case LIR_ult:
|
||||
if (branchOnFalse)
|
||||
BEQ(AT,ZERO,btarg);
|
||||
BEQ(AT, ZERO, btarg);
|
||||
else
|
||||
BNE(AT,ZERO,btarg);
|
||||
BNE(AT, ZERO, btarg);
|
||||
patch = _nIns;
|
||||
SLTU(AT,ra,rb);
|
||||
SLTU(AT, ra, rb);
|
||||
break;
|
||||
case LIR_ugt:
|
||||
if (branchOnFalse)
|
||||
BEQ(AT,ZERO,btarg);
|
||||
BEQ(AT, ZERO, btarg);
|
||||
else
|
||||
BNE(AT,ZERO,btarg);
|
||||
BNE(AT, ZERO, btarg);
|
||||
patch = _nIns;
|
||||
SLTU(AT,rb,ra);
|
||||
SLTU(AT, rb, ra);
|
||||
break;
|
||||
case LIR_ule:
|
||||
if (branchOnFalse)
|
||||
BNE(AT,ZERO,btarg);
|
||||
BNE(AT, ZERO, btarg);
|
||||
else
|
||||
BEQ(AT,ZERO,btarg);
|
||||
BEQ(AT, ZERO, btarg);
|
||||
patch = _nIns;
|
||||
SLT(AT,rb,ra);
|
||||
SLT(AT, rb, ra);
|
||||
break;
|
||||
case LIR_uge:
|
||||
if (branchOnFalse)
|
||||
BNE(AT,ZERO,btarg);
|
||||
BNE(AT, ZERO, btarg);
|
||||
else
|
||||
BEQ(AT,ZERO,btarg);
|
||||
BEQ(AT, ZERO, btarg);
|
||||
patch = _nIns;
|
||||
SLTU(AT,ra,rb);
|
||||
SLTU(AT, ra, rb);
|
||||
break;
|
||||
default:
|
||||
BADOPCODE(condop);
|
||||
}
|
||||
}
|
||||
TAG("asm_branch(branchOnFalse=%d, cond=%p{%s}, targ=%p)",
|
||||
branchOnFalse, cond, lirNames[cond->opcode()], targ);
|
||||
TAG("asm_bxx(branchOnFalse=%d, condop=%s, ra=%s rb=%s targ=%p)",
|
||||
branchOnFalse, lirNames[condop], gpn(ra), gpn(rb), targ);
|
||||
return patch;
|
||||
}
|
||||
|
||||
void Assembler::asm_branch_xov(LOpcode op, NIns* target)
|
||||
{
|
||||
USE(op);
|
||||
NanoAssert(target != NULL);
|
||||
|
||||
(void) asm_bxx(true, LIR_eq, AT, ZERO, target);
|
||||
|
||||
TAG("asm_branch_xov(op=%s, target=%p)", lirNames[op], target);
|
||||
}
|
||||
|
||||
NIns* Assembler::asm_branch(bool branchOnFalse, LIns *cond, NIns * const targ)
|
||||
{
|
||||
NanoAssert(cond->isCmp());
|
||||
LOpcode condop = cond->opcode();
|
||||
RegisterMask allow = isFCmpOpcode(condop) ? FpRegs : GpRegs;
|
||||
LIns *a = cond->oprnd1();
|
||||
LIns *b = cond->oprnd2();
|
||||
Register ra = findRegFor(a, allow);
|
||||
Register rb = (b==a) ? ra : findRegFor(b, allow & ~rmask(ra));
|
||||
|
||||
return asm_bxx(branchOnFalse, condop, ra, rb, targ);
|
||||
}
|
||||
|
||||
void Assembler::asm_j(NIns * const targ, bool bdelay)
|
||||
{
|
||||
underrunProtect(2*4); // branch + delay
|
||||
if (targ)
|
||||
NanoAssert(SEG(targ) == SEG(_nIns));
|
||||
if (bdelay)
|
||||
NanoAssert(targ != NULL);
|
||||
NanoAssert(SEG(targ) == SEG(_nIns));
|
||||
if (bdelay) {
|
||||
underrunProtect(2*4); // j + delay
|
||||
NOP();
|
||||
}
|
||||
J(targ);
|
||||
TAG("asm_j(targ=%p) bdelay=%d", targ);
|
||||
}
|
||||
|
|
@ -1563,7 +1607,7 @@ namespace nanojit
|
|||
|
||||
// FIXME: Put one of the argument moves into the BDS slot
|
||||
|
||||
underrunProtect(2*4); // branch+delay
|
||||
underrunProtect(2*4); // jalr+delay
|
||||
NOP();
|
||||
JALR(T9);
|
||||
|
||||
|
|
@ -1685,6 +1729,7 @@ namespace nanojit
|
|||
if (destKnown) {
|
||||
// j _fragEntry
|
||||
// move $v0,$zero
|
||||
underrunProtect(2 * 4); // j + branch delay
|
||||
MOVE(V0, ZERO);
|
||||
asm_j(frag->fragEntry, false);
|
||||
}
|
||||
|
|
@ -1698,6 +1743,7 @@ namespace nanojit
|
|||
// lui $v0,%hi(lr)
|
||||
// j _epilogue
|
||||
// addiu $v0,%lo(lr)
|
||||
underrunProtect(2 * 4); // j + branch delay
|
||||
ADDIU(V0, V0, lo(int32_t(lr)));
|
||||
asm_j(_epilogue, false);
|
||||
LUI(V0, hi(int32_t(lr)));
|
||||
|
|
@ -1707,7 +1753,6 @@ namespace nanojit
|
|||
// profiling for the exit
|
||||
verbose_only(
|
||||
if (_logc->lcbits & LC_FragProfile) {
|
||||
underrunProtect(4*4);
|
||||
// lui $fp,%hi(profCount)
|
||||
// lw $at,%lo(profCount)(fp)
|
||||
// addiu $at,1
|
||||
|
|
@ -1841,8 +1886,10 @@ namespace nanojit
|
|||
|
||||
if (op == LIR_icall)
|
||||
prefer = rmask(V0);
|
||||
#if NJ_SOFTFLOAT_SUPPORTED
|
||||
else if (op == LIR_callh)
|
||||
prefer = rmask(V1);
|
||||
#endif
|
||||
else if (op == LIR_fcall)
|
||||
prefer = rmask(FV0);
|
||||
else if (op == LIR_param) {
|
||||
|
|
|
|||
|
|
@ -175,15 +175,14 @@ namespace nanojit
|
|||
void asm_li_d(Register fr, int32_t msw, int32_t lsw); \
|
||||
void asm_li(Register r, int32_t imm); \
|
||||
void asm_j(NIns*, bool bdelay); \
|
||||
NIns *asm_branch_far(bool, LIns*, NIns*); \
|
||||
NIns *asm_branch_near(bool, LIns*, NIns*); \
|
||||
void asm_cmp(LOpcode condop, LIns *a, LIns *b, Register cr); \
|
||||
void asm_move(Register d, Register s); \
|
||||
void asm_regarg(ArgType ty, LInsp p, Register r); \
|
||||
void asm_stkarg(LInsp arg, int stkd); \
|
||||
void asm_arg(ArgType ty, LInsp arg, Register& r, Register& fr, int& stkd); \
|
||||
void asm_arg_64(LInsp arg, Register& r, Register& fr, int& stkd) ;
|
||||
|
||||
void asm_arg_64(LInsp arg, Register& r, Register& fr, int& stkd); \
|
||||
NIns *asm_branchtarget(NIns*); \
|
||||
NIns *asm_bxx(bool, LOpcode, Register, Register, NIns*);
|
||||
|
||||
// REQ: Platform specific declarations to include in RegAlloc class
|
||||
#define DECLARE_PLATFORM_REGALLOC()
|
||||
|
|
@ -227,7 +226,7 @@ namespace nanojit
|
|||
|
||||
#define MR(d, s) asm_move(d, s)
|
||||
|
||||
// underrun guarantees that there is always room to insert a jump
|
||||
// underrun guarantees that there is always room to insert a jump and branch delay slot
|
||||
#define JMP(t) asm_j(t, true)
|
||||
|
||||
// Opcodes: bits 31..26
|
||||
|
|
@ -543,10 +542,10 @@ namespace nanojit
|
|||
|
||||
|
||||
/* FPU instructions */
|
||||
#ifdef NJ_SOFTFLOAT
|
||||
#ifdef NJ_SOFTFLOAT_SUPPORTED
|
||||
|
||||
#if !defined(__mips_soft_float) || __mips_soft_float != 1
|
||||
#error NJ_SOFTFLOAT defined but not compiled with -msoft-float
|
||||
#error NJ_SOFTFLOAT_SUPPORTED defined but not compiled with -msoft-float
|
||||
#endif
|
||||
|
||||
#define LWC1(ft, offset, base) NanoAssertMsg(0, "softfloat LWC1")
|
||||
|
|
@ -574,7 +573,7 @@ namespace nanojit
|
|||
#else
|
||||
|
||||
#if defined(__mips_soft_float) && __mips_soft_float != 0
|
||||
#error compiled with -msoft-float but NJ_SOFTFLOAT not defined
|
||||
#error compiled with -msoft-float but NJ_SOFTFLOAT_SUPPORTED not defined
|
||||
#endif
|
||||
|
||||
#define FOP_FMT2(ffmt, fd, fs, func, name) \
|
||||
|
|
|
|||
Загрузка…
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