зеркало из https://github.com/mozilla/pjs.git
Bug 515309 - nanojit: kill reservations in the ARM backend. r=Jacob.Bramley.
--HG-- extra : convert_revision : 271317c774639b9604d3e9ab9d67d615b5166c64
This commit is contained in:
Nicholas Nethercote
Родитель
27ac87ccf8
Коммит
5f71541ade
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@ -630,7 +630,7 @@ Assembler::asm_arg_64(LInsp arg, Register& r, int& stkd)
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if (ARM_VFP) {
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fp_reg = findRegFor(arg, FpRegs);
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NanoAssert(fp_reg != UnknownReg);
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NanoAssert(isKnownReg(fp_reg));
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}
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#ifdef NJ_ARM_EABI
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@ -718,16 +718,15 @@ Assembler::asm_arg_64(LInsp arg, Register& r, int& stkd)
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void
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Assembler::asm_regarg(ArgSize sz, LInsp p, Register r)
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{
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NanoAssert(r != UnknownReg);
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NanoAssert(isKnownReg(r));
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if (sz & ARGSIZE_MASK_INT)
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{
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// arg goes in specific register
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if (p->isconst()) {
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asm_ld_imm(r, p->imm32());
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} else {
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Reservation* rA = getresv(p);
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if (rA) {
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if (rA->reg == UnknownReg) {
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if (p->isUsed()) {
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if (!p->hasKnownReg()) {
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// load it into the arg reg
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int d = findMemFor(p);
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if (p->isop(LIR_alloc)) {
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@ -737,7 +736,7 @@ Assembler::asm_regarg(ArgSize sz, LInsp p, Register r)
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}
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} else {
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// it must be in a saved reg
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MOV(r, rA->reg);
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MOV(r, p->getReg());
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}
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}
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else {
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@ -763,16 +762,16 @@ Assembler::asm_regarg(ArgSize sz, LInsp p, Register r)
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void
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Assembler::asm_stkarg(LInsp arg, int stkd)
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{
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Reservation* argRes = getresv(arg);
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bool isQuad = arg->isQuad();
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if (argRes && (argRes->reg != UnknownReg)) {
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Register rr;
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if (arg->isUsed() && (rr = arg->getReg(), isKnownReg(rr))) {
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// The argument resides somewhere in registers, so we simply need to
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// push it onto the stack.
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if (!ARM_VFP || !isQuad) {
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NanoAssert(IsGpReg(argRes->reg));
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NanoAssert(IsGpReg(rr));
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STR(argRes->reg, SP, stkd);
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STR(rr, SP, stkd);
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} else {
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// According to the comments in asm_arg_64, LIR_qjoin
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// can have a 64-bit argument even if VFP is disabled. However,
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@ -781,14 +780,14 @@ Assembler::asm_stkarg(LInsp arg, int stkd)
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// assert that we will never get 64-bit arguments unless VFP is
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// available.
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NanoAssert(ARM_VFP);
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NanoAssert(IsFpReg(argRes->reg));
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NanoAssert(IsFpReg(rr));
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#ifdef NJ_ARM_EABI
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// EABI requires that 64-bit arguments are 64-bit aligned.
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NanoAssert((stkd & 7) == 0);
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#endif
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FSTD(argRes->reg, SP, stkd);
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FSTD(rr, SP, stkd);
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}
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} else {
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// The argument does not reside in registers, so we need to get some
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@ -833,18 +832,17 @@ Assembler::asm_call(LInsp ins)
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// necessary here for floating point calls, but not for integer calls.
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if (ARM_VFP && ins->isUsed()) {
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// Determine the size (and type) of the instruction result.
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ArgSize rsize = (ArgSize)(call->_argtypes & ARGSIZE_MASK_ANY);
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ArgSize rsize = (ArgSize)(call->_argtypes & ARGSIZE_MASK_ANY);
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// If the result size is a floating-point value, treat the result
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// specially, as described previously.
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if (rsize == ARGSIZE_F) {
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Reservation * callRes = getresv(ins);
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Register rr = callRes->reg;
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Register rr = ins->getReg();
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NanoAssert(ins->opcode() == LIR_fcall);
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if (rr == UnknownReg) {
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int d = disp(callRes);
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if (!isKnownReg(rr)) {
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int d = disp(ins);
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NanoAssert(d != 0);
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freeRsrcOf(ins, false);
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@ -1072,16 +1070,13 @@ Assembler::asm_qjoin(LIns *ins)
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void
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Assembler::asm_store32(LIns *value, int dr, LIns *base)
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{
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Reservation *rA, *rB;
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Register ra, rb;
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if (base->isop(LIR_alloc)) {
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rb = FP;
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dr += findMemFor(base);
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ra = findRegFor(value, GpRegs);
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} else {
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findRegFor2(GpRegs, value, rA, base, rB);
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ra = rA->reg;
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rb = rB->reg;
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findRegFor2b(GpRegs, value, ra, base, rb);
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}
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if (!isS12(dr)) {
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@ -1096,10 +1091,10 @@ void
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Assembler::asm_restore(LInsp i, Reservation *resv, Register r)
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{
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if (i->isop(LIR_alloc)) {
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asm_add_imm(r, FP, disp(resv));
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asm_add_imm(r, FP, disp(i));
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} else if (i->isconst()) {
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if (!resv->arIndex) {
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i->resv()->clear();
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if (!i->getArIndex()) {
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i->markAsClear();
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}
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asm_ld_imm(r, i->imm32());
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}
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@ -1153,10 +1148,8 @@ Assembler::asm_load64(LInsp ins)
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LIns* base = ins->oprnd1();
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int offset = ins->disp();
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Reservation *resv = getresv(ins);
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NanoAssert(resv);
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Register rr = resv->reg;
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int d = disp(resv);
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Register rr = ins->getReg();
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int d = disp(ins);
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Register rb = findRegFor(base, GpRegs);
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NanoAssert(IsGpReg(rb));
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@ -1164,7 +1157,7 @@ Assembler::asm_load64(LInsp ins)
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//output("--- load64: Finished register allocation.");
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if (ARM_VFP && rr != UnknownReg) {
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if (ARM_VFP && isKnownReg(rr)) {
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// VFP is enabled and the result will go into a register.
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NanoAssert(IsFpReg(rr));
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@ -1178,7 +1171,7 @@ Assembler::asm_load64(LInsp ins)
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// Either VFP is not available or the result needs to go into memory;
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// in either case, VFP instructions are not required. Note that the
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// result will never be loaded into registers if VFP is not available.
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NanoAssert(resv->reg == UnknownReg);
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NanoAssert(!isKnownReg(rr));
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NanoAssert(d != 0);
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// Check that the offset is 8-byte (64-bit) aligned.
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@ -1197,7 +1190,6 @@ Assembler::asm_store64(LInsp value, int dr, LInsp base)
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//asm_output("<<< store64 (dr: %d)", dr);
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if (ARM_VFP) {
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//Reservation *valResv = getresv(value);
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Register rb = findRegFor(base, GpRegs);
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if (value->isconstq()) {
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@ -1214,8 +1206,8 @@ Assembler::asm_store64(LInsp value, int dr, LInsp base)
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Register rv = findRegFor(value, FpRegs);
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NanoAssert(rb != UnknownReg);
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NanoAssert(rv != UnknownReg);
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NanoAssert(isKnownReg(rb));
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NanoAssert(isKnownReg(rv));
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Register baseReg = rb;
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intptr_t baseOffset = dr;
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@ -1276,13 +1268,12 @@ Assembler::asm_quad(LInsp ins)
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{
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//asm_output(">>> asm_quad");
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Reservation *res = getresv(ins);
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int d = disp(res);
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Register rr = res->reg;
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int d = disp(ins);
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Register rr = ins->getReg();
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freeRsrcOf(ins, false);
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if (ARM_VFP && rr != UnknownReg)
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if (ARM_VFP && isKnownReg(rr))
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{
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asm_spill(rr, d, false, true);
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@ -1805,7 +1796,7 @@ Assembler::asm_i2f(LInsp ins)
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Register srcr = findRegFor(ins->oprnd1(), GpRegs);
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// todo: support int value in memory, as per x86
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NanoAssert(srcr != UnknownReg);
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NanoAssert(isKnownReg(srcr));
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FSITOD(rr, FpSingleScratch);
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FMSR(FpSingleScratch, srcr);
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@ -1818,7 +1809,7 @@ Assembler::asm_u2f(LInsp ins)
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Register sr = findRegFor(ins->oprnd1(), GpRegs);
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// todo: support int value in memory, as per x86
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NanoAssert(sr != UnknownReg);
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NanoAssert(isKnownReg(sr));
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FUITOD(rr, FpSingleScratch);
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FMSR(FpSingleScratch, sr);
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@ -1830,13 +1821,9 @@ Assembler::asm_fneg(LInsp ins)
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LInsp lhs = ins->oprnd1();
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Register rr = prepResultReg(ins, FpRegs);
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Reservation* rA = getresv(lhs);
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Register sr;
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if (!rA || rA->reg == UnknownReg)
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sr = findRegFor(lhs, FpRegs);
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else
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sr = rA->reg;
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Register sr = ( lhs->isUnusedOrHasUnknownReg()
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? findRegFor(lhs, FpRegs)
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: lhs->getReg() );
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FNEGD(rr, sr);
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}
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@ -1878,10 +1865,8 @@ Assembler::asm_fcmp(LInsp ins)
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NanoAssert(op >= LIR_feq && op <= LIR_fge);
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Reservation *rA, *rB;
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findRegFor2(FpRegs, lhs, rA, rhs, rB);
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Register ra = rA->reg;
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Register rb = rB->reg;
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Register ra, rb;
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findRegFor2b(FpRegs, lhs, ra, rhs, rb);
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int e_bit = (op != LIR_feq);
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@ -1998,7 +1983,6 @@ Assembler::asm_cmp(LIns *cond)
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LInsp lhs = cond->oprnd1();
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LInsp rhs = cond->oprnd2();
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Reservation *rA, *rB;
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// Not supported yet.
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NanoAssert(!lhs->isQuad() && !rhs->isQuad());
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@ -2017,9 +2001,8 @@ Assembler::asm_cmp(LIns *cond)
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NanoAssert(0);
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}
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} else {
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findRegFor2(GpRegs, lhs, rA, rhs, rB);
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Register ra = rA->reg;
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Register rb = rB->reg;
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Register ra, rb;
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findRegFor2b(GpRegs, lhs, ra, rhs, rb);
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CMP(ra, rb);
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}
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}
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@ -2096,17 +2079,16 @@ Assembler::asm_arith(LInsp ins)
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// We always need the result register and the first operand register.
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Register rr = prepResultReg(ins, allow);
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Reservation * rA = getresv(lhs);
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Register ra = UnknownReg;
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Register rb = UnknownReg;
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// If this is the last use of lhs in reg, we can re-use the result reg.
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if (!rA || (ra = rA->reg) == UnknownReg)
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ra = findSpecificRegFor(lhs, rr);
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// Else, lhs already has a register assigned.
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Register ra = ( lhs->isUnusedOrHasUnknownReg()
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? findSpecificRegFor(lhs, rr)
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: lhs->getReg() );
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// Don't re-use the registers we've already allocated.
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NanoAssert(rr != UnknownReg);
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NanoAssert(ra != UnknownReg);
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NanoAssert(isKnownReg(rr));
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NanoAssert(isKnownReg(ra));
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allow &= ~rmask(rr);
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allow &= ~rmask(ra);
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@ -2129,7 +2111,7 @@ Assembler::asm_arith(LInsp ins)
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Register rs = prepResultReg(ins, allow);
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int d = findMemFor(lhs) + rhs->imm32();
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NanoAssert(rs != UnknownReg);
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NanoAssert(isKnownReg(rs));
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asm_add_imm(rs, FP, d);
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}
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@ -2158,15 +2140,16 @@ Assembler::asm_arith(LInsp ins)
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// The rhs is either a register or cannot be encoded as a constant.
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Register rb;
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if (lhs == rhs) {
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rb = ra;
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} else {
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rb = asm_binop_rhs_reg(ins);
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if (rb == UnknownReg)
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if (!isKnownReg(rb))
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rb = findRegFor(rhs, allow);
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allow &= ~rmask(rb);
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}
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NanoAssert(rb != UnknownReg);
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NanoAssert(isKnownReg(rb));
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switch (op)
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{
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@ -2242,13 +2225,12 @@ Assembler::asm_neg_not(LInsp ins)
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Register rr = prepResultReg(ins, GpRegs);
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LIns* lhs = ins->oprnd1();
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Reservation *rA = getresv(lhs);
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// if this is last use of lhs in reg, we can re-use result reg
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Register ra;
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if (rA == 0 || (ra=rA->reg) == UnknownReg)
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ra = findSpecificRegFor(lhs, rr);
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// else, rA already has a register assigned.
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NanoAssert(ra != UnknownReg);
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// If this is the last use of lhs in reg, we can re-use result reg.
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// Else, lhs already has a register assigned.
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Register ra = ( lhs->isUnusedOrHasUnknownReg()
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? findSpecificRegFor(lhs, rr)
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: lhs->getReg() );
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NanoAssert(isKnownReg(ra));
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if (op == LIR_not)
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MVN(rr, ra);
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