зеркало из https://github.com/mozilla/pjs.git
Backout alignment-breaking patches for Bug 493821.
This commit is contained in:
Graydon Hoare
Родитель
4b6aaa7edf
Коммит
803a4b60d9
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@ -306,7 +306,8 @@ namespace nanojit
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ensureRoom(1);
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LInsp l = _buf->next();
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l->initOpcodeAndClearResv(LIR_quad);
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l->i64.imm64 = imm;
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l->i64.imm64_0 = int32_t(imm);
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l->i64.imm64_1 = int32_t(imm>>32);
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_buf->commit(1);
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_buf->_stats.lir++;
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return l;
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@ -468,13 +469,17 @@ namespace nanojit
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uint64_t LIns::imm64() const
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{
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NanoAssert(isconstq());
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return i64.imm64;
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return (uint64_t(i64.imm64_1) << 32) | uint64_t(i64.imm64_0);
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}
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double LIns::imm64f() const
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{
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NanoAssert(isconstq());
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return i64.d;
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union {
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double f;
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uint64_t q;
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} u;
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u.q = imm64();
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return u.f;
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}
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inline uint32_t argSlots(uint32_t argc) {
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@ -526,13 +531,13 @@ namespace nanojit
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{
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if (v == LIR_qlo) {
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if (i->isconstq())
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return insImm(i->imm64lo());
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return insImm(i->imm64_0());
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if (i->isop(LIR_qjoin))
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return i->oprnd1();
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}
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else if (v == LIR_qhi) {
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if (i->isconstq())
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return insImm(i->imm64hi());
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return insImm(i->imm64_1());
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if (i->isop(LIR_qjoin))
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return i->oprnd2();
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}
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@ -1513,10 +1518,10 @@ namespace nanojit
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#if defined NANOJIT_64BIT
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sprintf(buf, "#0x%lx", (nj_printf_ld)ref->imm64());
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#else
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formatImm(ref->imm64hi(), buf);
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formatImm(ref->imm64_1(), buf);
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buf += strlen(buf);
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*buf++ = ':';
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formatImm(ref->imm64lo(), buf);
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formatImm(ref->imm64_0(), buf);
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#endif
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}
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else if (ref->isconst()) {
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@ -1564,7 +1569,7 @@ namespace nanojit
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case LIR_quad:
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{
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sprintf(s, "#%X:%X /* %g */", i->imm64hi(), i->imm64lo(), i->imm64f());
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sprintf(s, "#%X:%X /* %g */", i->imm64_1(), i->imm64_0(), i->imm64f());
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break;
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}
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@ -219,11 +219,11 @@ namespace nanojit
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};
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// Used for LIR_quad.
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union i64_type
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{
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uint64_t imm64;
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double d;
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};
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struct i64_type
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{
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int32_t imm64_0;
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int32_t imm64_1;
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};
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#undef _sign_int
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@ -249,9 +249,9 @@ namespace nanojit
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inline uint8_t imm8() const { return c.imm8a; }
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inline uint8_t imm8b() const { return c.imm8b; }
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inline int32_t imm32() const { NanoAssert(isconst()); return i.imm32; }
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inline int32_t imm64_0() const { NanoAssert(isconstq()); return i64.imm64_0; }
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inline int32_t imm64_1() const { NanoAssert(isconstq()); return i64.imm64_1; }
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uint64_t imm64() const;
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uint32_t imm64lo() const { return uint32_t(imm64()); }
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uint32_t imm64hi() const { return uint32_t(imm64() >> 32); }
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double imm64f() const;
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Reservation* resv() { return &firstWord; }
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void* payload() const;
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@ -246,7 +246,7 @@ Assembler::asm_arg(ArgSize sz, LInsp arg, Register& r, int& stkd)
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if (arg->isop(LIR_quad)) {
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// XXX use some load-multiple action here from our const pool?
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int32_t v = arg->imm64lo(); // for the first iteration
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int32_t v = arg->imm64_0(); // for the first iteration
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for (int k = 0; k < 2; k++) {
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if (r != UnknownReg) {
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asm_ld_imm(r, v);
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@ -258,7 +258,7 @@ Assembler::asm_arg(ArgSize sz, LInsp arg, Register& r, int& stkd)
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asm_ld_imm(IP, v);
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stkd += 4;
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}
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v = arg->imm64hi(); // for the second iteration
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v = arg->imm64_1(); // for the second iteration
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}
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} else {
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int d = findMemFor(arg);
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@ -691,9 +691,9 @@ Assembler::asm_store64(LInsp value, int dr, LInsp base)
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// XXX use another reg, get rid of dependency
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STR(IP, rb, dr);
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LD32_nochk(IP, value->imm64lo());
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LD32_nochk(IP, value->imm64_0());
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STR(IP, rb, dr+4);
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LD32_nochk(IP, value->imm64hi());
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LD32_nochk(IP, value->imm64_1());
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return;
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}
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@ -721,7 +721,7 @@ Assembler::asm_store64(LInsp value, int dr, LInsp base)
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// has the right value
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if (value->isconstq()) {
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underrunProtect(4*4);
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asm_quad_nochk(rv, value->imm64lo(), value->imm64hi());
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asm_quad_nochk(rv, value->imm64_0(), value->imm64_1());
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}
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} else {
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int da = findMemFor(value);
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@ -735,7 +735,7 @@ Assembler::asm_store64(LInsp value, int dr, LInsp base)
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// stick a quad into register rr, where p points to the two
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// 32-bit parts of the quad, optinally also storing at FP+d
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void
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Assembler::asm_quad_nochk(Register rr, int32_t imm64lo, int32_t imm64hi)
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Assembler::asm_quad_nochk(Register rr, int32_t imm64_0, int32_t imm64_1)
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{
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// We're not going to use a slot, because it might be too far
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// away. Instead, we're going to stick a branch in the stream to
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@ -744,14 +744,14 @@ Assembler::asm_quad_nochk(Register rr, int32_t imm64lo, int32_t imm64hi)
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// stream should look like:
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// branch A
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// imm64lo
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// imm64hi
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// imm64_0
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// imm64_1
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// A: FLDD PC-16
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FLDD(rr, PC, -16);
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*(--_nIns) = (NIns) imm64hi;
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*(--_nIns) = (NIns) imm64lo;
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*(--_nIns) = (NIns) imm64_1;
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*(--_nIns) = (NIns) imm64_0;
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JMP_nochk(_nIns+2);
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}
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@ -772,13 +772,13 @@ Assembler::asm_quad(LInsp ins)
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FSTD(rr, FP, d);
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underrunProtect(4*4);
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asm_quad_nochk(rr, ins->imm64lo(), ins->imm64hi());
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asm_quad_nochk(rr, ins->imm64_0(), ins->imm64_1());
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} else {
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NanoAssert(d);
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STR(IP, FP, d+4);
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asm_ld_imm(IP, ins->imm64hi());
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asm_ld_imm(IP, ins->imm64_1());
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STR(IP, FP, d);
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asm_ld_imm(IP, ins->imm64lo());
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asm_ld_imm(IP, ins->imm64_0());
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}
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}
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@ -407,9 +407,9 @@ namespace nanojit
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// generating a pointless store/load/store sequence
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Register rb = findRegFor(base, GpRegs);
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STW32(L0, dr+4, rb);
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SET32(value->imm64lo(), L0);
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SET32(value->imm64_0(), L0);
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STW32(L0, dr, rb);
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SET32(value->imm64hi(), L0);
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SET32(value->imm64_1(), L0);
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return;
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}
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@ -876,9 +876,9 @@ namespace nanojit
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Register r = registerAlloc(GpRegs);
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_allocator.addFree(r);
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STW32(r, d+4, FP);
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SET32(ins->imm64lo(), r);
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SET32(ins->imm64_0(), r);
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STW32(r, d, FP);
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SET32(ins->imm64hi(), r);
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SET32(ins->imm64_1(), r);
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}
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}
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@ -566,8 +566,8 @@ namespace nanojit
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} else {
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rb = findRegFor(base, GpRegs);
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}
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STi(rb, dr+4, value->imm64hi());
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STi(rb, dr, value->imm64lo());
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STi(rb, dr+4, value->imm64_1());
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STi(rb, dr, value->imm64_0());
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return;
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}
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@ -1172,8 +1172,8 @@ namespace nanojit
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freeRsrcOf(ins, false);
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if (d)
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{
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STi(FP,d+4,ins->imm64hi());
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STi(FP,d, ins->imm64lo());
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STi(FP,d+4,ins->imm64_1());
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STi(FP,d, ins->imm64_0());
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}
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}
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