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Mostly cosmetic arm merges, merge ARM fcmp(e)d changes (522403, r=graydon).

This commit is contained in:
Andreas Gal 2009-10-14 17:53:31 -07:00
Родитель 9d8168ff9d
Коммит f2c90007d3
2 изменённых файлов: 50 добавлений и 67 удалений
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45
js/src/nanojit/NativeARM.cpp
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@ -1437,7 +1437,7 @@ Assembler::underrunProtect(int bytes)
// _nSlot points to the first empty position in the new code block
// _nIns points just past the last empty position.
// Assume B_nochk won't ever try to write to _nSlot. See B_cond_chk macro.
B_nochk(target);
JMP_nochk(target);
}
}
@ -1859,11 +1859,13 @@ Assembler::asm_fcmp(LInsp ins)
NanoAssert(op >= LIR_feq && op <= LIR_fge);
int e_bit = (op != LIR_feq);
Register ra = findRegFor(lhs, FpRegs);
Register rb = findRegFor(rhs, FpRegs);
// do the comparison and get results loaded in ARM status register
FMSTAT();
FCMPD(ra, rb);
FCMPD(ra, rb, e_bit);
}
Register
@ -2024,11 +2026,11 @@ Assembler::asm_fcond(LInsp ins)
Register r = prepResultReg(ins, AllowableFlagRegs);
switch (ins->opcode()) {
case LIR_feq: SET(r,EQ); break;
case LIR_flt: SET(r,LO); break;
case LIR_fle: SET(r,LS); break;
case LIR_fge: SET(r,GE); break;
case LIR_fgt: SET(r,GT); break;
case LIR_feq: SETEQ(r); break;
case LIR_flt: SETLO(r); break; // } note: VFP LT/LE operations require use of
case LIR_fle: SETLS(r); break; // } unsigned LO/LS condition codes!
case LIR_fge: SETGE(r); break;
case LIR_fgt: SETGT(r); break;
default: NanoAssert(0); break;
}
@ -2041,17 +2043,17 @@ Assembler::asm_cond(LInsp ins)
Register r = prepResultReg(ins, AllowableFlagRegs);
switch(ins->opcode())
{
case LIR_eq: SET(r,EQ); break;
case LIR_ov: SET(r,VS); break;
case LIR_lt: SET(r,LT); break;
case LIR_le: SET(r,LE); break;
case LIR_gt: SET(r,GT); break;
case LIR_ge: SET(r,GE); break;
case LIR_ult: SET(r,LO); break;
case LIR_ule: SET(r,LS); break;
case LIR_ugt: SET(r,HI); break;
case LIR_uge: SET(r,HS); break;
default: NanoAssert(0); break;
case LIR_eq: SETEQ(r); break;
case LIR_ov: SETVS(r); break;
case LIR_lt: SETLT(r); break;
case LIR_le: SETLE(r); break;
case LIR_gt: SETGT(r); break;
case LIR_ge: SETGE(r); break;
case LIR_ult: SETLO(r); break;
case LIR_ule: SETLS(r); break;
case LIR_ugt: SETHI(r); break;
case LIR_uge: SETHS(r); break;
default: NanoAssert(0); break;
}
asm_cmp(ins);
}
@ -2282,10 +2284,10 @@ Assembler::asm_cmov(LInsp ins)
case LIR_le: MOVGT(rr, iffalsereg); break;
case LIR_gt: MOVLE(rr, iffalsereg); break;
case LIR_ge: MOVLT(rr, iffalsereg); break;
case LIR_ult: MOVCS(rr, iffalsereg); break;
case LIR_ult: MOVHS(rr, iffalsereg); break;
case LIR_ule: MOVHI(rr, iffalsereg); break;
case LIR_ugt: MOVLS(rr, iffalsereg); break;
case LIR_uge: MOVCC(rr, iffalsereg); break;
case LIR_uge: MOVLO(rr, iffalsereg); break;
default: debug_only( NanoAssert(0) ); break;
}
/*const Register iftruereg =*/ findSpecificRegFor(iftrue, rr);
@ -2318,7 +2320,7 @@ Assembler::asm_param(LInsp ins)
if (kind == 0) {
// ordinary param
AbiKind abi = _thisfrag->lirbuf->abi;
uint32_t abi_regcount = abi == ABI_FASTCALL ? 2 : abi == ABI_THISCALL ? 1 : 0;
uint32_t abi_regcount = abi == ABI_CDECL ? 4 : abi == ABI_FASTCALL ? 2 : abi == ABI_THISCALL ? 1 : 0;
if (a < abi_regcount) {
// incoming arg in register
prepResultReg(ins, rmask(argRegs[a]));
@ -2378,5 +2380,4 @@ Assembler::asm_promote(LIns *ins)
}
}
#endif /* FEATURE_NANOJIT */

72
js/src/nanojit/NativeARM.h
Просмотреть файл

@ -467,6 +467,7 @@ enum {
*(--_nIns) = (NIns)( COND_AL | (_d)<<16 | (_r)<<8 | 0x90 | (_l) ); \
asm_output("mul %s,%s,%s",gpn(_d),gpn(_l),gpn(_r)); } while(0)
// RSBS _d, _r
// _d = 0 - _r
#define RSBS(_d,_r) ALUi(AL, rsb, 1, _d, _r, 0)
@ -512,9 +513,9 @@ enum {
// CMP
#define CMP(_l,_r) ALUr(AL, cmp, 1, 0, _l, _r)
#define CMN(_l,_r) ALUr(AL, cmn, 1, 0, _l, _r)
// MOV
#define MOVis_chk(_d,_op2imm,_stat,_chk) ALUi_chk(AL, mov, _stat, _d, 0, op2imm, _chk)
#define MOVis(_d,_op2imm,_stat) MOVis_chk(_d,_op2imm,_stat,1)
#define MOVi(_d,_op2imm) MOVis(_d,_op2imm,0);
@ -540,6 +541,9 @@ enum {
#define LDR(_d,_b,_off) asm_ldr_chk(_d,_b,_off,1)
#define LDR_nochk(_d,_b,_off) asm_ldr_chk(_d,_b,_off,0)
// _d = #_imm
#define LDi(_d,_imm) asm_ld_imm(_d,_imm)
// MOVW and MOVT are ARMv6T2 or newer only
// MOVW -- writes _imm into _d, zero-extends.
@ -571,7 +575,8 @@ enum {
#define MOVTi_cond(_cond,_d,_imm) MOVTi_cond_chk(_cond, _d, _imm, 1)
// i386 compat, for Assembler.cpp
#define MR(d,s) MOV(d,s)
#define MR(d,s) MOV(d,s)
#define ST(base,offset,reg) STR(reg,base,offset)
// Load a byte (8 bits). The offset range is ±4095.
#define LDRB(_d,_n,_off) do { \
@ -625,11 +630,6 @@ enum {
*(--_nIns) = BKPTi_insn(id); \
} while (0)
// this isn't a armv6t2 NOP -- it's a mov r0,r0
#define NOP_nochk() do { \
*(--_nIns) = (NIns)( COND_AL | (0xD<<21) | ((R0)<<12) | (R0) ); \
asm_output("nop"); } while(0)
// STMFD SP!, {reg}
#define PUSHr(_r) do { \
underrunProtect(4); \
@ -682,41 +682,8 @@ enum {
#define BCC(t) B_cond(CC,t)
#define BCS(t) B_cond(CS,t)
// NB: don't use COND_AL here, we shift the condition into place!
#define JMP(_t) \
B_cond_chk(AL,_t,1)
#define JMP_nochk(_t) \
B_cond_chk(AL,_t,0)
#define JA(t) B_cond(HI,t)
#define JNA(t) B_cond(LS,t)
#define JB(t) B_cond(CC,t)
#define JNB(t) B_cond(CS,t)
#define JE(t) B_cond(EQ,t)
#define JNE(t) B_cond(NE,t)
#define JBE(t) B_cond(LS,t)
#define JNBE(t) B_cond(HI,t)
#define JAE(t) B_cond(CS,t)
#define JNAE(t) B_cond(CC,t)
#define JL(t) B_cond(LT,t)
#define JNL(t) B_cond(GE,t)
#define JLE(t) B_cond(LE,t)
#define JNLE(t) B_cond(GT,t)
#define JGE(t) B_cond(GE,t)
#define JNGE(t) B_cond(LT,t)
#define JG(t) B_cond(GT,t)
#define JNG(t) B_cond(LE,t)
#define JO(t) B_cond(VS,t)
#define JNO(t) B_cond(VC,t)
// used for testing result of an FP compare on x86; not used on arm.
// JP = comparison false
#define JP(t) do {NanoAssert(0); B_cond(NE,t); asm_output("jp 0x%08x",t); } while(0)
// JNP = comparison true
#define JNP(t) do {NanoAssert(0); B_cond(EQ,t); asm_output("jnp 0x%08x",t); } while(0)
#define JMP(t) B(t)
#define JMP_nochk(t) B_nochk(t)
// MOV(cond) _r, #1
// MOV(!cond) _r, #0
@ -729,6 +696,18 @@ enum {
asm_output("mov%s %s, #0", condNames[_opp], gpn(_r)); \
} while (0)
#define SETEQ(r) SET(r,EQ)
#define SETLT(r) SET(r,LT)
#define SETLE(r) SET(r,LE)
#define SETGT(r) SET(r,GT)
#define SETGE(r) SET(r,GE)
#define SETLO(r) SET(r,LO)
#define SETLS(r) SET(r,LS)
#define SETHI(r) SET(r,HI)
#define SETHS(r) SET(r,HS)
#define SETVS(r) SET(r,VS)
#define SETCS(r) SET(r,CS)
// Load and sign extend a 16-bit value into a reg
#define MOVSX(_d,_off,_b) do { \
if ((_off)>=0) { \
@ -768,6 +747,7 @@ enum {
#define STMIA(_b, _mask) do { \
underrunProtect(4); \
NanoAssert(IsGpReg(_b)); \
NanoAssert(((_mask)&rmask(_b))==0 && isU8(_mask)); \
*(--_nIns) = (NIns)(COND_AL | (0x8A<<20) | ((_b)<<16) | (_mask)&0xFF); \
asm_output("stmia %s!,{0x%x}", gpn(_b), _mask); \
@ -775,6 +755,7 @@ enum {
#define LDMIA(_b, _mask) do { \
underrunProtect(4); \
NanoAssert(IsGpReg(_b)); \
NanoAssert(((_mask)&rmask(_b))==0 && isU8(_mask)); \
*(--_nIns) = (NIns)(COND_AL | (0x8B<<20) | ((_b)<<16) | (_mask)&0xFF); \
asm_output("ldmia %s!,{0x%x}", gpn(_b), (_mask)); \
@ -919,12 +900,13 @@ enum {
asm_output("fmstat"); \
} while (0)
#define FCMPD(_Dd,_Dm) do { \
#define FCMPD(_Dd,_Dm,_E) do { \
underrunProtect(4); \
NanoAssert(ARM_VFP); \
NanoAssert(IsFpReg(_Dd) && IsFpReg(_Dm)); \
*(--_nIns) = (NIns)( COND_AL | (0xEB4<<16) | (FpRegNum(_Dd)<<12) | (0xB4<<4) | (FpRegNum(_Dm)) ); \
asm_output("fcmpd %s,%s", gpn(_Dd), gpn(_Dm)); \
NanoAssert(((_E)==0) || ((_E)==1)); \
*(--_nIns) = (NIns)( COND_AL | (0xEB4<<16) | (FpRegNum(_Dd)<<12) | (0xB<<8) | ((_E)<<7) | (0x4<<4) | (FpRegNum(_Dm)) ); \
asm_output("fcmp%sd %s,%s", (((_E)==1)?"e":""), gpn(_Dd), gpn(_Dm)); \
} while (0)
#define FCPYD(_Dd,_Dm) do { \