528 строки
15 KiB
ArmAsm
528 строки
15 KiB
ArmAsm
/*
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright (c) 2012, Intel Corporation
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;
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are
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; met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the
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; distribution.
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;
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; * Neither the name of the Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived from
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; this software without specific prior written permission.
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;
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;
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; THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION "AS IS" AND ANY
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; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; This code is described in an Intel White-Paper:
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; "Fast SHA-256 Implementations on Intel Architecture Processors"
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;
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; To find it, surf to http://www.intel.com/p/en_US/embedded
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; and search for that title.
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; The paper is expected to be released roughly at the end of April, 2012
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; This code schedules 2 blocks at a time, with 4 lanes per block
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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*/
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/*
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* Conversion to GAS assembly and integration to libgcrypt
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* by Jussi Kivilinna <jussi.kivilinna@iki.fi>
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*/
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#ifdef __x86_64
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#include <config.h>
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#if (defined(HAVE_COMPATIBLE_GCC_AMD64_PLATFORM_AS) || \
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defined(HAVE_COMPATIBLE_GCC_WIN64_PLATFORM_AS)) && \
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defined(HAVE_INTEL_SYNTAX_PLATFORM_AS) && \
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defined(HAVE_GCC_INLINE_ASM_AVX2) && defined(HAVE_GCC_INLINE_ASM_BMI2) && \
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defined(USE_SHA256)
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#include "asm-common-amd64.h"
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.intel_syntax noprefix
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#define VMOVDQ vmovdqu /* ; assume buffers not aligned */
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/* ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Define Macros */
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/* addm [mem], reg */
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/* Add reg to mem using reg-mem add and store */
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#define addm(p1, p2) \
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add p2, p1; \
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mov p1, p2;
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/* ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; */
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#define X0 ymm4
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#define X1 ymm5
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#define X2 ymm6
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#define X3 ymm7
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/* XMM versions of above */
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#define XWORD0 xmm4
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#define XWORD1 xmm5
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#define XWORD2 xmm6
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#define XWORD3 xmm7
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#define XTMP0 ymm0
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#define XTMP1 ymm1
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#define XTMP2 ymm2
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#define XTMP3 ymm3
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#define XTMP4 ymm8
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#define XFER ymm9
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#define XTMP5 ymm11
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#define SHUF_00BA ymm10 /* shuffle xBxA -> 00BA */
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#define SHUF_DC00 ymm12 /* shuffle xDxC -> DC00 */
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#define BYTE_FLIP_MASK ymm13
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#define X_BYTE_FLIP_MASK xmm13 /* XMM version of BYTE_FLIP_MASK */
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#define NUM_BLKS rdx /* 3rd arg */
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#define CTX rsi /* 2nd arg */
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#define INP rdi /* 1st arg */
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#define c ecx
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#define d r8d
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#define e edx /* clobbers NUM_BLKS */
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#define y3 edi /* clobbers INP */
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#define TBL rbp
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#define SRND CTX /* SRND is same register as CTX */
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#define a eax
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#define b ebx
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#define f r9d
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#define g r10d
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#define h r11d
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#define old_h r11d
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#define T1 r12d
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#define y0 r13d
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#define y1 r14d
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#define y2 r15d
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#define _XFER_SIZE 2*64*4 /* 2 blocks, 64 rounds, 4 bytes/round */
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#define _XMM_SAVE_SIZE 0
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#define _INP_END_SIZE 8
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#define _INP_SIZE 8
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#define _CTX_SIZE 8
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#define _RSP_SIZE 8
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#define _XFER 0
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#define _XMM_SAVE _XFER + _XFER_SIZE
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#define _INP_END _XMM_SAVE + _XMM_SAVE_SIZE
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#define _INP _INP_END + _INP_END_SIZE
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#define _CTX _INP + _INP_SIZE
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#define _RSP _CTX + _CTX_SIZE
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#define STACK_SIZE _RSP + _RSP_SIZE
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#define ONE_ROUND_PART1(XFERIN, a, b, c, d, e, f, g, h) \
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/* h += Sum1 (e) + Ch (e, f, g) + (k[t] + w[0]); */ \
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/* d += h; */ \
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/* h += Sum0 (a) + Maj (a, b, c); */ \
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\
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/* Ch(x, y, z) => ((x & y) + (~x & z)) */ \
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/* Maj(x, y, z) => ((x & y) + (z & (x ^ y))) */ \
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\
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mov y3, e; \
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add h, [XFERIN]; \
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and y3, f; \
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rorx y0, e, 25; \
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rorx y1, e, 11; \
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lea h, [h + y3]; \
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andn y3, e, g; \
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rorx T1, a, 13; \
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xor y0, y1; \
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lea h, [h + y3]
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#define ONE_ROUND_PART2(a, b, c, d, e, f, g, h) \
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rorx y2, a, 22; \
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rorx y1, e, 6; \
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mov y3, a; \
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xor T1, y2; \
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xor y0, y1; \
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xor y3, b; \
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lea h, [h + y0]; \
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mov y0, a; \
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rorx y2, a, 2; \
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add d, h; \
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and y3, c; \
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xor T1, y2; \
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lea h, [h + y3]; \
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lea h, [h + T1]; \
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and y0, b; \
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lea h, [h + y0]
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#define ONE_ROUND(XFER, a, b, c, d, e, f, g, h) \
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ONE_ROUND_PART1(XFER, a, b, c, d, e, f, g, h); \
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ONE_ROUND_PART2(a, b, c, d, e, f, g, h)
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#define FOUR_ROUNDS_AND_SCHED(XFERIN, XFEROUT, X0, X1, X2, X3, a, b, c, d, e, f, g, h) \
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/* ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; RND N + 0 ;;;;;;;;;;;;;;;;;;;;;;;;;;;; */; \
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vpalignr XTMP0, X3, X2, 4 /* XTMP0 = W[-7] */; \
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vpaddd XTMP0, XTMP0, X0 /* XTMP0 = W[-7] + W[-16]; y1 = (e >> 6); S1 */; \
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vpalignr XTMP1, X1, X0, 4 /* XTMP1 = W[-15] */; \
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vpsrld XTMP2, XTMP1, 7; \
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vpslld XTMP3, XTMP1, (32-7); \
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vpor XTMP3, XTMP3, XTMP2 /* XTMP3 = W[-15] ror 7 */; \
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vpsrld XTMP2, XTMP1,18; \
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\
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ONE_ROUND(0*4+XFERIN, a, b, c, d, e, f, g, h); \
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\
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/* ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; RND N + 1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;; */; \
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vpsrld XTMP4, XTMP1, 3 /* XTMP4 = W[-15] >> 3 */; \
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vpslld XTMP1, XTMP1, (32-18); \
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vpxor XTMP3, XTMP3, XTMP1; \
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vpxor XTMP3, XTMP3, XTMP2 /* XTMP3 = W[-15] ror 7 ^ W[-15] ror 18 */; \
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vpxor XTMP1, XTMP3, XTMP4 /* XTMP1 = s0 */; \
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vpshufd XTMP2, X3, 0b11111010 /* XTMP2 = W[-2] {BBAA} */; \
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vpaddd XTMP0, XTMP0, XTMP1 /* XTMP0 = W[-16] + W[-7] + s0 */; \
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vpsrld XTMP4, XTMP2, 10 /* XTMP4 = W[-2] >> 10 {BBAA} */; \
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\
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ONE_ROUND(1*4+XFERIN, h, a, b, c, d, e, f, g); \
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\
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/* ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; RND N + 2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;; */; \
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vpsrlq XTMP3, XTMP2, 19 /* XTMP3 = W[-2] ror 19 {xBxA} */; \
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vpsrlq XTMP2, XTMP2, 17 /* XTMP2 = W[-2] ror 17 {xBxA} */; \
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vpxor XTMP2, XTMP2, XTMP3; \
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vpxor XTMP4, XTMP4, XTMP2 /* XTMP4 = s1 {xBxA} */; \
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vpshufb XTMP4, XTMP4, SHUF_00BA /* XTMP4 = s1 {00BA} */; \
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vpaddd XTMP0, XTMP0, XTMP4 /* XTMP0 = {..., ..., W[1], W[0]} */; \
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vpshufd XTMP2, XTMP0, 0b1010000 /* XTMP2 = W[-2] {DDCC} */; \
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\
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ONE_ROUND(2*4+XFERIN, g, h, a, b, c, d, e, f); \
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\
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/* ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; RND N + 3 ;;;;;;;;;;;;;;;;;;;;;;;;;;;; */; \
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vpsrld XTMP5, XTMP2, 10 /* XTMP5 = W[-2] >> 10 {DDCC} */; \
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vpsrlq XTMP3, XTMP2, 19 /* XTMP3 = W[-2] ror 19 {xDxC} */; \
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vpsrlq XTMP2, XTMP2, 17 /* XTMP2 = W[-2] ror 17 {xDxC} */; \
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vpxor XTMP2, XTMP2, XTMP3; \
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vpxor XTMP5, XTMP5, XTMP2 /* XTMP5 = s1 {xDxC} */; \
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vpshufb XTMP5, XTMP5, SHUF_DC00 /* XTMP5 = s1 {DC00} */; \
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vpaddd X0, XTMP5, XTMP0 /* X0 = {W[3], W[2], W[1], W[0]} */; \
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vpaddd XFER, X0, [TBL + XFEROUT]; \
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\
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ONE_ROUND_PART1(3*4+XFERIN, f, g, h, a, b, c, d, e); \
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vmovdqa [rsp + _XFER + XFEROUT], XFER; \
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ONE_ROUND_PART2(f, g, h, a, b, c, d, e);
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#define DO_4ROUNDS(XFERIN, a, b, c, d, e, f, g, h) \
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ONE_ROUND(0*4+XFERIN, a, b, c, d, e, f, g, h); \
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ONE_ROUND(1*4+XFERIN, h, a, b, c, d, e, f, g); \
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ONE_ROUND(2*4+XFERIN, g, h, a, b, c, d, e, f); \
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ONE_ROUND(3*4+XFERIN, f, g, h, a, b, c, d, e)
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/*
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; void sha256_rorx(void *input_data, UINT32 digest[8], UINT64 num_blks)
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;; arg 1 : pointer to input data
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;; arg 2 : pointer to digest
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;; arg 3 : Num blocks
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*/
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.text
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.globl _gcry_sha256_transform_amd64_avx2
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ELF(.type _gcry_sha256_transform_amd64_avx2,@function)
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.align 32
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_gcry_sha256_transform_amd64_avx2:
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CFI_STARTPROC()
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xor eax, eax
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cmp rdx, 0
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je .Lnowork
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push rbx
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CFI_PUSH(rbx)
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push rbp
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CFI_PUSH(rbp)
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push r12
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CFI_PUSH(r12)
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push r13
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CFI_PUSH(r13)
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push r14
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CFI_PUSH(r14)
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push r15
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CFI_PUSH(r15)
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vzeroupper
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vmovdqa BYTE_FLIP_MASK, [.LPSHUFFLE_BYTE_FLIP_MASK ADD_RIP]
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vmovdqa SHUF_00BA, [.L_SHUF_00BA ADD_RIP]
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vmovdqa SHUF_DC00, [.L_SHUF_DC00 ADD_RIP]
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mov rax, rsp
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CFI_DEF_CFA_REGISTER(rax);
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sub rsp, STACK_SIZE
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and rsp, ~63
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mov [rsp + _RSP], rax
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CFI_CFA_ON_STACK(_RSP, 6 * 8)
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shl NUM_BLKS, 6 /* convert to bytes */
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lea NUM_BLKS, [NUM_BLKS + INP - 64] /* pointer to last block */
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mov [rsp + _INP_END], NUM_BLKS
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/* Check if only one block of input. Note: Loading initial digest
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* only uses 'mov' instruction and does not change condition
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* flags. */
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cmp NUM_BLKS, INP
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/* ; load initial digest */
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mov a,[4*0 + CTX]
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mov b,[4*1 + CTX]
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mov c,[4*2 + CTX]
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mov d,[4*3 + CTX]
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mov e,[4*4 + CTX]
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mov f,[4*5 + CTX]
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mov g,[4*6 + CTX]
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mov h,[4*7 + CTX]
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mov [rsp + _CTX], CTX
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je .Ldo_last_block
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.Loop0:
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lea TBL, [.LK256 ADD_RIP]
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/* ; Load first 16 dwords from two blocks */
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VMOVDQ XTMP0, [INP + 0*32]
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VMOVDQ XTMP1, [INP + 1*32]
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VMOVDQ XTMP2, [INP + 2*32]
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VMOVDQ XTMP3, [INP + 3*32]
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/* ; byte swap data */
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vpshufb XTMP0, XTMP0, BYTE_FLIP_MASK
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vpshufb XTMP1, XTMP1, BYTE_FLIP_MASK
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vpshufb XTMP2, XTMP2, BYTE_FLIP_MASK
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vpshufb XTMP3, XTMP3, BYTE_FLIP_MASK
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/* ; transpose data into high/low halves */
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vperm2i128 X0, XTMP0, XTMP2, 0x20
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vperm2i128 X1, XTMP0, XTMP2, 0x31
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vperm2i128 X2, XTMP1, XTMP3, 0x20
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vperm2i128 X3, XTMP1, XTMP3, 0x31
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.Last_block_enter:
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add INP, 64
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mov [rsp + _INP], INP
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/* ; schedule 48 input dwords, by doing 3 rounds of 12 each */
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xor SRND, SRND
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vpaddd XFER, X0, [TBL + 0*32]
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vmovdqa [rsp + _XFER + 0*32], XFER
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vpaddd XFER, X1, [TBL + 1*32]
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vmovdqa [rsp + _XFER + 1*32], XFER
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vpaddd XFER, X2, [TBL + 2*32]
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vmovdqa [rsp + _XFER + 2*32], XFER
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vpaddd XFER, X3, [TBL + 3*32]
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vmovdqa [rsp + _XFER + 3*32], XFER
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.align 16
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.Loop1:
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FOUR_ROUNDS_AND_SCHED(rsp + _XFER + SRND + 0*32, SRND + 4*32, X0, X1, X2, X3, a, b, c, d, e, f, g, h)
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FOUR_ROUNDS_AND_SCHED(rsp + _XFER + SRND + 1*32, SRND + 5*32, X1, X2, X3, X0, e, f, g, h, a, b, c, d)
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FOUR_ROUNDS_AND_SCHED(rsp + _XFER + SRND + 2*32, SRND + 6*32, X2, X3, X0, X1, a, b, c, d, e, f, g, h)
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FOUR_ROUNDS_AND_SCHED(rsp + _XFER + SRND + 3*32, SRND + 7*32, X3, X0, X1, X2, e, f, g, h, a, b, c, d)
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add SRND, 4*32
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cmp SRND, 3 * 4*32
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jb .Loop1
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/* ; Do last 16 rounds with no scheduling */
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DO_4ROUNDS(rsp + _XFER + (3*4*32 + 0*32), a, b, c, d, e, f, g, h)
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DO_4ROUNDS(rsp + _XFER + (3*4*32 + 1*32), e, f, g, h, a, b, c, d)
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DO_4ROUNDS(rsp + _XFER + (3*4*32 + 2*32), a, b, c, d, e, f, g, h)
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DO_4ROUNDS(rsp + _XFER + (3*4*32 + 3*32), e, f, g, h, a, b, c, d)
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mov CTX, [rsp + _CTX]
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mov INP, [rsp + _INP]
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addm([4*0 + CTX],a)
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addm([4*1 + CTX],b)
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addm([4*2 + CTX],c)
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addm([4*3 + CTX],d)
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addm([4*4 + CTX],e)
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addm([4*5 + CTX],f)
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addm([4*6 + CTX],g)
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addm([4*7 + CTX],h)
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cmp INP, [rsp + _INP_END]
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ja .Ldone_hash
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/* ;;; Do second block using previously scheduled results */
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xor SRND, SRND
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.align 16
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.Loop3:
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DO_4ROUNDS(rsp + _XFER + SRND + 0*32 + 16, a, b, c, d, e, f, g, h)
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DO_4ROUNDS(rsp + _XFER + SRND + 1*32 + 16, e, f, g, h, a, b, c, d)
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add SRND, 2*32
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cmp SRND, 4 * 4*32
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jb .Loop3
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mov CTX, [rsp + _CTX]
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mov INP, [rsp + _INP]
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add INP, 64
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addm([4*0 + CTX],a)
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addm([4*1 + CTX],b)
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addm([4*2 + CTX],c)
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addm([4*3 + CTX],d)
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addm([4*4 + CTX],e)
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addm([4*5 + CTX],f)
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addm([4*6 + CTX],g)
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addm([4*7 + CTX],h)
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cmp INP, [rsp + _INP_END]
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jb .Loop0
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ja .Ldone_hash
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|
|
.Ldo_last_block:
|
|
/* ;;; do last block */
|
|
lea TBL, [.LK256 ADD_RIP]
|
|
|
|
VMOVDQ XWORD0, [INP + 0*16]
|
|
VMOVDQ XWORD1, [INP + 1*16]
|
|
VMOVDQ XWORD2, [INP + 2*16]
|
|
VMOVDQ XWORD3, [INP + 3*16]
|
|
|
|
vpshufb XWORD0, XWORD0, X_BYTE_FLIP_MASK
|
|
vpshufb XWORD1, XWORD1, X_BYTE_FLIP_MASK
|
|
vpshufb XWORD2, XWORD2, X_BYTE_FLIP_MASK
|
|
vpshufb XWORD3, XWORD3, X_BYTE_FLIP_MASK
|
|
|
|
jmp .Last_block_enter
|
|
|
|
.Lonly_one_block:
|
|
|
|
/* ; load initial digest */
|
|
mov a,[4*0 + CTX]
|
|
mov b,[4*1 + CTX]
|
|
mov c,[4*2 + CTX]
|
|
mov d,[4*3 + CTX]
|
|
mov e,[4*4 + CTX]
|
|
mov f,[4*5 + CTX]
|
|
mov g,[4*6 + CTX]
|
|
mov h,[4*7 + CTX]
|
|
|
|
vmovdqa BYTE_FLIP_MASK, [.LPSHUFFLE_BYTE_FLIP_MASK ADD_RIP]
|
|
vmovdqa SHUF_00BA, [.L_SHUF_00BA ADD_RIP]
|
|
vmovdqa SHUF_DC00, [.L_SHUF_DC00 ADD_RIP]
|
|
|
|
mov [rsp + _CTX], CTX
|
|
jmp .Ldo_last_block
|
|
|
|
.Ldone_hash:
|
|
vzeroall
|
|
|
|
/* burn stack */
|
|
vmovdqa [rsp + _XFER + 0 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 1 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 2 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 3 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 4 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 5 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 6 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 7 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 8 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 9 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 10 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 11 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 12 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 13 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 14 * 32], ymm0
|
|
vmovdqa [rsp + _XFER + 15 * 32], ymm0
|
|
xor eax, eax
|
|
|
|
mov rsp, [rsp + _RSP]
|
|
CFI_DEF_CFA_REGISTER(rsp)
|
|
|
|
pop r15
|
|
CFI_POP(r15)
|
|
pop r14
|
|
CFI_POP(r14)
|
|
pop r13
|
|
CFI_POP(r13)
|
|
pop r12
|
|
CFI_POP(r12)
|
|
pop rbp
|
|
CFI_POP(rbp)
|
|
pop rbx
|
|
CFI_POP(rbx)
|
|
|
|
.Lnowork:
|
|
ret
|
|
CFI_ENDPROC()
|
|
|
|
.align 64
|
|
.LK256:
|
|
.long 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
|
|
.long 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
|
|
.long 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
|
|
.long 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
|
|
.long 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
|
|
.long 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
|
|
.long 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
|
|
.long 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
|
|
.long 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
|
|
.long 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
|
|
.long 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
|
|
.long 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
|
|
.long 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
|
|
.long 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
|
|
.long 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
|
|
.long 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
|
|
.long 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
|
|
.long 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
|
|
.long 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
|
|
.long 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
|
|
.long 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
|
|
.long 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
|
|
.long 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
|
|
.long 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
|
|
.long 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
|
|
.long 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
|
|
.long 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
|
|
.long 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
|
|
.long 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
|
|
.long 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
|
|
.long 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
|
|
.long 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
|
|
|
|
.LPSHUFFLE_BYTE_FLIP_MASK:
|
|
.octa 0x0c0d0e0f08090a0b0405060700010203,0x0c0d0e0f08090a0b0405060700010203
|
|
|
|
/* shuffle xBxA -> 00BA */
|
|
.L_SHUF_00BA:
|
|
.octa 0xFFFFFFFFFFFFFFFF0b0a090803020100,0xFFFFFFFFFFFFFFFF0b0a090803020100
|
|
|
|
/* shuffle xDxC -> DC00 */
|
|
.L_SHUF_DC00:
|
|
.octa 0x0b0a090803020100FFFFFFFFFFFFFFFF,0x0b0a090803020100FFFFFFFFFFFFFFFF
|
|
|
|
#endif
|
|
#endif
|