468 строки
16 KiB
ArmAsm
468 строки
16 KiB
ArmAsm
/*
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright (c) 2012, Intel Corporation
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;
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are
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; met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the
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; distribution.
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;
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; * Neither the name of the Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived from
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; this software without specific prior written permission.
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;
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;
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; THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION "AS IS" AND ANY
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; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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*/
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/*
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* Conversion to GAS assembly and integration to libgcrypt
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* by Jussi Kivilinna <jussi.kivilinna@iki.fi>
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*
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* Note: original implementation was named as SHA512-SSE4. However, only SSSE3
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* is required.
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*/
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#ifdef __x86_64
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#include <config.h>
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#if (defined(HAVE_COMPATIBLE_GCC_AMD64_PLATFORM_AS) || \
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defined(HAVE_COMPATIBLE_GCC_WIN64_PLATFORM_AS)) && \
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defined(HAVE_INTEL_SYNTAX_PLATFORM_AS) && \
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defined(HAVE_GCC_INLINE_ASM_SSSE3) && defined(USE_SHA512)
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#include "asm-common-amd64.h"
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.intel_syntax noprefix
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.text
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/* Virtual Registers */
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#define msg rdi /* ARG1 */
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#define digest rsi /* ARG2 */
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#define msglen rdx /* ARG3 */
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#define T1 rcx
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#define T2 r8
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#define a_64 r9
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#define b_64 r10
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#define c_64 r11
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#define d_64 r12
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#define e_64 r13
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#define f_64 r14
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#define g_64 r15
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#define h_64 rbx
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#define tmp0 rax
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/*
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; Local variables (stack frame)
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; Note: frame_size must be an odd multiple of 8 bytes to XMM align RSP
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*/
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#define frame_W 0 /* Message Schedule */
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#define frame_W_size (80 * 8)
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#define frame_WK ((frame_W) + (frame_W_size)) /* W[t] + K[t] | W[t+1] + K[t+1] */
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#define frame_WK_size (2 * 8)
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#define frame_GPRSAVE ((frame_WK) + (frame_WK_size))
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#define frame_GPRSAVE_size (5 * 8)
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#define frame_size ((frame_GPRSAVE) + (frame_GPRSAVE_size))
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/* Useful QWORD "arrays" for simpler memory references */
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#define MSG(i) msg + 8*(i) /* Input message (arg1) */
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#define DIGEST(i) digest + 8*(i) /* Output Digest (arg2) */
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#define K_t(i) .LK512 + 8*(i) ADD_RIP /* SHA Constants (static mem) */
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#define W_t(i) rsp + frame_W + 8*(i) /* Message Schedule (stack frame) */
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#define WK_2(i) rsp + frame_WK + 8*((i) % 2) /* W[t]+K[t] (stack frame) */
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/* MSG, DIGEST, K_t, W_t are arrays */
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/* WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even */
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#define SHA512_Round(t, a, b, c, d, e, f, g, h) \
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/* Compute Round %%t */; \
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mov T1, f /* T1 = f */; \
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mov tmp0, e /* tmp = e */; \
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xor T1, g /* T1 = f ^ g */; \
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ror tmp0, 23 /* 41 ; tmp = e ror 23 */; \
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and T1, e /* T1 = (f ^ g) & e */; \
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xor tmp0, e /* tmp = (e ror 23) ^ e */; \
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xor T1, g /* T1 = ((f ^ g) & e) ^ g = CH(e,f,g) */; \
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add T1, [WK_2(t)] /* W[t] + K[t] from message scheduler */; \
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ror tmp0, 4 /* 18 ; tmp = ((e ror 23) ^ e) ror 4 */; \
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xor tmp0, e /* tmp = (((e ror 23) ^ e) ror 4) ^ e */; \
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mov T2, a /* T2 = a */; \
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add T1, h /* T1 = CH(e,f,g) + W[t] + K[t] + h */; \
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ror tmp0, 14 /* 14 ; tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e) */; \
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add T1, tmp0 /* T1 = CH(e,f,g) + W[t] + K[t] + S1(e) */; \
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mov tmp0, a /* tmp = a */; \
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xor T2, c /* T2 = a ^ c */; \
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and tmp0, c /* tmp = a & c */; \
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and T2, b /* T2 = (a ^ c) & b */; \
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xor T2, tmp0 /* T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c) */; \
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mov tmp0, a /* tmp = a */; \
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ror tmp0, 5 /* 39 ; tmp = a ror 5 */; \
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xor tmp0, a /* tmp = (a ror 5) ^ a */; \
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add d, T1 /* e(next_state) = d + T1 */; \
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ror tmp0, 6 /* 34 ; tmp = ((a ror 5) ^ a) ror 6 */; \
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xor tmp0, a /* tmp = (((a ror 5) ^ a) ror 6) ^ a */; \
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lea h, [T1 + T2] /* a(next_state) = T1 + Maj(a,b,c) */; \
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ror tmp0, 28 /* 28 ; tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a) */; \
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add h, tmp0 /* a(next_state) = T1 + Maj(a,b,c) S0(a) */
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#define SHA512_2Sched_2Round_sse_PART1(t, a, b, c, d, e, f, g, h) \
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/* \
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; Compute rounds %%t-2 and %%t-1 \
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; Compute message schedule QWORDS %%t and %%t+1 \
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; \
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; Two rounds are computed based on the values for K[t-2]+W[t-2] and \
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; K[t-1]+W[t-1] which were previously stored at WK_2 by the message \
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; scheduler. \
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; The two new schedule QWORDS are stored at [W_t(%%t)] and [W_t(%%t+1)]. \
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; They are then added to their respective SHA512 constants at \
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; [K_t(%%t)] and [K_t(%%t+1)] and stored at dqword [WK_2(%%t)] \
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; For brievity, the comments following vectored instructions only refer to \
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; the first of a pair of QWORDS. \
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; Eg. XMM2=W[t-2] really means XMM2={W[t-2]|W[t-1]} \
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; The computation of the message schedule and the rounds are tightly \
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; stitched to take advantage of instruction-level parallelism. \
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; For clarity, integer instructions (for the rounds calculation) are indented \
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; by one tab. Vectored instructions (for the message scheduler) are indented \
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; by two tabs. \
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*/ \
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\
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mov T1, f; \
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movdqa xmm2, [W_t(t-2)] /* XMM2 = W[t-2] */; \
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xor T1, g; \
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and T1, e; \
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movdqa xmm0, xmm2 /* XMM0 = W[t-2] */; \
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xor T1, g; \
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add T1, [WK_2(t)]; \
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movdqu xmm5, [W_t(t-15)] /* XMM5 = W[t-15] */; \
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mov tmp0, e; \
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ror tmp0, 23 /* 41 */; \
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movdqa xmm3, xmm5 /* XMM3 = W[t-15] */; \
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xor tmp0, e; \
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ror tmp0, 4 /* 18 */; \
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psrlq xmm0, 61 - 19 /* XMM0 = W[t-2] >> 42 */; \
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xor tmp0, e; \
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ror tmp0, 14 /* 14 */; \
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psrlq xmm3, (8 - 7) /* XMM3 = W[t-15] >> 1 */; \
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add T1, tmp0; \
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add T1, h; \
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pxor xmm0, xmm2 /* XMM0 = (W[t-2] >> 42) ^ W[t-2] */; \
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mov T2, a; \
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xor T2, c; \
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pxor xmm3, xmm5 /* XMM3 = (W[t-15] >> 1) ^ W[t-15] */; \
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and T2, b; \
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mov tmp0, a; \
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psrlq xmm0, 19 - 6 /* XMM0 = ((W[t-2]>>42)^W[t-2])>>13 */; \
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and tmp0, c; \
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xor T2, tmp0; \
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psrlq xmm3, (7 - 1) /* XMM3 = ((W[t-15]>>1)^W[t-15])>>6 */; \
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mov tmp0, a; \
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ror tmp0, 5 /* 39 */; \
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pxor xmm0, xmm2 /* XMM0 = (((W[t-2]>>42)^W[t-2])>>13)^W[t-2] */; \
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xor tmp0, a; \
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ror tmp0, 6 /* 34 */; \
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pxor xmm3, xmm5 /* XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15] */; \
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xor tmp0, a; \
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ror tmp0, 28 /* 28 */; \
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psrlq xmm0, 6 /* XMM0 = ((((W[t-2]>>42)^W[t-2])>>13)^W[t-2])>>6 */; \
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add T2, tmp0; \
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add d, T1; \
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psrlq xmm3, 1 /* XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15]>>1 */; \
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lea h, [T1 + T2]
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#define SHA512_2Sched_2Round_sse_PART2(t, a, b, c, d, e, f, g, h) \
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movdqa xmm1, xmm2 /* XMM1 = W[t-2] */; \
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mov T1, f; \
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xor T1, g; \
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movdqa xmm4, xmm5 /* XMM4 = W[t-15] */; \
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and T1, e; \
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xor T1, g; \
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psllq xmm1, (64 - 19) - (64 - 61) /* XMM1 = W[t-2] << 42 */; \
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add T1, [WK_2(t+1)]; \
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mov tmp0, e; \
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psllq xmm4, (64 - 1) - (64 - 8) /* XMM4 = W[t-15] << 7 */; \
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ror tmp0, 23 /* 41 */; \
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xor tmp0, e; \
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pxor xmm1, xmm2 /* XMM1 = (W[t-2] << 42)^W[t-2] */; \
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ror tmp0, 4 /* 18 */; \
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xor tmp0, e; \
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pxor xmm4, xmm5 /* XMM4 = (W[t-15]<<7)^W[t-15] */; \
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ror tmp0, 14 /* 14 */; \
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add T1, tmp0; \
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psllq xmm1, (64 - 61) /* XMM1 = ((W[t-2] << 42)^W[t-2])<<3 */; \
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add T1, h; \
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mov T2, a; \
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psllq xmm4, (64 - 8) /* XMM4 = ((W[t-15]<<7)^W[t-15])<<56 */; \
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xor T2, c; \
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and T2, b; \
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pxor xmm0, xmm1 /* XMM0 = s1(W[t-2]) */; \
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mov tmp0, a; \
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and tmp0, c; \
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movdqu xmm1, [W_t(t- 7)] /* XMM1 = W[t-7] */; \
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xor T2, tmp0; \
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pxor xmm3, xmm4 /* XMM3 = s0(W[t-15]) */; \
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mov tmp0, a; \
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paddq xmm0, xmm3 /* XMM0 = s1(W[t-2]) + s0(W[t-15]) */; \
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ror tmp0, 5 /* 39 */; \
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paddq xmm0, [W_t(t-16)] /* XMM0 = s1(W[t-2]) + s0(W[t-15]) + W[t-16] */; \
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xor tmp0, a; \
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paddq xmm0, xmm1 /* XMM0 = s1(W[t-2]) + W[t-7] + s0(W[t-15]) + W[t-16] */; \
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ror tmp0, 6 /* 34 */; \
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movdqa [W_t(t)], xmm0 /* Store scheduled qwords */; \
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xor tmp0, a; \
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paddq xmm0, [K_t(t)] /* Compute W[t]+K[t] */; \
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ror tmp0, 28 /* 28 */; \
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movdqa [WK_2(t)], xmm0 /* Store W[t]+K[t] for next rounds */; \
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add T2, tmp0; \
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add d, T1; \
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lea h, [T1 + T2]
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#define SHA512_2Sched_2Round_sse(t, a, b, c, d, e, f, g, h) \
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SHA512_2Sched_2Round_sse_PART1(t, a, b, c, d, e, f, g, h); \
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SHA512_2Sched_2Round_sse_PART2(t, h, a, b, c, d, e, f, g)
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/*
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; void sha512_sse4(const void* M, void* D, uint64_t L);
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; Purpose: Updates the SHA512 digest stored at D with the message stored in M.
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; The size of the message pointed to by M must be an integer multiple of SHA512
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; message blocks.
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; L is the message length in SHA512 blocks.
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*/
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.globl _gcry_sha512_transform_amd64_ssse3
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ELF(.type _gcry_sha512_transform_amd64_ssse3,@function;)
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.align 16
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_gcry_sha512_transform_amd64_ssse3:
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CFI_STARTPROC()
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xor eax, eax
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cmp msglen, 0
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je .Lnowork
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/* Allocate Stack Space */
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sub rsp, frame_size
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CFI_ADJUST_CFA_OFFSET(frame_size);
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/* Save GPRs */
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mov [rsp + frame_GPRSAVE + 8 * 0], rbx
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mov [rsp + frame_GPRSAVE + 8 * 1], r12
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mov [rsp + frame_GPRSAVE + 8 * 2], r13
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mov [rsp + frame_GPRSAVE + 8 * 3], r14
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mov [rsp + frame_GPRSAVE + 8 * 4], r15
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CFI_REL_OFFSET(rbx, frame_GPRSAVE + 8 * 0);
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CFI_REL_OFFSET(r12, frame_GPRSAVE + 8 * 1);
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CFI_REL_OFFSET(r13, frame_GPRSAVE + 8 * 2);
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CFI_REL_OFFSET(r14, frame_GPRSAVE + 8 * 3);
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CFI_REL_OFFSET(r15, frame_GPRSAVE + 8 * 4);
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.Lupdateblock:
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/* Load state variables */
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mov a_64, [DIGEST(0)]
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mov b_64, [DIGEST(1)]
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mov c_64, [DIGEST(2)]
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mov d_64, [DIGEST(3)]
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mov e_64, [DIGEST(4)]
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mov f_64, [DIGEST(5)]
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mov g_64, [DIGEST(6)]
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mov h_64, [DIGEST(7)]
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/* BSWAP 2 QWORDS */
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movdqa xmm1, [.LXMM_QWORD_BSWAP ADD_RIP]
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movdqu xmm0, [MSG(0)]
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pshufb xmm0, xmm1 /* BSWAP */
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movdqa [W_t(0)], xmm0 /* Store Scheduled Pair */
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paddq xmm0, [K_t(0)] /* Compute W[t]+K[t] */
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movdqa [WK_2(0)], xmm0 /* Store into WK for rounds */
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#define T_2_14(t, a, b, c, d, e, f, g, h) \
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/* BSWAP 2 QWORDS; Compute 2 Rounds */; \
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movdqu xmm0, [MSG(t)]; \
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pshufb xmm0, xmm1 /* BSWAP */; \
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SHA512_Round(((t) - 2), a##_64, b##_64, c##_64, d##_64, \
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e##_64, f##_64, g##_64, h##_64); \
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movdqa [W_t(t)], xmm0 /* Store Scheduled Pair */; \
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paddq xmm0, [K_t(t)] /* Compute W[t]+K[t] */; \
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SHA512_Round(((t) - 1), h##_64, a##_64, b##_64, c##_64, \
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d##_64, e##_64, f##_64, g##_64); \
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movdqa [WK_2(t)], xmm0 /* Store W[t]+K[t] into WK */
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#define T_16_78(t, a, b, c, d, e, f, g, h) \
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SHA512_2Sched_2Round_sse((t), a##_64, b##_64, c##_64, d##_64, \
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e##_64, f##_64, g##_64, h##_64)
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#define T_80(t, a, b, c, d, e, f, g, h) \
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/* Compute 2 Rounds */; \
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SHA512_Round((t - 2), a##_64, b##_64, c##_64, d##_64, \
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e##_64, f##_64, g##_64, h##_64); \
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SHA512_Round((t - 1), h##_64, a##_64, b##_64, c##_64, \
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d##_64, e##_64, f##_64, g##_64)
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T_2_14(2, a, b, c, d, e, f, g, h)
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T_2_14(4, g, h, a, b, c, d, e, f)
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T_2_14(6, e, f, g, h, a, b, c, d)
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T_2_14(8, c, d, e, f, g, h, a, b)
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T_2_14(10, a, b, c, d, e, f, g, h)
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T_2_14(12, g, h, a, b, c, d, e, f)
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T_2_14(14, e, f, g, h, a, b, c, d)
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T_16_78(16, c, d, e, f, g, h, a, b)
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T_16_78(18, a, b, c, d, e, f, g, h)
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T_16_78(20, g, h, a, b, c, d, e, f)
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T_16_78(22, e, f, g, h, a, b, c, d)
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T_16_78(24, c, d, e, f, g, h, a, b)
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T_16_78(26, a, b, c, d, e, f, g, h)
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T_16_78(28, g, h, a, b, c, d, e, f)
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T_16_78(30, e, f, g, h, a, b, c, d)
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T_16_78(32, c, d, e, f, g, h, a, b)
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T_16_78(34, a, b, c, d, e, f, g, h)
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T_16_78(36, g, h, a, b, c, d, e, f)
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T_16_78(38, e, f, g, h, a, b, c, d)
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T_16_78(40, c, d, e, f, g, h, a, b)
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T_16_78(42, a, b, c, d, e, f, g, h)
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T_16_78(44, g, h, a, b, c, d, e, f)
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T_16_78(46, e, f, g, h, a, b, c, d)
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T_16_78(48, c, d, e, f, g, h, a, b)
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T_16_78(50, a, b, c, d, e, f, g, h)
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T_16_78(52, g, h, a, b, c, d, e, f)
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T_16_78(54, e, f, g, h, a, b, c, d)
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T_16_78(56, c, d, e, f, g, h, a, b)
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T_16_78(58, a, b, c, d, e, f, g, h)
|
|
T_16_78(60, g, h, a, b, c, d, e, f)
|
|
T_16_78(62, e, f, g, h, a, b, c, d)
|
|
T_16_78(64, c, d, e, f, g, h, a, b)
|
|
T_16_78(66, a, b, c, d, e, f, g, h)
|
|
T_16_78(68, g, h, a, b, c, d, e, f)
|
|
T_16_78(70, e, f, g, h, a, b, c, d)
|
|
T_16_78(72, c, d, e, f, g, h, a, b)
|
|
T_16_78(74, a, b, c, d, e, f, g, h)
|
|
T_16_78(76, g, h, a, b, c, d, e, f)
|
|
T_16_78(78, e, f, g, h, a, b, c, d)
|
|
T_80(80, c, d, e, f, g, h, a, b)
|
|
|
|
/* Update digest */
|
|
add [DIGEST(0)], a_64
|
|
add [DIGEST(1)], b_64
|
|
add [DIGEST(2)], c_64
|
|
add [DIGEST(3)], d_64
|
|
add [DIGEST(4)], e_64
|
|
add [DIGEST(5)], f_64
|
|
add [DIGEST(6)], g_64
|
|
add [DIGEST(7)], h_64
|
|
|
|
/* Advance to next message block */
|
|
add msg, 16*8
|
|
dec msglen
|
|
jnz .Lupdateblock
|
|
|
|
/* Restore GPRs */
|
|
mov rbx, [rsp + frame_GPRSAVE + 8 * 0]
|
|
mov r12, [rsp + frame_GPRSAVE + 8 * 1]
|
|
mov r13, [rsp + frame_GPRSAVE + 8 * 2]
|
|
mov r14, [rsp + frame_GPRSAVE + 8 * 3]
|
|
mov r15, [rsp + frame_GPRSAVE + 8 * 4]
|
|
CFI_RESTORE(rbx)
|
|
CFI_RESTORE(r12)
|
|
CFI_RESTORE(r13)
|
|
CFI_RESTORE(r14)
|
|
CFI_RESTORE(r15)
|
|
|
|
pxor xmm0, xmm0
|
|
pxor xmm1, xmm1
|
|
pxor xmm2, xmm2
|
|
pxor xmm3, xmm3
|
|
pxor xmm4, xmm4
|
|
pxor xmm5, xmm5
|
|
|
|
/* Burn stack */
|
|
mov eax, 0
|
|
.Lerase_stack:
|
|
movdqu [rsp + rax], xmm0
|
|
add eax, 16
|
|
cmp eax, frame_W_size
|
|
jne .Lerase_stack
|
|
movdqu [rsp + frame_WK], xmm0
|
|
xor eax, eax
|
|
|
|
/* Restore Stack Pointer */
|
|
add rsp, frame_size
|
|
CFI_ADJUST_CFA_OFFSET(-frame_size);
|
|
|
|
.Lnowork:
|
|
ret
|
|
CFI_ENDPROC()
|
|
|
|
/*
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;;; Binary Data
|
|
*/
|
|
|
|
.align 16
|
|
|
|
/* Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb. */
|
|
.LXMM_QWORD_BSWAP:
|
|
.octa 0x08090a0b0c0d0e0f0001020304050607
|
|
|
|
/* K[t] used in SHA512 hashing */
|
|
.LK512:
|
|
.quad 0x428a2f98d728ae22,0x7137449123ef65cd
|
|
.quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
|
|
.quad 0x3956c25bf348b538,0x59f111f1b605d019
|
|
.quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
|
|
.quad 0xd807aa98a3030242,0x12835b0145706fbe
|
|
.quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
|
|
.quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
|
|
.quad 0x9bdc06a725c71235,0xc19bf174cf692694
|
|
.quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
|
|
.quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
|
|
.quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
|
|
.quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
|
|
.quad 0x983e5152ee66dfab,0xa831c66d2db43210
|
|
.quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
|
|
.quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
|
|
.quad 0x06ca6351e003826f,0x142929670a0e6e70
|
|
.quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
|
|
.quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
|
|
.quad 0x650a73548baf63de,0x766a0abb3c77b2a8
|
|
.quad 0x81c2c92e47edaee6,0x92722c851482353b
|
|
.quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
|
|
.quad 0xc24b8b70d0f89791,0xc76c51a30654be30
|
|
.quad 0xd192e819d6ef5218,0xd69906245565a910
|
|
.quad 0xf40e35855771202a,0x106aa07032bbd1b8
|
|
.quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
|
|
.quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
|
|
.quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
|
|
.quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
|
|
.quad 0x748f82ee5defb2fc,0x78a5636f43172f60
|
|
.quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
|
|
.quad 0x90befffa23631e28,0xa4506cebde82bde9
|
|
.quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
|
|
.quad 0xca273eceea26619c,0xd186b8c721c0c207
|
|
.quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
|
|
.quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
|
|
.quad 0x113f9804bef90dae,0x1b710b35131c471b
|
|
.quad 0x28db77f523047d84,0x32caab7b40c72493
|
|
.quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
|
|
.quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
|
|
.quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817
|
|
|
|
#endif
|
|
#endif
|