Moved SDRAM defines out of example
This commit is contained in:
Fabien Poussin
Родитель
90f32c3546
Коммит
13ebce61e2
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@ -41,6 +41,85 @@
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/* Driver constants. */
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/*
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* FMC SDRAM Mode definition register defines
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*/
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#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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/*
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* FMC_ReadPipe_Delay
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*/
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#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
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#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
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#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
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#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
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/*
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* FMC_Read_Burst
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*/
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#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
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#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
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#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
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/*
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* FMC_SDClock_Period
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*/
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#define FMC_SDClock_Disable ((uint32_t)0x00000000)
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#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
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#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
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#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
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/*
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* FMC_ColumnBits_Number
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*/
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#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
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#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
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#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
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#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
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/*
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* FMC_RowBits_Number
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*/
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#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
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#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
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#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
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/*
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* FMC_SDMemory_Data_Width
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*/
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#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
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#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
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#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
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/*
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* FMC_InternalBank_Number
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*/
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#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
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#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
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/*
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* FMC_CAS_Latency
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*/
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#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
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#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
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#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
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/*
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* FMC_Write_Protection
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*/
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#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
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#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -56,7 +135,7 @@
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#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__)
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#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__)
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#define STM32_FSMC_USE_SDRAM1 FALSE
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#define STM32_FSMC_USE_SDRAM1 FALSE
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#else
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#else
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#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE
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#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE
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#endif
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#endif
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/**
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/**
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@ -66,7 +145,7 @@
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#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__)
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#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__)
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#define STM32_FSMC_USE_SDRAM2 FALSE
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#define STM32_FSMC_USE_SDRAM2 FALSE
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#else
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#else
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#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE
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#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE
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#endif
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#endif
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/** @} */
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/** @} */
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@ -32,84 +32,6 @@
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******************************************************************************
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******************************************************************************
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*/
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*/
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/*
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* FMC SDRAM Mode definition register defines
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*/
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#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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/*
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* FMC_ReadPipe_Delay
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*/
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#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
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#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
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#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
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#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
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/*
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* FMC_Read_Burst
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*/
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#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
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#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
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#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
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/*
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* FMC_SDClock_Period
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*/
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#define FMC_SDClock_Disable ((uint32_t)0x00000000)
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#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
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#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
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#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
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/*
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* FMC_ColumnBits_Number
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*/
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#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
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#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
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#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
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#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
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/*
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* FMC_RowBits_Number
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*/
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#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
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#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
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#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
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/*
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* FMC_SDMemory_Data_Width
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*/
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#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
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#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
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#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
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/*
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* FMC_InternalBank_Number
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*/
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#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
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#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
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/*
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* FMC_CAS_Latency
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*/
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#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
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#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
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#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
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/*
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* FMC_Write_Protection
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*/
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#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
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#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
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#define SDRAM_SIZE (8 * 1024 * 1024)
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#define SDRAM_SIZE (8 * 1024 * 1024)
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#define SDRAM_START ((void *)FSMC_Bank6_MAP_BASE)
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#define SDRAM_START ((void *)FSMC_Bank6_MAP_BASE)
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