Merge branch 'master' of https://github.com/ChibiOS/ChibiOS-Contrib

os/hal/include/hal_eeprom.h

@@ -68,7 +68,7 @@
   uint16_t        pagesize;                                                 \
   /* Time needed by IC for single byte/page writing. */                     \
   systime_t       write_time;
-  
+
 typedef uint32_t fileoffset_t;
 
 typedef struct {

os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.c

@@ -34,6 +34,14 @@
 /* Driver local definitions.                                                 */
 /*===========================================================================*/
 
+#ifndef COMP_CSR_EN
+#define COMP_CSR_EN COMP_CSR_COMPxEN
+#endif
+
+#ifndef COMP_CSR_POLARITY
+#define COMP_CSR_POLARITY COMP_CSR_COMPxPOL
+#endif
+
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
@@ -122,7 +130,7 @@ void comp_lld_init(void) {
 #if STM32_COMP_USE_COMP1
   /* Driver initialization.*/
   compObjectInit(&COMPD1);
-  COMPD1.reg = COMP;
+  COMPD1.reg = COMP1;
   COMPD1.reg->CSR = 0;
 #if STM32_COMP_USE_INTERRUPTS
   nvicEnableVector(COMP1_2_3_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
@@ -191,6 +199,8 @@ void comp_lld_init(void) {
 
 }
 
+#if STM32_COMP_USE_INTERRUPTS
+
 /**
  * @brief  COMP1, COMP2, COMP3 interrupt handler.
  *
@@ -369,6 +379,8 @@ void comp_ext_lld_channel_disable(COMPDriver *compp, uint32_t channel) {
 #endif
 }
 
+#endif
+
 /**
  * @brief   Configures and activates the COMP peripheral.
  *
@@ -379,11 +391,11 @@ void comp_ext_lld_channel_disable(COMPDriver *compp, uint32_t channel) {
 void comp_lld_start(COMPDriver *compp) {
 
   // Apply CSR Execpt the enable bit.
-  compp->reg->CSR = compp->config->csr & ~COMP_CSR_COMPxEN;
+  compp->reg->CSR = compp->config->csr & ~COMP_CSR_EN;
 
   // Inverted output
   if (compp->config->output_mode == COMP_OUTPUT_INVERTED)
-    compp->reg->CSR |= COMP_CSR_COMPxPOL;
+    compp->reg->CSR |= COMP_CSR_POLARITY;
 
 #if STM32_COMP_USE_INTERRUPTS
 #if STM32_COMP_USE_COMP1
@@ -500,7 +512,7 @@ void comp_lld_stop(COMPDriver *compp) {
  */
 void comp_lld_enable(COMPDriver *compp) {
 
-   compp->reg->CSR |= COMP_CSR_COMPxEN; /* Enable */
+   compp->reg->CSR |= COMP_CSR_EN; /* Enable */
 }
 
 /**
@@ -512,7 +524,7 @@ void comp_lld_enable(COMPDriver *compp) {
  */
 void comp_lld_disable(COMPDriver *compp) {
 
-  compp->reg->CSR &= ~COMP_CSR_COMPxEN; /* Disable */
+  compp->reg->CSR &= ~COMP_CSR_EN; /* Disable */
 }
 
 #endif /* HAL_USE_COMP */

os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.h

@@ -201,9 +201,9 @@
 #define STM32_HAS_COMP6 TRUE
 #define STM32_HAS_COMP7 TRUE
 
-#elif defined(STM32F373xx) || defined(STM32F378xx) || defined(STM32L0XX) || defined(STM32L1XX) \
-  || defined(STM32F051x8) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F078xx) \
-  || defined(STM32F072xb) || defined(STM32F071xb)
+#elif defined(STM32F373xx) || defined(STM32F378xx) || defined(STM32L0XX)   || defined(STM32L1XX) \
+   || defined(STM32F051x8) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F078xx) \
+   || defined(STM32F072xb) || defined(STM32F071xb) || defined(STM32L4XX)
 #define STM32_HAS_COMP1 TRUE
 #define STM32_HAS_COMP2 TRUE
 #define STM32_HAS_COMP3 FALSE

os/hal/ports/STM32/STM32L4xx/platform.mk

@@ -13,12 +13,15 @@ else
 endif
 
 include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/COMPv1/driver.mk
 include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/driver.mk
 include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/driver.mk
 include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/OPAMPv1/driver.mk
 include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/driver.mk
 include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/driver.mk
 
+
 # Shared variables
 ALLCSRC += $(PLATFORMSRC_CONTRIB)
 ALLINC  += $(PLATFORMINC_CONTRIB)

os/hal/src/hal_ee24xx.c

@@ -198,7 +198,7 @@ static size_t __clamp_size(void *ip, size_t n) {
 /**
  * @brief   Write data that can be fitted in one page boundary
  */
-static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *written) {
+static msg_t __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *written) {
 
   msg_t status = MSG_RESET;
 
@@ -210,6 +210,8 @@ static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *
     *written += len;
     eepfs_lseek(ip, eepfs_getposition(ip) + len);
   }
+
+  return status;
 }
 
 /**

tools/mx2board.py

@@ -35,11 +35,15 @@ PIN_PUPDR_FLOATING = "PIN_PUPDR_FLOATING({0})"
 PIN_PUPDR_PULLUP = "PIN_PUPDR_PULLUP({0})"
 PIN_PUPDR_PULLDOWN = "PIN_PUPDR_PULLDOWN({0})"
 PIN_AFIO_AF = "PIN_AFIO_AF({0}, {1})"
+PIN_ASCR_DISABLED = "PIN_ASCR_DISABLED({0})"
+PIN_ASCR_ENABLED = "PIN_ASCR_ENABLED({0})"
+PIN_LOCKR_DISABLED = "PIN_LOCKR_DISABLED({0})"
+PIN_LOCKR_ENABLED = "PIN_LOCKR_ENABLED({0})"
 
 FMT = '{0}'
 FMT_DEF = '({0})'
 
-PIN_CONF_LIST = ['MODER', 'OTYPER', 'OSPEEDR', 'PUPDR', 'ODR']
+PIN_CONF_LIST = ['MODER', 'OTYPER', 'OSPEEDR', 'PUPDR', 'ODR', 'ASCR', 'LOCKR']
 PIN_CONF_LIST_AF = ['AFRL', 'AFRH']
 
 DEFAULT_PAD = {"SIGNAL": "UNUSED",
@@ -48,7 +52,9 @@ DEFAULT_PAD = {"SIGNAL": "UNUSED",
                "OTYPER": PIN_OTYPE_PUSHPULL,
                "OSPEEDR": PIN_OSPEED_VERYLOW,
                "PUPDR": PIN_PUPDR_FLOATING,
-               "ODR": PIN_ODR_LOW}
+               "ODR": PIN_ODR_LOW,
+               "ASCR": PIN_ASCR_DISABLED,
+               "LOCKR": PIN_LOCKR_DISABLED}
 
 PIN_MODE_TRANSLATE = {"GPIO_MODE_AF_PP": PIN_MODE_ALTERNATE,
                       "GPIO_MODE_ANALOG": PIN_MODE_ANALOG,
@@ -207,8 +213,13 @@ def read_project(gpio, filename):
     with open(filename, 'r') as mx_file:
         tmp = mx_file.readlines()
     pads = {}
+    mcu = 'Unknown'
+    
+    for l in tmp:
+        if l.startswith('Mcu.Name'):
+            mcu = l.split('=')[-1].strip()
 
-    # Default all pads to analog
+    # Default pad mode is analog, here we assign proper mode and speed.
     for p in gpio['ports'].keys():
         pads[p] = {}
         for i in range(0, 16):
@@ -267,7 +278,7 @@ def read_project(gpio, filename):
                     pads[pad_port][pad_num]["OTYPER"] = PIN_OTYPE_OPENDRAIN
 
 
-    return pads
+    return mcu, pads
 
 
 # Add defines for all pins with labels
@@ -389,10 +400,11 @@ if __name__ == '__main__':
     else:
         gpio_file = get_gpio_file(args.project, args.mx)
         gpio = read_gpio(gpio_file)
-    proj = read_project(gpio, args.project)
+
+    mcu, proj = read_project(gpio, args.project)
     defines = gen_defines(proj)
     ports = gen_ports(gpio, proj)
-
+    
     with open(cur_path + '/templates/board_gpio.tpl', 'r') as tpl_file:
         tpl = tpl_file.read()
     template = Template(tpl)
@@ -405,6 +417,6 @@ if __name__ == '__main__':
     for p in sorted(ports.keys()):
         ports_sorted.append((p, ports[p]))
 
-    template.stream(defines=defines_sorted, ports=ports_sorted).dump(args.output)
+    template.stream(defines=defines_sorted, ports=ports_sorted, ascr_lockr='L4' in mcu).dump(args.output)
 
     print('File generated at ' + args.output)

tools/templates/board_gpio.tpl

@@ -50,6 +50,19 @@
     {{ i }} | \
     {%- endfor %}
     0)
+{% if ascr_lockr %}
+#define VAL_GPIO{{p}}_ASCR ( \
+    {%- for i in v.ASCR %}
+    {{ i }} | \
+    {%- endfor %}
+    0)
+
+#define VAL_GPIO{{p}}_LOCKR ( \
+    {%- for i in v.LOCKR %}
+    {{ i }} | \
+    {%- endfor %}
+    0)
+{% endif %}
 {% endfor %}
 
-#endif
+#endif