diff --git a/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_spi_config.cpp b/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_spi_config.cpp index ef2d3a1..3e2661a 100644 --- a/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_spi_config.cpp +++ b/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_spi_config.cpp @@ -3,8 +3,16 @@ // See LICENSE file in the project root for full license information. // -#include "win_dev_spi_native.h" +#include "win_dev_spi_native_target.h" -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 +// port for SCK pin is: GPIOA_SPC +// port for MISO pin is: GPIOA_SDO +// port for MOSI pin is: GPIOA_SDI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOA, 5, GPIOA, 6, GPIOA, 7, 5) diff --git a/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_spi_config.cpp b/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_spi_config.cpp index ef2d3a1..8c6cfc2 100644 --- a/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_spi_config.cpp +++ b/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_spi_config.cpp @@ -3,8 +3,28 @@ // See LICENSE file in the project root for full license information. // -#include "win_dev_spi_native.h" +#include "win_dev_spi_native_target.h" -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 +// port for SCK pin is: SPI1_SCLK +// port for MISO pin is: SPI1_MISO +// port for MOSI pin is: SPI1_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOA, 5, GPIOA, 6, GPIOA, 7, 5) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI2 +// port for SCK pin is: SPI2_SCLK +// port for MISO pin is: SPI2_MISO +// port for MOSI pin is: SPI2_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOB, 13, GPIOB, 14, GPIOB, 15, 5) diff --git a/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_spi_config.cpp b/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_spi_config.cpp index ef2d3a1..8c6cfc2 100644 --- a/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_spi_config.cpp +++ b/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_spi_config.cpp @@ -3,8 +3,28 @@ // See LICENSE file in the project root for full license information. // -#include "win_dev_spi_native.h" +#include "win_dev_spi_native_target.h" -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 +// port for SCK pin is: SPI1_SCLK +// port for MISO pin is: SPI1_MISO +// port for MOSI pin is: SPI1_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOA, 5, GPIOA, 6, GPIOA, 7, 5) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI2 +// port for SCK pin is: SPI2_SCLK +// port for MISO pin is: SPI2_MISO +// port for MOSI pin is: SPI2_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOB, 13, GPIOB, 14, GPIOB, 15, 5) diff --git a/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/mcuconf.h b/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/mcuconf.h index b80b4e2..785b44b 100644 --- a/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/mcuconf.h +++ b/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/mcuconf.h @@ -258,10 +258,10 @@ * SPI driver system settings. */ #define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 TRUE -#define STM32_SPI_USE_SPI4 TRUE -#define STM32_SPI_USE_SPI5 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) diff --git a/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_spi_config.cpp b/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_spi_config.cpp index ef2d3a1..b356b09 100644 --- a/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_spi_config.cpp +++ b/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_spi_config.cpp @@ -3,8 +3,16 @@ // See LICENSE file in the project root for full license information. // -#include "win_dev_spi_native.h" +#include "win_dev_spi_native_target.h" -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 +// port for SCK pin is: SPI1_SCLK +// port for MISO pin is: SPI1_MISO +// port for MOSI pin is: SPI1_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOA, 5, GPIOA, 6, GPIOA, 7, 5) diff --git a/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/mcuconf.h b/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/mcuconf.h index 2bc22f1..58cd508 100644 --- a/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/mcuconf.h +++ b/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/mcuconf.h @@ -259,9 +259,9 @@ * SPI driver system settings. */ #define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 TRUE -#define STM32_SPI_USE_SPI4 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE #define STM32_SPI_USE_SPI5 TRUE #define STM32_SPI_USE_SPI6 FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) diff --git a/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_spi_config.cpp b/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_spi_config.cpp index f08c565..6f913e8 100644 --- a/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_spi_config.cpp +++ b/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_spi_config.cpp @@ -5,6 +5,14 @@ #include "win_dev_spi_native_target.h" -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// +////////// +// SPI5 // +////////// + +// pin configuration for SPI5 +// port for SCK pin is: SPI5_SCK +// port for MISO pin is: SPI5_MISO +// port for MOSI pin is: SPI5_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOF, 7, GPIOF, 8, GPIOF, 9, 5) diff --git a/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h b/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h index eeede4f..f283832 100644 --- a/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h +++ b/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h @@ -280,9 +280,9 @@ * SPI driver system settings. */ #define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 TRUE -#define STM32_SPI_USE_SPI4 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE #define STM32_SPI_USE_SPI5 TRUE #define STM32_SPI_USE_SPI6 FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) diff --git a/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_spi_config.cpp b/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_spi_config.cpp index f08c565..6f913e8 100644 --- a/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_spi_config.cpp +++ b/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_spi_config.cpp @@ -5,6 +5,14 @@ #include "win_dev_spi_native_target.h" -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// +////////// +// SPI5 // +////////// + +// pin configuration for SPI5 +// port for SCK pin is: SPI5_SCK +// port for MISO pin is: SPI5_MISO +// port for MOSI pin is: SPI5_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOF, 7, GPIOF, 8, GPIOF, 9, 5) diff --git a/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_spi_config.cpp b/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_spi_config.cpp index ef2d3a1..0dc93e9 100644 --- a/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_spi_config.cpp +++ b/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_spi_config.cpp @@ -3,8 +3,28 @@ // See LICENSE file in the project root for full license information. // -#include "win_dev_spi_native.h" +#include "win_dev_spi_native_target.h" -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// +////////// +// SPI2 // +////////// + +// pin configuration for SPI2 +// port for SCK pin is: SPI2_SCLK +// port for MISO pin is: SPI2_MISO +// port for MOSI pin is: SPI2_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOB, 13, GPIOB, 14, GPIOB, 15, 5) + +////////// +// SPI3 // +////////// + +// pin configuration for SPI3 +// port for SCK pin is: SPI3_SCLK +// port for MISO pin is: SPI3_MISO +// port for MOSI pin is: SPI3_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOC, 10, GPIOC, 11, GPIOC, 12, 5) diff --git a/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_spi_config.cpp b/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_spi_config.cpp index f08c565..4b89dfe 100644 --- a/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_spi_config.cpp +++ b/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_spi_config.cpp @@ -5,6 +5,26 @@ #include "win_dev_spi_native_target.h" -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// +////////// +// SPI2 // +////////// + +// pin configuration for SPI2 +// port for SCK pin is: SPI2_SCLK +// port for MISO pin is: SPI2_MISO +// port for MOSI pin is: SPI2_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOB, 13, GPIOB, 14, GPIOB, 15, 5) + +////////// +// SPI3 // +////////// + +// pin configuration for SPI3 +// port for SCK pin is: SPI3_SCLK +// port for MISO pin is: SPI3_MISO +// port for MOSI pin is: SPI3_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(3, GPIOC, 10, GPIOC, 11, GPIOC, 12, 5) diff --git a/CMSIS-OS/ChibiOS/ST_STM32F411_DISCOVERY/target_windows_devices_spi_config.cpp b/CMSIS-OS/ChibiOS/ST_STM32F411_DISCOVERY/target_windows_devices_spi_config.cpp index f08c565..8c6cfc2 100644 --- a/CMSIS-OS/ChibiOS/ST_STM32F411_DISCOVERY/target_windows_devices_spi_config.cpp +++ b/CMSIS-OS/ChibiOS/ST_STM32F411_DISCOVERY/target_windows_devices_spi_config.cpp @@ -5,6 +5,26 @@ #include "win_dev_spi_native_target.h" -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 +// port for SCK pin is: SPI1_SCLK +// port for MISO pin is: SPI1_MISO +// port for MOSI pin is: SPI1_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOA, 5, GPIOA, 6, GPIOA, 7, 5) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI2 +// port for SCK pin is: SPI2_SCLK +// port for MISO pin is: SPI2_MISO +// port for MOSI pin is: SPI2_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOB, 13, GPIOB, 14, GPIOB, 15, 5) diff --git a/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_spi_config.cpp b/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_spi_config.cpp index ef2d3a1..b356b09 100644 --- a/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_spi_config.cpp +++ b/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_spi_config.cpp @@ -3,8 +3,16 @@ // See LICENSE file in the project root for full license information. // -#include "win_dev_spi_native.h" +#include "win_dev_spi_native_target.h" -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 +// port for SCK pin is: SPI1_SCLK +// port for MISO pin is: SPI1_MISO +// port for MOSI pin is: SPI1_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOA, 5, GPIOA, 6, GPIOA, 7, 5)