Rework NUCLEO64_F411RE (#129)
* Update serial configuration and change OEM String * Change default use of USB on PA11, PA12 to serial use of USART6 * Change default use of PA15, PB7 to use USART1 * Update serial config to use USART1 * Update the OEM String ***ST_NUCLEO64_F411RE_NF*** * Update target_windows_devices_serialcommunication_config.h * Update readme * Include pin use for analog inputs * Include pin use for USART1 * Include pin use for USART6 * Update verification * Inserted a verification mark * Update verification 2 * Another try to verify this stuff Signed-off-by: piwi1263 <piwi1263@gmail.com> * Update verification 3 * Last try before I go crazy on this Signed-off-by: piwi1263 <piwi1263@gmail.com> * Rework DAC support There is no DAC on the STM32F411xE and no external DAC is available on the NUCLEO64-F411RE. * Corrected DAC settings in mcuconf.h * Removed pin setup from DAC configuration Signed-off-by: piwi1263 <piwi1263@gmail.com> Co-authored-by: José Simões <jose.simoes@eclo.solutions>
This commit is contained in:
Peter Wessel
GitHub
Родитель
f4407182fe
Коммит
6dada3bc3c
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@ -1,5 +1,5 @@
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## ST of the shelve board ##
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The board used in this community contribution is the NUCLEO64_F411RE board from ST. The board can be purchased from various sources and should be about 20 euros. Further information on the Nucleo64 boards can be found in the user manual UM1724 on the ST side (www.st.com). The board used here is of revision c as can be found on the board's lower backside sticker. The board MB1136 C-02 is configured to use ST-LINK MCO as clock input for HSE so we have an HSE of 8 MHz. Plus X2 is mounted we do have an LSE as well. This is reflected in the mcuconf.h in both nanoBooter and nanoCLR paths. If it is chosen to activate LSE as this is a more accurate clock for RTC then board.h file needs to be adjusted accordingly to use 32768 frequency for LSE.
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Serial port 2 (USART2) is used to communicate thru the ST-Link connector, so only one Mini-USB cable is used to start the nanoFramework adventure.
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@ -12,7 +12,7 @@ In Visual Studio and with nanoFramework extension being installed, open the Devi
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Now you can start your adventure in the nanoFramework world and use one of the samples and adjust to the board specific features. Try to make a sample of yourself and publish it on f.e. www.hackster.io to show your achievement.
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For your convenience I've listed below the features and on what pins they can be found to help you out for an easy start.
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For your convenience listed below are the features currently set and on what pins they can be found to help you out for an easy start.
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Arduino header pins:
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====================
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@ -22,6 +22,12 @@ Arduino header pins:
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* D11 - D13 are setup and configured for SPI1 however the on board LED (LD2) is connected to D13 as well and might be of influence. In that case solder bridge SB21 needs to be removed.
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* D14 = I2C1 SDA
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* D15 = I2C1 SCL
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* A0 = ADC1 Channel 1
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* A1 = ADC1 Channel 2
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* A2 = ADC1 Channel 3
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* A3 = ADC1 Channel 4
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* A4 = ADC1 Channel 5
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* A5 = ADC1 Channel 6
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Connector CN7:
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@ -29,10 +35,14 @@ Connector CN7:
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* 1 = SPI3 SCK
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* 2 = SPI3 MISO
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* 3 = SPI3 MOSI
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* 17 = USART1 TX
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* 21 = USART1 RX
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Connector CN10:
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===============
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* 12 = USART6 RX
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* 14 = USART6 TX
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* 26 = SPI2 MOSI
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* 28 = SPI2 MISO
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* 30 = SPI2 SCK
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@ -82,11 +82,11 @@
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#define GPIOA_ARD_D7 8U
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#define GPIOA_ARD_D8 9U
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#define GPIOA_ARD_D2 10U
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#define GPIOA_OTG_FS_DM 11U
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#define GPIOA_OTG_FS_DP 12U
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#define GPIOA_USART6_TX 11U
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#define GPIOA_USART6_RX 12U
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#define GPIOA_SWDIO 13U
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#define GPIOA_SWCLK 14U
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#define GPIOA_PIN15 15U
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#define GPIOA_USART1_TX 15U
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#define GPIOB_ARD_A3 0U
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#define GPIOB_ADC1_IN8 0U
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@ -97,7 +97,7 @@
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#define GPIOB_ARD_D5 4U
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#define GPIOB_ARD_D4 5U
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#define GPIOB_ARD_D10 6U
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#define GPIOB_PIN7 7U
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#define GPIOB_USART1_RX 7U
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#define GPIOB_ARD_D15 8U
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#define GPIOB_ARD_D14 9U
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#define GPIOB_ARD_D6 10U
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@ -248,10 +248,11 @@
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#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U)
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#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U)
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#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U)
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#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U)
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#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U)
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#define LINE_USART6_TX PAL_LINE(GPIOA, 11U)
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#define LINE_USART6_RX PAL_LINE(GPIOA, 12U)
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#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
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#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
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#define LINE_USART1_TX PAL_LINE(GPIOA, 15U)
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#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U)
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#define LINE_ADC1_IN8 PAL_LINE(GPIOB, 0U)
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@ -260,6 +261,7 @@
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#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U)
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#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U)
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#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U)
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#define LINE_USART1_RX PAL_LINE(GPIOB, 7U)
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#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U)
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#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U)
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#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U)
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@ -316,11 +318,11 @@
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* PA8 - ARD_D7 (input pullup).
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* PA9 - ARD_D8 (input pullup).
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* PA10 - ARD_D2 (input pullup).
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* PA11 - OTG_FS_DM (alternate 10).
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* PA12 - OTG_FS_DP (alternate 10).
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* PA11 - USART6_TX (alternate 8).
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* PA12 - USART6_RX (alternate 8).
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* PA13 - SWDIO (alternate 0).
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* PA14 - SWCLK (alternate 0).
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* PA15 - PIN15 (input pullup).
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* PA15 - USART1_TX (alternate 7).
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*/
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#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ARD_A0) | \
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PIN_MODE_INPUT(GPIOA_ARD_A1) | \
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@ -333,11 +335,11 @@
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PIN_MODE_INPUT(GPIOA_ARD_D7) | \
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PIN_MODE_INPUT(GPIOA_ARD_D8) | \
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PIN_MODE_INPUT(GPIOA_ARD_D2) | \
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PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
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PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
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PIN_MODE_ALTERNATE(GPIOA_USART6_TX) | \
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PIN_MODE_ALTERNATE(GPIOA_USART6_RX) | \
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PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
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PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
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PIN_MODE_INPUT(GPIOA_PIN15))
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PIN_MODE_ALTERNATE(GPIOA_USART1_TX))
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#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \
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@ -349,15 +351,15 @@
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \
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PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
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PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
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PIN_OTYPE_PUSHPULL(GPIOA_USART6_TX) | \
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PIN_OTYPE_PUSHPULL(GPIOA_USART6_RX) | \
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PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
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PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
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PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
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PIN_OTYPE_PUSHPULL(GPIOA_USART1_TX))
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#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \
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PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \
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PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \
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PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \
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PIN_OSPEED_HIGH(GPIOA_ARD_D1) | \
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PIN_OSPEED_HIGH(GPIOA_ARD_D0) | \
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PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \
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PIN_OSPEED_MEDIUM(GPIOA_LED_GREEN) | \
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PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \
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@ -365,11 +367,11 @@
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PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \
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PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \
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PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \
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PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \
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PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \
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PIN_OSPEED_HIGH(GPIOA_USART6_TX) | \
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PIN_OSPEED_HIGH(GPIOA_USART6_RX) | \
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PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
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PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
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PIN_OSPEED_HIGH(GPIOA_PIN15))
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PIN_OSPEED_HIGH(GPIOA_USART1_TX))
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#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \
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PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | \
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PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \
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@ -381,11 +383,11 @@
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PIN_PUPDR_PULLUP(GPIOA_ARD_D7) | \
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PIN_PUPDR_PULLUP(GPIOA_ARD_D8) | \
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PIN_PUPDR_PULLUP(GPIOA_ARD_D2) | \
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PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
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PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
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PIN_PUPDR_FLOATING(GPIOA_USART6_TX) | \
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PIN_PUPDR_FLOATING(GPIOA_USART6_RX) | \
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PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
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PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
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PIN_PUPDR_PULLUP(GPIOA_PIN15))
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PIN_PUPDR_FLOATING(GPIOA_USART1_TX))
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#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \
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PIN_ODR_HIGH(GPIOA_ARD_A1) | \
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PIN_ODR_HIGH(GPIOA_ARD_D1) | \
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@ -397,11 +399,11 @@
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PIN_ODR_HIGH(GPIOA_ARD_D7) | \
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PIN_ODR_HIGH(GPIOA_ARD_D8) | \
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PIN_ODR_HIGH(GPIOA_ARD_D2) | \
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PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
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PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
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PIN_ODR_HIGH(GPIOA_USART6_TX) | \
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PIN_ODR_HIGH(GPIOA_USART6_RX) | \
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PIN_ODR_HIGH(GPIOA_SWDIO) | \
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PIN_ODR_HIGH(GPIOA_SWCLK) | \
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PIN_ODR_HIGH(GPIOA_PIN15))
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PIN_ODR_HIGH(GPIOA_USART1_TX))
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#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \
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PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \
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PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | \
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@ -413,11 +415,11 @@
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#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \
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PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \
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PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \
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PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \
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PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \
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PIN_AFIO_AF(GPIOA_USART6_TX, 8U) | \
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PIN_AFIO_AF(GPIOA_USART6_RX, 8U) | \
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PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
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PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
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PIN_AFIO_AF(GPIOA_PIN15, 0U))
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PIN_AFIO_AF(GPIOA_USART1_TX, 7U))
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/*
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* GPIOB setup:
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@ -429,7 +431,7 @@
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* PB4 - ARD_D5 (input pullup).
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* PB5 - ARD_D4 (input pullup).
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* PB6 - ARD_D10 (input pullup).
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* PB7 - PIN7 (input pullup).
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* PB7 - USART1_RX (alternate 7).
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* PB8 - ARD_D15 (alternate 4).
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* PB9 - ARD_D14 (alternate 4).
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* PB10 - ARD_D6 (input pullup).
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@ -446,7 +448,7 @@
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PIN_MODE_INPUT(GPIOB_ARD_D5) | \
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PIN_MODE_INPUT(GPIOB_ARD_D4) | \
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PIN_MODE_INPUT(GPIOB_ARD_D10) | \
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PIN_MODE_INPUT(GPIOB_PIN7) | \
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PIN_MODE_ALTERNATE(GPIOB_USART1_RX) | \
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PIN_MODE_ALTERNATE(GPIOB_ARD_D15) | \
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PIN_MODE_ALTERNATE(GPIOB_ARD_D14) | \
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PIN_MODE_INPUT(GPIOB_ARD_D6) | \
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@ -462,7 +464,7 @@
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PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \
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PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \
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PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | \
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PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
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PIN_OTYPE_PUSHPULL(GPIOB_USART1_RX) | \
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PIN_OTYPE_OPENDRAIN(GPIOB_ARD_D15) | \
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PIN_OTYPE_OPENDRAIN(GPIOB_ARD_D14) | \
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PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \
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@ -478,7 +480,7 @@
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PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \
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PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \
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PIN_OSPEED_HIGH(GPIOB_ARD_D10) | \
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PIN_OSPEED_HIGH(GPIOB_PIN7) | \
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PIN_OSPEED_HIGH(GPIOB_USART1_RX) | \
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PIN_OSPEED_MEDIUM(GPIOB_ARD_D15) | \
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PIN_OSPEED_MEDIUM(GPIOB_ARD_D14) | \
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PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \
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@ -494,7 +496,7 @@
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PIN_PUPDR_PULLUP(GPIOB_ARD_D5) | \
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PIN_PUPDR_PULLUP(GPIOB_ARD_D4) | \
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PIN_PUPDR_PULLUP(GPIOB_ARD_D10) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
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PIN_PUPDR_FLOATING(GPIOB_USART1_RX) | \
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PIN_PUPDR_FLOATING(GPIOB_ARD_D15) | \
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PIN_PUPDR_FLOATING(GPIOB_ARD_D14) | \
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PIN_PUPDR_PULLUP(GPIOB_ARD_D6) | \
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@ -510,7 +512,7 @@
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PIN_ODR_HIGH(GPIOB_ARD_D5) | \
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PIN_ODR_HIGH(GPIOB_ARD_D4) | \
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PIN_ODR_HIGH(GPIOB_ARD_D10) | \
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PIN_ODR_HIGH(GPIOB_PIN7) | \
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PIN_ODR_HIGH(GPIOB_USART1_RX) | \
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PIN_ODR_HIGH(GPIOB_ARD_D15) | \
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PIN_ODR_HIGH(GPIOB_ARD_D14) | \
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PIN_ODR_HIGH(GPIOB_ARD_D6) | \
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@ -526,7 +528,7 @@
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PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \
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PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \
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PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN7, 0U))
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PIN_AFIO_AF(GPIOB_USART1_RX, 7U))
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#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 4U) | \
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PIN_AFIO_AF(GPIOB_ARD_D14, 4U) | \
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PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \
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@ -14,6 +14,6 @@
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#include <target_common.h>
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#include <chversion.h>
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|
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#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH)
|
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#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@"
|
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|
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#endif /* _TARGET_BOARD_NANOBOOTER_H_ */
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@ -14,6 +14,6 @@
|
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#include <target_common.h>
|
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#include <chversion.h>
|
||||
|
||||
#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH)
|
||||
#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@"
|
||||
|
||||
#endif /* _TARGET_BOARD_NANOCLR_H_ */
|
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|
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@ -7,8 +7,8 @@
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|
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const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = {
|
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|
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// DAC1, channel 1, GPIO port A, pin 4
|
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{1, 1, GPIOA, 4},
|
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// NO DAC support on the STM32F411xE MCU
|
||||
,
|
||||
|
||||
};
|
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|
||||
|
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|
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@ -6,6 +6,35 @@
|
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#include "target_windows_devices_serialcommunication_config.h"
|
||||
#include "win_dev_serial_native_target.h"
|
||||
|
||||
///////////
|
||||
// UART1 //
|
||||
///////////
|
||||
|
||||
// pin configuration for UART1
|
||||
// port: GPIOA, GPIOB
|
||||
// TX pin: is GPIOA_15
|
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// RX pin: is GPIOB_7
|
||||
// GPIO alternate pin function is 7 (see "Table 9. Alternate function mapping" in STM32F411xC and STM32F411xE datasheet)
|
||||
UART_CONFIG_PINS(1, GPIOA, GPIOB, 15, 7, 7)
|
||||
|
||||
// buffers
|
||||
// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary
|
||||
// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache)
|
||||
#if defined(__GNUC__)
|
||||
__attribute__((aligned (32)))
|
||||
#endif
|
||||
uint8_t Uart1_TxBuffer[UART1_TX_SIZE];
|
||||
#if defined(__GNUC__)
|
||||
__attribute__((aligned (32)))
|
||||
#endif
|
||||
uint8_t Uart1_RxBuffer[UART1_RX_SIZE];
|
||||
|
||||
// initialization for UART1
|
||||
UART_INIT(1, UART1_TX_SIZE, UART1_RX_SIZE)
|
||||
|
||||
// un-initialization for UART1
|
||||
UART_UNINIT(1)
|
||||
|
||||
///////////
|
||||
// UART6 //
|
||||
///////////
|
||||
|
|
|
|||
|
|
@ -4,6 +4,19 @@
|
|||
//
|
||||
|
||||
|
||||
///////////
|
||||
// UART1 //
|
||||
///////////
|
||||
|
||||
// enable USART1
|
||||
#define NF_SERIAL_COMM_STM32_UART_USE_USART1 TRUE
|
||||
|
||||
// buffers size
|
||||
// tx buffer size: 1024 bytes
|
||||
#define UART1_TX_SIZE 1024
|
||||
// rx buffer size: 1024 bytes
|
||||
#define UART1_RX_SIZE 1024
|
||||
|
||||
///////////
|
||||
// UART6 //
|
||||
///////////
|
||||
|
|
|
|||
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