nanoframework
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nf-Community-Targets
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Код Задачи Пакеты Проекты Релизы Вики Активность

Adds MBN_QUAIL target. (#145)

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Robin Jones 2020-11-30 06:54:22 +00:00 коммит произвёл GitHub
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Коммит a70531bfc8
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Идентификатор ключа GPG: 4AEE18F83AFDEB23
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112
CMSIS-OS/ChibiOS/MBN_QUAIL/CMakeLists.txt Normal file
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#
# Copyright (c) .NET Foundation and Contributors
# See LICENSE file in the project root for full license information.
#
include(binutils.common)
include(binutils.ChibiOS)
ENABLE_LANGUAGE(ASM)
# add packages
NF_ADD_COMMON_PACKAGES()
NF_ADD_PLATFORM_PACKAGES()
#######################################
add_subdirectory("common")
add_subdirectory("nanoBooter")
add_subdirectory("nanoCLR")
#######################
# nanoBooter executable
add_executable(
# executables for project, project sources
${NANOBOOTER_PROJECT_NAME}.elf
)
NF_ADD_PLATFORM_DEPENDENCIES(${NANOBOOTER_PROJECT_NAME})
NF_ADD_COMMON_SOURCES(${NANOBOOTER_PROJECT_NAME})
NF_ADD_PLATFORM_SOURCES(${NANOBOOTER_PROJECT_NAME})
# include directories for nanoBooter
NF_ADD_COMMON_INCLUDE_DIRECTORIES(${NANOBOOTER_PROJECT_NAME})
NF_ADD_PLATFORM_INCLUDE_DIRECTORIES(${NANOBOOTER_PROJECT_NAME})
#######################
# nanoCLR executable
add_executable(
# executables for project, project sources
${NANOCLR_PROJECT_NAME}.elf
)
NF_ADD_PLATFORM_DEPENDENCIES(${NANOCLR_PROJECT_NAME})
NF_ADD_COMMON_SOURCES(${NANOCLR_PROJECT_NAME})
NF_ADD_PLATFORM_SOURCES(${NANOCLR_PROJECT_NAME})
# include directories for nanoCLR
NF_ADD_COMMON_INCLUDE_DIRECTORIES(${NANOCLR_PROJECT_NAME})
NF_ADD_PLATFORM_INCLUDE_DIRECTORIES(${NANOCLR_PROJECT_NAME})
# set compiler options
nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf)
nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf)
# set compiler definitions
nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf)
nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf)
# set linker files
if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo)
nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/mbn_quail_booter-DEBUG.ld)
nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/mbn_quail_CLR-DEBUG.ld)
else()
nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/mbn_quail_booter.ld)
nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/mbn_quail_CLR.ld)
endif()
# set linker options
nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf)
nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf)
# add other linker flags
###########################################################
# the sizes of CRT heap and ChibiOS stacks are defined here
############################################################################
# CRT heap is assigned to RAM4 region @ CCM SRAM so we are OK to use it all
############################################################################
set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x10000")
set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x10000")
# generate output files
nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf)
nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf)
# if HEX2DFU tool is available pack the binaries into a DFU package
if(HEX2DFU_TOOL_AVAILABLE)
####################################################################################################
## when changing the linker file make sure to update the new addresses for the image files below ##
## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ##
####################################################################################################
if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo)
NF_GENERATE_DFU_PACKAGE(
${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin 08000000
${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin 08008000
${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.dfu
)
else()
NF_GENERATE_DFU_PACKAGE(
${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin 08000000
${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin 08004000
${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.dfu
)
endif()
endif()

36
CMSIS-OS/ChibiOS/MBN_QUAIL/README.md Normal file
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# This board is now old and has no owner. As such, it may not work out of the box.
## Configuration of Chibios, HAL and MCU ##
For a successful build the following changes are required:
In _halconf.g_ (in both nanoBooter and nanoCLR folders), when compared with a default file:
- HAL_USE_SERIAL to TRUE
- HAL_USE_SERIAL_USB to TRUE
- HAL_USE_USB to TRUE
- SERIAL_DEFAULT_BITRATE to 921600
In _mcuconf.h_ (in both nanoBooter and nanoCLR folders), when compared with a default file:
- STM32_SERIAL_USE_USART2 to TRUE
- STM32_USB_USE_OTG1 to TRUE
In _chconf.h_ (_**only**_ for nanoCLR folder), when compared with a default file:
- set the CORTEX_VTOR_INIT with the appropriate address of the vector table for nanoCLR
## Definitions for each image ##
Any defines specific to an image (nanoBooter or nanoCLR) that are to be made available throughout the code should be added to the _target_board.h.in_. There is one in [nanoBooter](nanoBooter/target_board.h.in) and another in [nanoCLR](nanoCLR/target_board.h.in) directories, allowing different defines for each one.
Defines that are common to a target board should be added to the [_target_common.h.in_](target_common.h.in).
The content of these files is parsed by CMake. It can include CMake variables. Check the documentation of CMake config files [here](https://cmake.org/cmake/help/v3.7/command/configure_file.html?highlight=configure_file).
**NOTE: this configuration was successfully tested in a ST_STM32F4_DISCOVERY board using the Serial over USB connection on USB port 1 that creates a virtual COM port.**
## Floating point
The current build is set to add support for single-precision floating point.
Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`.

266
CMSIS-OS/ChibiOS/MBN_QUAIL/board.c Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#include "stm32_gpio.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief Type of STM32 GPIO port setup.
*/
typedef struct {
uint32_t moder;
uint32_t otyper;
uint32_t ospeedr;
uint32_t pupdr;
uint32_t odr;
uint32_t afrl;
uint32_t afrh;
} gpio_setup_t;
/**
* @brief Type of STM32 GPIO initialization data.
*/
typedef struct {
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
gpio_setup_t PAData;
#endif
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
gpio_setup_t PBData;
#endif
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
gpio_setup_t PCData;
#endif
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
gpio_setup_t PDData;
#endif
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
gpio_setup_t PEData;
#endif
// #if STM32_HAS_GPIOF || defined(__DOXYGEN__)
// gpio_setup_t PFData;
// #endif
// #if STM32_HAS_GPIOG || defined(__DOXYGEN__)
// gpio_setup_t PGData;
// #endif
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
gpio_setup_t PHData;
#endif
// #if STM32_HAS_GPIOI || defined(__DOXYGEN__)
// gpio_setup_t PIData;
// #endif
// #if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
// gpio_setup_t PJData;
// #endif
// #if STM32_HAS_GPIOK || defined(__DOXYGEN__)
// gpio_setup_t PKData;
// #endif
} gpio_config_t;
/**
* @brief STM32 GPIO static initialization data.
*/
static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
#endif
// #if STM32_HAS_GPIOF
// {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
// VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
// #endif
// #if STM32_HAS_GPIOG
// {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
// VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
// #endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
#endif
// #if STM32_HAS_GPIOI
// {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
// VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
// #endif
// #if STM32_HAS_GPIOJ
// {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
// VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
// #endif
// #if STM32_HAS_GPIOK
// {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
// VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
// #endif
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
}
static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
rccResetAHB1(STM32_GPIO_EN_MASK);
rccEnableAHB1(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA
gpio_init(GPIOA, &gpio_default_config.PAData);
#endif
#if STM32_HAS_GPIOB
gpio_init(GPIOB, &gpio_default_config.PBData);
#endif
#if STM32_HAS_GPIOC
gpio_init(GPIOC, &gpio_default_config.PCData);
#endif
#if STM32_HAS_GPIOD
gpio_init(GPIOD, &gpio_default_config.PDData);
#endif
#if STM32_HAS_GPIOE
gpio_init(GPIOE, &gpio_default_config.PEData);
#endif
// #if STM32_HAS_GPIOF
// gpio_init(GPIOF, &gpio_default_config.PFData);
// #endif
// #if STM32_HAS_GPIOG
// gpio_init(GPIOG, &gpio_default_config.PGData);
// #endif
#if STM32_HAS_GPIOH
gpio_init(GPIOH, &gpio_default_config.PHData);
#endif
// #if STM32_HAS_GPIOI
// gpio_init(GPIOI, &gpio_default_config.PIData);
// #endif
// #if STM32_HAS_GPIOJ
// gpio_init(GPIOJ, &gpio_default_config.PJData);
// #endif
// #if STM32_HAS_GPIOK
// gpio_init(GPIOK, &gpio_default_config.PKData);
// #endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Early initialization code.
* @details GPIO ports and system clocks are initialized before everything
* else.
*/
void __early_init(void) {
stm32_gpio_init();
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
return !palReadLine(LINE_SD_DETECT);
}
/**
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
}

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CMSIS-OS/ChibiOS/MBN_QUAIL/board.h Normal file
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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#ifndef BOARD_H
#define BOARD_H
/*
* Board identifier.
*/
#define BOARD_MBN_QUAIL
#define BOARD_NAME "Mikrobus.Net QUAIL"
#define BOARD_OTG_NOVBUSSENS
/*
* Board oscillators-related settings.
* NOTE: LSE not fitted.
*/
#if !defined(STM32_LSECLK)
#define STM32_LSECLK 32768U
#endif
#if !defined(STM32_HSECLK)
#define STM32_HSECLK 12000000U
#endif
/*
* Board voltages.
* Required for performance limits calculation.
*/
#define STM32_VDD 300U
/*
* MCU type as defined in the ST header.
*/
#define STM32F427xx
/*
* IO pins assignments.
*/
#define GPIOA_PA0 0U
#define GPIOA_INT1 1U
#define GPIOA_RST1 2U
#define GPIOA_CS1 3U
#define GPIOA_AN2 4U
#define GPIOA_AN4 5U
#define GPIOA_AN1 6U
#define GPIOA_AN3 7U
#define GPIOA_FLASH_HOLD 8U
#define GPIOA_TX4 9U
#define GPIOA_RX4 10U
#define GPIOA_OTG_FS_DM 11U
#define GPIOA_OTG_FS_DP 12U
#define GPIOA_FLASH_CS 13U
#define GPIOA_INT4 14U
#define GPIOA_GPIO1 15U
#define GPIOB_GPIO2 0U
#define GPIOB_PB1 1U
#define GPIOB_BOOT1 2U
#define GPIOB_SPI1_CLK 3U
#define GPIOB_SPI1_MISO 4U
#define GPIOB_SPI1_MOSI 5U
#define GPIOB_I2C1_SCL 6U
#define GPIOB_I2C1_SDA 7U
#define GPIOB_PB8 8U
#define GPIOB_INT2 9U
#define GPIOB_GPIO3 10U
#define GPIOB_GPIO4 11U
#define GPIOB_GPIO5 12U
#define GPIOB_GPIO6 13U
#define GPIOB_OTG_HS_DM 14U
#define GPIOB_OTG_HS_DP 15U
#define GPIOC_ID0 0U
#define GPIOC_ID1 1U
#define GPIOC_ID2 2U
#define GPIOC_LED3 3U
#define GPIOC_GPIO7 4U
#define GPIOC_GPIO8 5U
#define GPIOC_TX3 6U
#define GPIOC_RX3 7U
#define GPIOC_INT3 8U
#define GPIOC_FLASH_WP 9U
#define GPIOC_SPI3_CLK 10U
#define GPIOC_SPI3_MISO 11U
#define GPIOC_SPI3_MOSI 12U
#define GPIOC_GPIO9 13U
#define GPIOC_OSC32_IN 14U
#define GPIOC_OSC32_OUT 15U
#define GPIOD_RST4 0U
#define GPIOD_CS4 1U
#define GPIOD_GPIO10 2U
#define GPIOD_GPIO11 3U
#define GPIOD_GPIO12 4U
#define GPIOD_TX2 5U
#define GPIOD_RX2 6U
#define GPIOD_GPIO13 7U
#define GPIOD_TX1 8U
#define GPIOD_RX1 9U
#define GPIOD_GPIO14 10U
#define GPIOD_CS3 11U
#define GPIOD_RST3 12U
#define GPIOD_PWM3 13U
#define GPIOD_PWM4 14U
#define GPIOD_PWM2 15U
#define GPIOE_CS2 0U
#define GPIOE_RST2 1U
#define GPIOE_GPIO15 2U
#define GPIOE_GPIO16 3U
#define GPIOE_GPIO17 4U
#define GPIOE_GPIO18 5U
#define GPIOE_GPIO19 6U
#define GPIOE_GPIO20 7U
#define GPIOE_GPIO21 8U
#define GPIOE_PWM1 9U
#define GPIOE_LED2 10U
#define GPIOE_GPIO22 11U
#define GPIOE_USB_DETECT 12U
#define GPIOE_GPIO23 13U
#define GPIOE_GPIO24 14U
#define GPIOE_LED1 15U
#define GPIOH_OSC_IN 0U
#define GPIOH_OSC_OUT 1U
#define GPIOH_PIN2 2U
#define GPIOH_PIN3 3U
#define GPIOH_PIN4 4U
#define GPIOH_PIN5 5U
#define GPIOH_PIN6 6U
#define GPIOH_PIN7 7U
#define GPIOH_PIN8 8U
#define GPIOH_PIN9 9U
#define GPIOH_PIN10 10U
#define GPIOH_PIN11 11U
#define GPIOH_PIN12 12U
#define GPIOH_PIN13 13U
#define GPIOH_PIN14 14U
#define GPIOH_PIN15 15U
/*
* IO lines assignments.
*/
// Christophe : what are those "lines" used for ?
#define LINE_INT1 PAL_LINE(GPIOA, 1U)
#define LINE_RST1 PAL_LINE(GPIOA, 2U)
#define LINE_CS1 PAL_LINE(GPIOA, 3U)
#define LINE_AN2 PAL_LINE(GPIOA, 4U)
#define LINE_AN4 PAL_LINE(GPIOA, 5U)
#define LINE_AN1 PAL_LINE(GPIOA, 6U)
#define LINE_AN3 PAL_LINE(GPIOA, 7U)
// The ANx lines are used by the microSD click board to detect the MicroSD
// _AN1 is when using socket 1
// _AN2 is when using socket 2
// _AN3 is when using socket 3
// _AN4 is when using socket 4
// Whatever socket is used the LINE_SD_DETECT has to match
// and the GPIO configs needs to be adjusted
// - PIN_MODE has to be set to Input
// - PIN_ODR has to be set to High
// - PIN_PUPDR has to be set to Floating
// - PIN_OTYPE has to be set to Pushpull
// - PIN_OSPEED has to be set to High
// - PIN_AFIO has to be set to 0
#define LINE_SD_DETECT PAL_LINE(GPIOA, 6U)
#define LINE_FLASH_HOLD PAL_LINE(GPIOA, 8U)
#define LINE_TX4 PAL_LINE(GPIOA, 9U)
#define LINE_RX4 PAL_LINE(GPIOA, 10U)
#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U)
#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U)
#define LINE_FLASH_CS PAL_LINE(GPIOA, 13U)
#define LINE_INT4 PAL_LINE(GPIOA, 14U)
#define LINE_GPIO1 PAL_LINE(GPIOA, 15U)
#define LINE_GPIO2 PAL_LINE(GPIOB, 0U)
#define LINE_PB1 PAL_LINE(GPIOB, 1U)
#define LINE_BOOT1 PAL_LINE(GPIOB, 2U)
#define LINE_SPI1_CLK PAL_LINE(GPIOB, 3U)
#define LINE_SPI1_MISO PAL_LINE(GPIOB, 4U)
#define LINE_SPI1_MOSI PAL_LINE(GPIOB, 5U)
#define LINE_I2C1_SCL PAL_LINE(GPIOB, 6U)
#define LINE_I2C1_SDA PAL_LINE(GPIOB, 7U)
#define LINE_PB8 PAL_LINE(GPIOB, 8U)
#define LINE_INT2 PAL_LINE(GPIOB, 9U)
#define LINE_GPIO3 PAL_LINE(GPIOB, 10U)
#define LINE_GPIO4 PAL_LINE(GPIOB, 11U)
#define LINE_GPIO5 PAL_LINE(GPIOB, 12U)
#define LINE_GPIO6 PAL_LINE(GPIOB, 13U)
#define LINE_OTG_HS_DM PAL_LINE(GPIOB, 14U)
#define LINE_OTG_HS_DP PAL_LINE(GPIOB, 15U)
#define LINE_ID0 PAL_LINE(GPIOC, 0U)
#define LINE_ID1 PAL_LINE(GPIOC, 1U)
#define LINE_ID2 PAL_LINE(GPIOC, 2U)
#define LINE_LED3 PAL_LINE(GPIOC, 3U)
#define LINE_GPIO7 PAL_LINE(GPIOC, 4U)
#define LINE_GPIO8 PAL_LINE(GPIOC, 5U)
#define LINE_TX3 PAL_LINE(GPIOC, 6U)
#define LINE_RX3 PAL_LINE(GPIOC, 7U)
#define LINE_INT3 PAL_LINE(GPIOC, 8U)
#define LINE_FLASH_WP PAL_LINE(GPIOC, 9U)
#define LINE_SPI3_CLK PAL_LINE(GPIOC, 10U)
#define LINE_SPI3_MISO PAL_LINE(GPIOC, 11U)
#define LINE_SPI3_MOSI PAL_LINE(GPIOC, 12U)
#define LINE_GPIO9 PAL_LINE(GPIOC, 13U)
#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
#define LINE_RST4 PAL_LINE(GPIOD, 0U)
#define LINE_CS4 PAL_LINE(GPIOD, 1U)
#define LINE_CS5 PAL_LINE(GPIOD, 2U)
#define LINE_GPIO11 PAL_LINE(GPIOD, 3U)
#define LINE_GPIO12 PAL_LINE(GPIOD, 4U)
#define LINE_CS6 PAL_LINE(GPIOD, 5U)
#define LINE_RX2 PAL_LINE(GPIOD, 6U)
#define LINE_CS7 PAL_LINE(GPIOD, 7U)
#define LINE_TX1 PAL_LINE(GPIOD, 8U)
#define LINE_RX1 PAL_LINE(GPIOD, 9U)
#define LINE_GPIO14 PAL_LINE(GPIOD, 10U)
#define LINE_CS3 PAL_LINE(GPIOD, 11U)
#define LINE_RST3 PAL_LINE(GPIOD, 12U)
#define LINE_PWM3 PAL_LINE(GPIOD, 13U)
#define LINE_PWM4 PAL_LINE(GPIOD, 14U)
#define LINE_PWM2 PAL_LINE(GPIOD, 15U)
#define LINE_CS2 PAL_LINE(GPIOE, 0U)
#define LINE_RST2 PAL_LINE(GPIOE, 1U)
#define LINE_GPIO15 PAL_LINE(GPIOE, 2U)
#define LINE_GPIO16 PAL_LINE(GPIOE, 3U)
#define LINE_GPIO17 PAL_LINE(GPIOE, 4U)
#define LINE_GPIO18 PAL_LINE(GPIOE, 5U)
#define LINE_GPIO19 PAL_LINE(GPIOE, 6U)
#define LINE_GPIO20 PAL_LINE(GPIOE, 7U)
#define LINE_GPIO21 PAL_LINE(GPIOE, 8U)
#define LINE_PWM1 PAL_LINE(GPIOE, 9U)
#define LINE_LED2 PAL_LINE(GPIOE, 10U)
#define LINE_GPIO22 PAL_LINE(GPIOE, 11U)
#define LINE_USB_DETECT PAL_LINE(GPIOE, 12U)
#define LINE_GPIO23 PAL_LINE(GPIOE, 13U)
#define LINE_GPIO24 PAL_LINE(GPIOE, 14U)
#define LINE_LED1 PAL_LINE(GPIOE, 15U)
#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the STM32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
#define PIN_ODR_LOW(n) (0U << (n))
#define PIN_ODR_HIGH(n) (1U << (n))
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
/*
* GPIOA setup:
*
* PA0 - N/A
* PA1 - INT1 (input floating).
* PA2 - RST1 (input floating).
* PA3 - CS1 (alternate 14).
* PA4 - AN2 (alternate 14).
* PA5 - AN5 (input pullup).
* PA6 - AN1 (input floating).
* PA7 - AN3 (input pullup).
* PA8 - FLASH_HOLD (alternate 4).
* PA9 - TX4 (alternate 7).
* PA10 - RX4 (alternate 7).
* PA11 - OTG_FS_DM (alternate 14).
* PA12 - OTG_FS_DP (alternate 14).
* PA13 - FLASH_CS (alternate 0).
* PA14 - INT4 (alternate 0).
* PA15 - GPIO1 (input floating).
*/
#define VAL_GPIOA_MODER (PIN_MODE_ALTERNATE(GPIOA_PA0) | \
PIN_MODE_INPUT(GPIOA_INT1) | \
PIN_MODE_INPUT(GPIOA_RST1) | \
PIN_MODE_OUTPUT(GPIOA_CS1) | \
PIN_MODE_ANALOG(GPIOA_AN2) | \
PIN_MODE_ANALOG(GPIOA_AN4) | \
PIN_MODE_INPUT(GPIOA_AN1) | \
PIN_MODE_ANALOG(GPIOA_AN3) | \
PIN_MODE_OUTPUT(GPIOA_FLASH_HOLD) | \
PIN_MODE_ALTERNATE(GPIOA_TX4) | \
PIN_MODE_ALTERNATE(GPIOA_RX4) | \
PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
PIN_MODE_OUTPUT(GPIOA_FLASH_CS) | \
PIN_MODE_INPUT(GPIOA_INT4) | \
PIN_MODE_INPUT(GPIOA_GPIO1))
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PA0) | \
PIN_OTYPE_PUSHPULL(GPIOA_INT1) | \
PIN_OTYPE_PUSHPULL(GPIOA_RST1) | \
PIN_OTYPE_PUSHPULL(GPIOA_CS1) | \
PIN_OTYPE_PUSHPULL(GPIOA_AN2) | \
PIN_OTYPE_PUSHPULL(GPIOA_AN4) | \
PIN_OTYPE_PUSHPULL(GPIOA_AN1) | \
PIN_OTYPE_PUSHPULL(GPIOA_AN3) | \
PIN_OTYPE_PUSHPULL(GPIOA_FLASH_HOLD) | \
PIN_OTYPE_PUSHPULL(GPIOA_TX4) | \
PIN_OTYPE_PUSHPULL(GPIOA_RX4) | \
PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
PIN_OTYPE_PUSHPULL(GPIOA_FLASH_CS) | \
PIN_OTYPE_PUSHPULL(GPIOA_INT4) | \
PIN_OTYPE_PUSHPULL(GPIOA_GPIO1))
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PA0) | \
PIN_OSPEED_HIGH(GPIOA_INT1) | \
PIN_OSPEED_HIGH(GPIOA_RST1) | \
PIN_OSPEED_HIGH(GPIOA_CS1) | \
PIN_OSPEED_HIGH(GPIOA_AN2) | \
PIN_OSPEED_HIGH(GPIOA_AN4) | \
PIN_OSPEED_HIGH(GPIOA_AN1) | \
PIN_OSPEED_HIGH(GPIOA_AN3) | \
PIN_OSPEED_HIGH(GPIOA_FLASH_HOLD) | \
PIN_OSPEED_HIGH(GPIOA_TX4) | \
PIN_OSPEED_HIGH(GPIOA_RX4) | \
PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \
PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \
PIN_OSPEED_HIGH(GPIOA_FLASH_CS) | \
PIN_OSPEED_HIGH(GPIOA_INT4) | \
PIN_OSPEED_HIGH(GPIOA_GPIO1))
#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PA0) | \
PIN_PUPDR_FLOATING(GPIOA_INT1) | \
PIN_PUPDR_FLOATING(GPIOA_RST1) | \
PIN_PUPDR_FLOATING(GPIOA_CS1) | \
PIN_PUPDR_FLOATING(GPIOA_AN2) | \
PIN_PUPDR_FLOATING(GPIOA_AN4) | \
PIN_PUPDR_FLOATING(GPIOA_AN1) | \
PIN_PUPDR_FLOATING(GPIOA_AN3) | \
PIN_PUPDR_FLOATING(GPIOA_FLASH_HOLD) | \
PIN_PUPDR_FLOATING(GPIOA_TX4) | \
PIN_PUPDR_FLOATING(GPIOA_RX4) | \
PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
PIN_PUPDR_FLOATING(GPIOA_FLASH_CS) | \
PIN_PUPDR_FLOATING(GPIOA_INT4) | \
PIN_PUPDR_FLOATING(GPIOA_GPIO1))
#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_PA0) | \
PIN_ODR_LOW(GPIOA_INT1) | \
PIN_ODR_LOW(GPIOA_RST1) | \
PIN_ODR_LOW(GPIOA_CS1) | \
PIN_ODR_LOW(GPIOA_AN2) | \
PIN_ODR_LOW(GPIOA_AN4) | \
PIN_ODR_HIGH(GPIOA_AN1) | \
PIN_ODR_LOW(GPIOA_AN3) | \
PIN_ODR_HIGH(GPIOA_FLASH_HOLD) | \
PIN_ODR_LOW(GPIOA_TX4) | \
PIN_ODR_LOW(GPIOA_RX4) | \
PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
PIN_ODR_HIGH(GPIOA_FLASH_CS) | \
PIN_ODR_LOW(GPIOA_INT4) | \
PIN_ODR_LOW(GPIOA_GPIO1))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PA0, 0U) | \
PIN_AFIO_AF(GPIOA_INT1, 0U) | \
PIN_AFIO_AF(GPIOA_RST1, 0U) | \
PIN_AFIO_AF(GPIOA_CS1, 0U) | \
PIN_AFIO_AF(GPIOA_AN2, 0U) | \
PIN_AFIO_AF(GPIOA_AN4, 0U) | \
PIN_AFIO_AF(GPIOA_AN1, 0U) | \
PIN_AFIO_AF(GPIOA_AN3, 0U))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_FLASH_HOLD, 0U) | \
PIN_AFIO_AF(GPIOA_TX4, 7U) | \
PIN_AFIO_AF(GPIOA_RX4, 7U) | \
PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \
PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \
PIN_AFIO_AF(GPIOA_FLASH_CS, 0U) | \
PIN_AFIO_AF(GPIOA_INT4, 0U) | \
PIN_AFIO_AF(GPIOA_GPIO1, 0U))
/*
* GPIOB setup:
*
* PB0 - GPIO2 (alternate 14).
* PB1 - PB1 (alternate 14).
* PB2 - BOOT1 (input pullup).
* PB3 - SPI1_CLK (alternate 0).
* PB4 - SPI1_MISO (input pullup).
* PB5 - SPI1_MOSI (alternate 12).
* PB6 - I2C1_SCL (alternate 12).
* PB7 - PIN7 (input pullup).
* PB8 - PB8 (alternate 14).
* PB9 - INT2 (alternate 14).
* PB10 - GPIO3 (alternate 14).
* PB11 - GPIO4 (alternate 14).
* PB12 - GPIO5 (alternate 12).
* PB13 - GPIO6 (input pulldown).
* PB14 - OTG_HS_DM (alternate 12).
* PB15 - OTG_HS_DP (alternate 12).
*/
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_GPIO2) | \
PIN_MODE_ALTERNATE(GPIOB_PB1) | \
PIN_MODE_ALTERNATE(GPIOB_BOOT1) | \
PIN_MODE_ALTERNATE(GPIOB_SPI1_CLK) | \
PIN_MODE_ALTERNATE(GPIOB_SPI1_MISO) | \
PIN_MODE_ALTERNATE(GPIOB_SPI1_MOSI) | \
PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \
PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \
PIN_MODE_INPUT(GPIOB_PB8) | \
PIN_MODE_INPUT(GPIOB_INT2) | \
PIN_MODE_INPUT(GPIOB_GPIO3) | \
PIN_MODE_INPUT(GPIOB_GPIO4) | \
PIN_MODE_INPUT(GPIOB_GPIO5) | \
PIN_MODE_INPUT(GPIOB_GPIO6) | \
PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \
PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP))
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_GPIO2) | \
PIN_OTYPE_PUSHPULL(GPIOB_PB1) | \
PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \
PIN_OTYPE_PUSHPULL(GPIOB_SPI1_CLK) | \
PIN_OTYPE_PUSHPULL(GPIOB_SPI1_MISO) | \
PIN_OTYPE_PUSHPULL(GPIOB_SPI1_MOSI) | \
PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \
PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \
PIN_OTYPE_PUSHPULL(GPIOB_PB8) | \
PIN_OTYPE_PUSHPULL(GPIOB_INT2) | \
PIN_OTYPE_PUSHPULL(GPIOB_GPIO3) | \
PIN_OTYPE_PUSHPULL(GPIOB_GPIO4) | \
PIN_OTYPE_PUSHPULL(GPIOB_GPIO5) | \
PIN_OTYPE_PUSHPULL(GPIOB_GPIO6) |\
PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \
PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP))
#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_GPIO2) | \
PIN_OSPEED_HIGH(GPIOB_PB1) | \
PIN_OSPEED_HIGH(GPIOB_BOOT1) | \
PIN_OSPEED_HIGH(GPIOB_SPI1_CLK) | \
PIN_OSPEED_HIGH(GPIOB_SPI1_MISO) | \
PIN_OSPEED_HIGH(GPIOB_SPI1_MOSI) | \
PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \
PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \
PIN_OSPEED_HIGH(GPIOB_PB8) | \
PIN_OSPEED_HIGH(GPIOB_INT2) | \
PIN_OSPEED_HIGH(GPIOB_GPIO3) | \
PIN_OSPEED_HIGH(GPIOB_GPIO4) | \
PIN_OSPEED_HIGH(GPIOB_GPIO5) | \
PIN_OSPEED_HIGH(GPIOB_GPIO6) |\
PIN_OSPEED_HIGH(GPIOB_OTG_HS_DM) | \
PIN_OSPEED_HIGH(GPIOB_OTG_HS_DP))
#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_GPIO2) | \
PIN_PUPDR_FLOATING(GPIOB_PB1) | \
PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \
PIN_PUPDR_FLOATING(GPIOB_SPI1_CLK) | \
PIN_PUPDR_FLOATING(GPIOB_SPI1_MISO) | \
PIN_PUPDR_FLOATING(GPIOB_SPI1_MOSI) | \
PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \
PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \
PIN_PUPDR_FLOATING(GPIOB_PB8) | \
PIN_PUPDR_FLOATING(GPIOB_INT2) | \
PIN_PUPDR_FLOATING(GPIOB_GPIO3) | \
PIN_PUPDR_FLOATING(GPIOB_GPIO4) | \
PIN_PUPDR_FLOATING(GPIOB_GPIO5) | \
PIN_PUPDR_FLOATING(GPIOB_GPIO6) |\
PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \
PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP))
#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_GPIO2) | \
PIN_ODR_LOW(GPIOB_PB1) | \
PIN_ODR_HIGH(GPIOB_BOOT1) | \
PIN_ODR_LOW(GPIOB_SPI1_CLK) | \
PIN_ODR_LOW(GPIOB_SPI1_MISO) | \
PIN_ODR_LOW(GPIOB_SPI1_MOSI) | \
PIN_ODR_LOW(GPIOB_I2C1_SCL) | \
PIN_ODR_LOW(GPIOB_I2C1_SDA) | \
PIN_ODR_LOW(GPIOB_PB8) | \
PIN_ODR_LOW(GPIOB_INT2) | \
PIN_ODR_LOW(GPIOB_GPIO3) | \
PIN_ODR_LOW(GPIOB_GPIO4) | \
PIN_ODR_LOW(GPIOB_GPIO5) | \
PIN_ODR_LOW(GPIOB_GPIO6) | \
PIN_ODR_LOW(GPIOB_OTG_HS_DM) | \
PIN_ODR_LOW(GPIOB_OTG_HS_DP))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_GPIO2, 0U) | \
PIN_AFIO_AF(GPIOB_PB1, 0U) | \
PIN_AFIO_AF(GPIOB_BOOT1, 0U) | \
PIN_AFIO_AF(GPIOB_SPI1_CLK, 5U) | \
PIN_AFIO_AF(GPIOB_SPI1_MISO, 5U) | \
PIN_AFIO_AF(GPIOB_SPI1_MOSI, 5U) | \
PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \
PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PB8, 0U) | \
PIN_AFIO_AF(GPIOB_INT2, 0U) | \
PIN_AFIO_AF(GPIOB_GPIO3, 0U) | \
PIN_AFIO_AF(GPIOB_GPIO4, 0U) | \
PIN_AFIO_AF(GPIOB_GPIO5, 0U) | \
PIN_AFIO_AF(GPIOB_GPIO6, 0U) | \
PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12U) | \
PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12U))
/*
* GPIOC setup:
*
* PC0 - ID1 (alternate 12).
* PC1 - ID1 (output pushpull maximum).
* PC2 - ID2 (output pushpull maximum).
* PC3 - PIN3 (input pullup).
* PC4 - GPIO7 (output pushpull maximum).
* PC5 - GPIO8 (input floating).
* PC6 - TX3 (alternate 14).
* PC7 - RX3 (alternate 14).
* PC8 - PIN8 (input pullup).
* PC9 - FLASH_WP (alternate 4).
* PC10 - SPI3_CLK (alternate 14).
* PC11 - PIN11 (input pullup).
* PC12 - PIN12 (input pullup).
* PC13 - PIN13 (input pullup).
* PC14 - OSC32_IN (input floating).
* PC15 - OSC32_OUT (input floating).
*/
#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ID0) | \
PIN_MODE_INPUT(GPIOC_ID1) | \
PIN_MODE_INPUT(GPIOC_ID2) | \
PIN_MODE_OUTPUT(GPIOC_LED3) | \
PIN_MODE_INPUT(GPIOC_GPIO7) | \
PIN_MODE_INPUT(GPIOC_GPIO8) | \
PIN_MODE_ALTERNATE(GPIOC_TX3) | \
PIN_MODE_ALTERNATE(GPIOC_RX3) | \
PIN_MODE_INPUT(GPIOC_INT3) | \
PIN_MODE_OUTPUT(GPIOC_FLASH_WP) | \
PIN_MODE_ALTERNATE(GPIOC_SPI3_CLK) | \
PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) | \
PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) | \
PIN_MODE_INPUT(GPIOC_GPIO9) | \
PIN_MODE_ALTERNATE(GPIOC_OSC32_IN) | \
PIN_MODE_ALTERNATE(GPIOC_OSC32_OUT))
#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ID0) | \
PIN_OTYPE_PUSHPULL(GPIOC_ID1) |\
PIN_OTYPE_PUSHPULL(GPIOC_ID2) |\
PIN_OTYPE_PUSHPULL(GPIOC_LED3) | \
PIN_OTYPE_PUSHPULL(GPIOC_GPIO7) | \
PIN_OTYPE_PUSHPULL(GPIOC_GPIO8) | \
PIN_OTYPE_PUSHPULL(GPIOC_TX3) | \
PIN_OTYPE_PUSHPULL(GPIOC_RX3) | \
PIN_OTYPE_PUSHPULL(GPIOC_INT3) | \
PIN_OTYPE_PUSHPULL(GPIOC_FLASH_WP) | \
PIN_OTYPE_PUSHPULL(GPIOC_SPI3_CLK) | \
PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MISO) | \
PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MOSI) | \
PIN_OTYPE_PUSHPULL(GPIOC_GPIO9) | \
PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ID0) | \
PIN_OSPEED_HIGH(GPIOC_ID1) | \
PIN_OSPEED_HIGH(GPIOC_ID2) | \
PIN_OSPEED_HIGH(GPIOC_LED3) | \
PIN_OSPEED_HIGH(GPIOC_GPIO7) | \
PIN_OSPEED_HIGH(GPIOC_GPIO8) | \
PIN_OSPEED_HIGH(GPIOC_TX3) | \
PIN_OSPEED_HIGH(GPIOC_RX3) | \
PIN_OSPEED_HIGH(GPIOC_INT3) | \
PIN_OSPEED_HIGH(GPIOC_FLASH_WP) | \
PIN_OSPEED_HIGH(GPIOC_SPI3_CLK) | \
PIN_OSPEED_HIGH(GPIOC_SPI3_MISO) | \
PIN_OSPEED_HIGH(GPIOC_SPI3_MOSI) | \
PIN_OSPEED_HIGH(GPIOC_GPIO9) | \
PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \
PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))
#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ID0) | \
PIN_PUPDR_FLOATING(GPIOC_ID1) |\
PIN_PUPDR_FLOATING(GPIOC_ID2) |\
PIN_PUPDR_FLOATING(GPIOC_LED3) | \
PIN_PUPDR_FLOATING(GPIOC_GPIO7) | \
PIN_PUPDR_FLOATING(GPIOC_GPIO8) | \
PIN_PUPDR_FLOATING(GPIOC_TX3) | \
PIN_PUPDR_FLOATING(GPIOC_RX3) | \
PIN_PUPDR_FLOATING(GPIOC_INT3) | \
PIN_PUPDR_FLOATING(GPIOC_FLASH_WP) | \
PIN_PUPDR_FLOATING(GPIOC_SPI3_CLK) | \
PIN_PUPDR_FLOATING(GPIOC_SPI3_MISO) | \
PIN_PUPDR_FLOATING(GPIOC_SPI3_MOSI) | \
PIN_PUPDR_FLOATING(GPIOC_GPIO9) | \
PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
#define VAL_GPIOC_ODR (PIN_ODR_LOW(GPIOC_ID0) | \
PIN_ODR_LOW(GPIOC_ID1) | \
PIN_ODR_LOW(GPIOC_ID2) | \
PIN_ODR_LOW(GPIOC_LED3) | \
PIN_ODR_LOW(GPIOC_GPIO7) | \
PIN_ODR_LOW(GPIOC_GPIO8) | \
PIN_ODR_LOW(GPIOC_TX3) | \
PIN_ODR_LOW(GPIOC_RX3) | \
PIN_ODR_LOW(GPIOC_INT3) | \
PIN_ODR_HIGH(GPIOC_FLASH_WP) | \
PIN_ODR_LOW(GPIOC_SPI3_CLK) | \
PIN_ODR_LOW(GPIOC_SPI3_MISO) | \
PIN_ODR_LOW(GPIOC_SPI3_MOSI) | \
PIN_ODR_LOW(GPIOC_GPIO9) | \
PIN_ODR_LOW(GPIOC_OSC32_IN) | \
PIN_ODR_LOW(GPIOC_OSC32_OUT))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ID0, 0U) | \
PIN_AFIO_AF(GPIOC_ID1, 0U) | \
PIN_AFIO_AF(GPIOC_ID2, 0U) | \
PIN_AFIO_AF(GPIOC_LED3, 0U) | \
PIN_AFIO_AF(GPIOC_GPIO7, 0U) | \
PIN_AFIO_AF(GPIOC_GPIO8, 0U) | \
PIN_AFIO_AF(GPIOC_TX3, 8U) | \
PIN_AFIO_AF(GPIOC_RX3, 8U))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_INT3, 0U) | \
PIN_AFIO_AF(GPIOC_FLASH_WP, 0U) | \
PIN_AFIO_AF(GPIOC_SPI3_CLK, 6U) | \
PIN_AFIO_AF(GPIOC_SPI3_MISO, 6U) | \
PIN_AFIO_AF(GPIOC_SPI3_MOSI, 6U) | \
PIN_AFIO_AF(GPIOC_GPIO9, 0U) | \
PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
/*
* GPIOD setup:
*
* PD0 - RST4 (alternate 12).
* PD1 - CS4 (alternate 12).
* PD2 - PIN2 (input pullup).
* PD3 - GPIO11 (alternate 14).
* PD4 - GPIO12 (input pullup).
* PD5 - PIN5 (input pullup).
* PD6 - RX2 (alternate 14).
* PD7 - PIN7 (input pullup).
* PD8 - TX1 (alternate 12).
* PD9 - RX1 (alternate 12).
* PD10 - GPIO14 (alternate 12).
* PD11 - CS3 (input floating).
* PD12 - RST3 (output pushpull maximum).
* PD13 - PWM3 (output pushpull maximum).
* PD14 - PWM4 (alternate 12).
* PD15 - FMC_D1 (alternate 12).
*/
#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_RST4) | \
PIN_MODE_OUTPUT(GPIOD_CS4) | \
PIN_MODE_INPUT(GPIOD_GPIO10) | \
PIN_MODE_INPUT(GPIOD_GPIO11) | \
PIN_MODE_INPUT(GPIOD_GPIO12) | \
PIN_MODE_ALTERNATE(GPIOD_TX2) | \
PIN_MODE_ALTERNATE(GPIOD_RX2) | \
PIN_MODE_INPUT(GPIOD_GPIO13) | \
PIN_MODE_ALTERNATE(GPIOD_TX1) | \
PIN_MODE_ALTERNATE(GPIOD_RX1) | \
PIN_MODE_INPUT(GPIOD_GPIO14) | \
PIN_MODE_OUTPUT(GPIOD_CS3) | \
PIN_MODE_INPUT(GPIOD_RST3) | \
PIN_MODE_ALTERNATE(GPIOD_PWM3) | \
PIN_MODE_ALTERNATE(GPIOD_PWM4) | \
PIN_MODE_ALTERNATE(GPIOD_PWM2))
#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_RST4) | \
PIN_OTYPE_PUSHPULL(GPIOD_CS4) | \
PIN_OTYPE_PUSHPULL(GPIOD_GPIO10) | \
PIN_OTYPE_PUSHPULL(GPIOD_GPIO11) | \
PIN_OTYPE_PUSHPULL(GPIOD_GPIO12) | \
PIN_OTYPE_PUSHPULL(GPIOD_TX2) | \
PIN_OTYPE_PUSHPULL(GPIOD_RX2) | \
PIN_OTYPE_PUSHPULL(GPIOD_GPIO13) | \
PIN_OTYPE_PUSHPULL(GPIOD_TX1) | \
PIN_OTYPE_PUSHPULL(GPIOD_RX1) | \
PIN_OTYPE_PUSHPULL(GPIOD_GPIO14) | \
PIN_OTYPE_PUSHPULL(GPIOD_CS3) | \
PIN_OTYPE_PUSHPULL(GPIOD_RST3) | \
PIN_OTYPE_PUSHPULL(GPIOD_PWM3) | \
PIN_OTYPE_PUSHPULL(GPIOD_PWM4) | \
PIN_OTYPE_PUSHPULL(GPIOD_PWM2))
#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_RST4) | \
PIN_OSPEED_HIGH(GPIOD_CS4) | \
PIN_OSPEED_HIGH(GPIOD_GPIO10) | \
PIN_OSPEED_HIGH(GPIOD_GPIO11) | \
PIN_OSPEED_HIGH(GPIOD_GPIO12) | \
PIN_OSPEED_HIGH(GPIOD_TX2) | \
PIN_OSPEED_HIGH(GPIOD_RX2) | \
PIN_OSPEED_HIGH(GPIOD_GPIO13) | \
PIN_OSPEED_HIGH(GPIOD_TX1) | \
PIN_OSPEED_HIGH(GPIOD_RX1) | \
PIN_OSPEED_HIGH(GPIOD_GPIO14) | \
PIN_OSPEED_HIGH(GPIOD_CS3) | \
PIN_OSPEED_HIGH(GPIOD_RST3) | \
PIN_OSPEED_HIGH(GPIOD_PWM3) | \
PIN_OSPEED_HIGH(GPIOD_PWM4) | \
PIN_OSPEED_HIGH(GPIOD_PWM2))
#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_RST4) | \
PIN_PUPDR_FLOATING(GPIOD_CS4) | \
PIN_PUPDR_FLOATING(GPIOD_GPIO10) | \
PIN_PUPDR_FLOATING(GPIOD_GPIO11) | \
PIN_PUPDR_FLOATING(GPIOD_GPIO12) | \
PIN_PUPDR_FLOATING(GPIOD_TX2) | \
PIN_PUPDR_FLOATING(GPIOD_RX2) | \
PIN_PUPDR_FLOATING(GPIOD_GPIO13) | \
PIN_PUPDR_FLOATING(GPIOD_TX1) | \
PIN_PUPDR_FLOATING(GPIOD_RX1) | \
PIN_PUPDR_FLOATING(GPIOD_GPIO14) | \
PIN_PUPDR_FLOATING(GPIOD_CS3) | \
PIN_PUPDR_FLOATING(GPIOD_RST3) | \
PIN_PUPDR_FLOATING(GPIOD_PWM3) | \
PIN_PUPDR_FLOATING(GPIOD_PWM4) | \
PIN_PUPDR_FLOATING(GPIOD_PWM2))
#define VAL_GPIOD_ODR (PIN_ODR_LOW(GPIOD_RST4) | \
PIN_ODR_LOW(GPIOD_CS4) | \
PIN_ODR_LOW(GPIOD_GPIO10) | \
PIN_ODR_LOW(GPIOD_GPIO11) | \
PIN_ODR_LOW(GPIOD_GPIO12) | \
PIN_ODR_LOW(GPIOD_TX2) | \
PIN_ODR_LOW(GPIOD_RX2) | \
PIN_ODR_LOW(GPIOD_GPIO13) | \
PIN_ODR_LOW(GPIOD_TX1) | \
PIN_ODR_LOW(GPIOD_RX1) | \
PIN_ODR_LOW(GPIOD_GPIO14) | \
PIN_ODR_LOW(GPIOD_CS3) | \
PIN_ODR_LOW(GPIOD_RST3) | \
PIN_ODR_LOW(GPIOD_PWM3) | \
PIN_ODR_LOW(GPIOD_PWM4) | \
PIN_ODR_LOW(GPIOD_PWM2))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_RST4, 0U) | \
PIN_AFIO_AF(GPIOD_CS4, 0U) | \
PIN_AFIO_AF(GPIOD_GPIO10, 0U) | \
PIN_AFIO_AF(GPIOD_GPIO11, 0U) | \
PIN_AFIO_AF(GPIOD_GPIO12, 0U) | \
PIN_AFIO_AF(GPIOD_TX2, 7U) | \
PIN_AFIO_AF(GPIOD_RX2, 7U) | \
PIN_AFIO_AF(GPIOD_GPIO13, 0U))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_TX1, 7U) | \
PIN_AFIO_AF(GPIOD_RX1, 7U) | \
PIN_AFIO_AF(GPIOD_GPIO14, 0U) | \
PIN_AFIO_AF(GPIOD_CS3, 0U) | \
PIN_AFIO_AF(GPIOD_RST3, 0U) | \
PIN_AFIO_AF(GPIOD_PWM3, 2U) | \
PIN_AFIO_AF(GPIOD_PWM4, 2U) | \
PIN_AFIO_AF(GPIOD_PWM2, 2U))
/*
* GPIOE setup:
*
* PE0 - CS2 (alternate 12).
* PE1 - RST2 (alternate 12).
* PE2 - PIN2 (input pullup).
* PE3 - PIN3 (input pullup).
* PE4 - SPI1_MISO (input pullup).
* PE5 - PIN5 (input pullup).
* PE6 - PIN6 (input pullup).
* PE7 - GPIO20 (alternate 12).
* PE8 - GPIO21 (alternate 12).
* PE9 - PWM1 (alternate 12).
* PE10 - FMC_D7 (alternate 12).
* PE11 - GPIO22 (alternate 12).
* PE12 - USB_DETECT (alternate 12).
* PE13 - GPIO23 (alternate 12).
* PE14 - GPIO24 (alternate 12).
* PE15 - FMC_D12 (alternate 12).
*/
#define VAL_GPIOE_MODER (PIN_MODE_OUTPUT(GPIOE_CS2) | \
PIN_MODE_INPUT(GPIOE_RST2) | \
PIN_MODE_INPUT(GPIOE_GPIO15) | \
PIN_MODE_INPUT(GPIOE_GPIO16) | \
PIN_MODE_INPUT(GPIOE_GPIO17) | \
PIN_MODE_INPUT(GPIOE_GPIO18) | \
PIN_MODE_INPUT(GPIOE_GPIO19) | \
PIN_MODE_INPUT(GPIOE_GPIO20) | \
PIN_MODE_INPUT(GPIOE_GPIO21) | \
PIN_MODE_ALTERNATE(GPIOE_PWM1) | \
PIN_MODE_OUTPUT(GPIOE_LED2) | \
PIN_MODE_INPUT(GPIOE_GPIO22) | \
PIN_MODE_ALTERNATE(GPIOE_USB_DETECT) | \
PIN_MODE_INPUT(GPIOE_GPIO23) | \
PIN_MODE_INPUT(GPIOE_GPIO24) | \
PIN_MODE_OUTPUT(GPIOE_LED1))
#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_CS2) | \
PIN_OTYPE_PUSHPULL(GPIOE_RST2) | \
PIN_OTYPE_PUSHPULL(GPIOE_GPIO15) | \
PIN_OTYPE_PUSHPULL(GPIOE_GPIO16) | \
PIN_OTYPE_PUSHPULL(GPIOE_GPIO17) | \
PIN_OTYPE_PUSHPULL(GPIOE_GPIO18) | \
PIN_OTYPE_PUSHPULL(GPIOE_GPIO19) | \
PIN_OTYPE_PUSHPULL(GPIOE_GPIO20) | \
PIN_OTYPE_PUSHPULL(GPIOE_GPIO21) | \
PIN_OTYPE_PUSHPULL(GPIOE_PWM1) | \
PIN_OTYPE_PUSHPULL(GPIOE_LED2) | \
PIN_OTYPE_PUSHPULL(GPIOE_GPIO22) | \
PIN_OTYPE_PUSHPULL(GPIOE_USB_DETECT) | \
PIN_OTYPE_PUSHPULL(GPIOE_GPIO23) | \
PIN_OTYPE_PUSHPULL(GPIOE_GPIO24) | \
PIN_OTYPE_PUSHPULL(GPIOE_LED1))
#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_CS2) | \
PIN_OSPEED_HIGH(GPIOE_RST2) | \
PIN_OSPEED_HIGH(GPIOE_GPIO15) | \
PIN_OSPEED_HIGH(GPIOE_GPIO16) | \
PIN_OSPEED_HIGH(GPIOE_GPIO17) | \
PIN_OSPEED_HIGH(GPIOE_GPIO18) | \
PIN_OSPEED_HIGH(GPIOE_GPIO19) | \
PIN_OSPEED_HIGH(GPIOE_GPIO20) | \
PIN_OSPEED_HIGH(GPIOE_GPIO21) | \
PIN_OSPEED_HIGH(GPIOE_PWM1) | \
PIN_OSPEED_HIGH(GPIOE_LED2) | \
PIN_OSPEED_HIGH(GPIOE_GPIO22) | \
PIN_OSPEED_HIGH(GPIOE_USB_DETECT) | \
PIN_OSPEED_HIGH(GPIOE_GPIO23) | \
PIN_OSPEED_HIGH(GPIOE_GPIO24) | \
PIN_OSPEED_HIGH(GPIOE_LED1))
#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_CS2) | \
PIN_PUPDR_FLOATING(GPIOE_RST2) | \
PIN_PUPDR_FLOATING(GPIOE_GPIO15) | \
PIN_PUPDR_FLOATING(GPIOE_GPIO16) | \
PIN_PUPDR_FLOATING(GPIOE_GPIO17) | \
PIN_PUPDR_FLOATING(GPIOE_GPIO18) | \
PIN_PUPDR_FLOATING(GPIOE_GPIO19) | \
PIN_PUPDR_FLOATING(GPIOE_GPIO20) | \
PIN_PUPDR_FLOATING(GPIOE_GPIO21) | \
PIN_PUPDR_FLOATING(GPIOE_PWM1) | \
PIN_PUPDR_FLOATING(GPIOE_LED2) | \
PIN_PUPDR_FLOATING(GPIOE_GPIO22) | \
PIN_PUPDR_FLOATING(GPIOE_USB_DETECT) | \
PIN_PUPDR_FLOATING(GPIOE_GPIO23) | \
PIN_PUPDR_FLOATING(GPIOE_GPIO24) | \
PIN_PUPDR_FLOATING(GPIOE_LED1))
#define VAL_GPIOE_ODR (PIN_ODR_LOW(GPIOE_CS2) | \
PIN_ODR_LOW(GPIOE_RST2) | \
PIN_ODR_LOW(GPIOE_GPIO15) | \
PIN_ODR_LOW(GPIOE_GPIO16) | \
PIN_ODR_LOW(GPIOE_GPIO17) | \
PIN_ODR_LOW(GPIOE_GPIO18) | \
PIN_ODR_LOW(GPIOE_GPIO19) | \
PIN_ODR_LOW(GPIOE_GPIO20) | \
PIN_ODR_LOW(GPIOE_GPIO21) | \
PIN_ODR_LOW(GPIOE_PWM1) | \
PIN_ODR_LOW(GPIOE_LED2) | \
PIN_ODR_LOW(GPIOE_GPIO22) | \
PIN_ODR_LOW(GPIOE_USB_DETECT) | \
PIN_ODR_LOW(GPIOE_GPIO23) | \
PIN_ODR_LOW(GPIOE_GPIO24) | \
PIN_ODR_LOW(GPIOE_LED1))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_CS2, 0U) | \
PIN_AFIO_AF(GPIOE_RST2, 0U) | \
PIN_AFIO_AF(GPIOE_GPIO15, 0U) | \
PIN_AFIO_AF(GPIOE_GPIO16, 0U) | \
PIN_AFIO_AF(GPIOE_GPIO17, 0U) | \
PIN_AFIO_AF(GPIOE_GPIO18, 0U) | \
PIN_AFIO_AF(GPIOE_GPIO19, 0U) | \
PIN_AFIO_AF(GPIOE_GPIO20, 0U))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_GPIO21, 0U) | \
PIN_AFIO_AF(GPIOE_PWM1, 1U) | \
PIN_AFIO_AF(GPIOE_LED2, 0U) | \
PIN_AFIO_AF(GPIOE_GPIO22, 0U) | \
PIN_AFIO_AF(GPIOE_USB_DETECT, 0U) | \
PIN_AFIO_AF(GPIOE_GPIO23, 0U) | \
PIN_AFIO_AF(GPIOE_GPIO24, 0U) | \
PIN_AFIO_AF(GPIOE_LED1, 0U))
/*
* GPIOH setup:
*
* PH0 - OSC_IN (input floating).
* PH1 - OSC_OUT (input floating).
* PH2 - PIN2 (input pullup).
* PH3 - PIN3 (input pullup).
* PH4 - SPI1_MISO (input pullup).
* PH5 - PIN5 (input pullup).
* PH6 - PIN6 (input pullup).
* PH7 - PIN7 (input pullup).
* PH8 - PIN8 (input pullup).
* PH9 - PIN9 (input pullup).
* PH10 - PIN10 (input pullup).
* PH11 - PIN11 (input pullup).
* PH12 - PIN12 (input pullup).
* PH13 - PIN13 (input pullup).
* PH14 - PIN14 (input pullup).
* PH15 - PIN15 (input pullup).
*/
#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
PIN_MODE_INPUT(GPIOH_PIN2) | \
PIN_MODE_INPUT(GPIOH_PIN3) | \
PIN_MODE_INPUT(GPIOH_PIN4) | \
PIN_MODE_INPUT(GPIOH_PIN5) | \
PIN_MODE_INPUT(GPIOH_PIN6) | \
PIN_MODE_INPUT(GPIOH_PIN7) | \
PIN_MODE_INPUT(GPIOH_PIN8) | \
PIN_MODE_INPUT(GPIOH_PIN9) | \
PIN_MODE_INPUT(GPIOH_PIN10) | \
PIN_MODE_INPUT(GPIOH_PIN11) | \
PIN_MODE_INPUT(GPIOH_PIN12) | \
PIN_MODE_INPUT(GPIOH_PIN13) | \
PIN_MODE_INPUT(GPIOH_PIN14) | \
PIN_MODE_INPUT(GPIOH_PIN15))
#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \
PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \
PIN_OSPEED_VERYLOW(GPIOH_PIN15))
#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
PIN_PUPDR_PULLUP(GPIOH_PIN4) | \
PIN_PUPDR_PULLUP(GPIOH_PIN5) | \
PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
PIN_PUPDR_PULLUP(GPIOH_PIN13) | \
PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
PIN_PUPDR_PULLUP(GPIOH_PIN15))
#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
PIN_ODR_HIGH(GPIOH_PIN2) | \
PIN_ODR_HIGH(GPIOH_PIN3) | \
PIN_ODR_HIGH(GPIOH_PIN4) | \
PIN_ODR_HIGH(GPIOH_PIN5) | \
PIN_ODR_HIGH(GPIOH_PIN6) | \
PIN_ODR_HIGH(GPIOH_PIN7) | \
PIN_ODR_HIGH(GPIOH_PIN8) | \
PIN_ODR_HIGH(GPIOH_PIN9) | \
PIN_ODR_HIGH(GPIOH_PIN10) | \
PIN_ODR_HIGH(GPIOH_PIN11) | \
PIN_ODR_HIGH(GPIOH_PIN12) | \
PIN_ODR_HIGH(GPIOH_PIN13) | \
PIN_ODR_HIGH(GPIOH_PIN14) | \
PIN_ODR_HIGH(GPIOH_PIN15))
#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
PIN_AFIO_AF(GPIOH_PIN7, 0U))
#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
PIN_AFIO_AF(GPIOH_PIN15, 0U))
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* BOARD_H */

61
CMSIS-OS/ChibiOS/MBN_QUAIL/cmake-variants.json Normal file
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{
"buildType": {
"default": "debug",
"choices": {
"debug": {
"short": "Debug",
"long": "Emit debug information without performing optimizations",
"buildType": "Debug"
},
"minsize": {
"short": "MinSizeRel",
"long": "Optimize for smallest binary size",
"buildType": "MinSizeRel"
},
"reldeb": {
"short": "RelWithDebInfo",
"long": "Perform optimizations AND include debugging information",
"buildType": "RelWithDebInfo"
}
}
},
"linkage": {
"default": "",
"choices": {
"MBN_QUAIL": {
"short": "MBN_QUAIL",
"settings": {
"BUILD_VERSION": "0.9.99.999",
"CMAKE_TOOLCHAIN_FILE" : "CMake/toolchain.arm-none-eabi.cmake",
"TOOLCHAIN_PREFIX": "<absolute-path-to-the-toolchain-folder-mind-the-forward-slashes>",
"TOOL_HEX2DFU_PREFIX": "<absolute-path-to-hex2dfu-mind-the-forward-slashes>",
"RTOS": "CHIBIOS",
"TARGET_SERIES": "STM32F4xx",
"RTOS_SOURCE_FOLDER": "",
"RTOS_BOARD": "MBN_QUAIL",
"CHIBIOS_CONTRIB_REQUIRED": "OFF",
"CHIBIOS_CONTRIB_SOURCE": "",
"STM32_CUBE_PACKAGE_REQUIRED": "OFF",
"STM32_CUBE_PACKAGE_SOURCE": "",
"SUPPORT_ANY_BASE_CONVERSION": "ON",
"NF_FEATURE_DEBUGGER": "ON",
"NF_FEATURE_RTC": "ON",
"NF_BUILD_RTM": "OFF",
"API_System.Math": "ON",
"API_Hardware.Stm32": "ON",
"API_Windows.Devices.Gpio": "ON",
"API_System.Device.Gpio": "ON",
"API_Windows.Devices.Spi": "ON",
"API_Windows.Devices.I2c": "ON",
"API_System.Device.I2c": "ON",
"API_Windows.Devices.Pwm": "ON",
"API_Windows.Devices.SerialCommunication": "ON",
"API_nanoFramework.Devices.OneWire": "ON",
"API_nanoFramework.ResourceManager": "ON",
"API_nanoFramework.System.Collections": "ON",
"API_nanoFramework.System.Text": "ON"
}
}
}
}
}

11
CMSIS-OS/ChibiOS/MBN_QUAIL/common/CMakeLists.txt Normal file
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#
# Copyright (c) .NET Foundation and Contributors
# See LICENSE file in the project root for full license information.
#
# append common source files
list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c")
list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$<OR:$<CONFIG:Debug>,$<CONFIG:RelWithDebInfo>>:-DEBUG>.c")
# make var global
set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global")

142
CMSIS-OS/ChibiOS/MBN_QUAIL/common/Device_BlockStorage-DEBUG.c Normal file
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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#include <nanoHAL_Types.h>
#include <nanoPAL_BlockStorage.h>
//16kB block
const BlockRange BlockRange1[] =
{
{ BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 1 }, // 0x08000000 nanoBooter
{ BlockRange_BLOCKTYPE_CODE , 2, 3 } // 0x08008000 nanoCLR
};
//64kB block
const BlockRange BlockRange2[] =
{
{ BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08010000 nanoCLR
};
//128kB block
const BlockRange BlockRange3[] =
{
{ BlockRange_BLOCKTYPE_CODE , 0, 3 }, // 0x08020000 nanoCLR
{ BlockRange_BLOCKTYPE_DEPLOYMENT, 4, 6 }, // 0x080A0000 deployment
};
//16kB block
const BlockRange BlockRange4[] =
{
{ BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 3 } // 0x08100000 deployment
};
//64kB block
const BlockRange BlockRange5[] =
{
{ BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0 } // 0x08110000 deployment
};
//128kB block
const BlockRange BlockRange6[] =
{
{ BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 6 } // 0x08120000 deployment
};
const BlockRegionInfo BlockRegions[] =
{
{
(0), // no attributes for this region
0x08000000, // start address for block region
4, // total number of blocks in this region
0x4000, // total number of bytes per block
ARRAYSIZE_CONST_EXPR(BlockRange1),
BlockRange1,
},
{
(0), // no attributes for this region
0x08010000, // start address for block region
1, // total number of blocks in this region
0x10000, // total number of bytes per block
ARRAYSIZE_CONST_EXPR(BlockRange2),
BlockRange2,
},
{
(0), // no attributes for this region
0x08020000, // start address for block region
7, // total number of blocks in this region
0x20000, // total number of bytes per block
ARRAYSIZE_CONST_EXPR(BlockRange3),
BlockRange3,
},
{
(0), // no attributes for this region
0x08100000, // start address for block region
4, // total number of blocks in this region
0x4000, // total number of bytes per block
ARRAYSIZE_CONST_EXPR(BlockRange4),
BlockRange4,
},
{
(0), // no attributes for this region
0x08110000, // start address for block region
1, // total number of blocks in this region
0x10000, // total number of bytes per block
ARRAYSIZE_CONST_EXPR(BlockRange5),
BlockRange5,
},
{
(0), // no attributes for this region
0x08120000, // start address for block region
7, // total number of blocks in this region
0x20000, // total number of bytes per block
ARRAYSIZE_CONST_EXPR(BlockRange6),
BlockRange6,
},
};
const DeviceBlockInfo Device_BlockInfo =
{
(MediaAttribute_SupportsXIP), // STM32 flash memory is XIP
2, // UINT32 BytesPerSector
ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions;
(BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions;
};
MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig =
{
{ // BLOCK_CONFIG
{
0, // GPIO_PIN Pin;
false, // BOOL ActiveState;
},
(DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo
},
{ // CPU_MEMORY_CONFIG
0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect;
true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly;
0, // UINT32 CPU_MEMORY_CONFIG::WaitStates;
0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts;
16, // UINT32 CPU_MEMORY_CONFIG::BitWidth;
0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress;
0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes;
0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable
0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead
0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable
},
0, // UINT32 ChipProtection;
0, // UINT32 ManufacturerCode;
0, // UINT32 DeviceCode;
};
BlockStorageDevice Device_BlockStorage;

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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#include <nanoHAL_Types.h>
#include <nanoPAL_BlockStorage.h>
// 16kB block
const BlockRange BlockRange1[] = {
{BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 1}, // 0x08000000 nanoBooter
{BlockRange_BLOCKTYPE_CODE, 2, 3} // 0x08008000 nanoCLR
};
// 64kB block
const BlockRange BlockRange2[] = {
{BlockRange_BLOCKTYPE_CODE, 0, 0} // 0x08010000 nanoCLR
};
// 128kB block
const BlockRange BlockRange3[] = {
{BlockRange_BLOCKTYPE_CODE, 0, 0}, // 0x08020000 nanoCLR
{BlockRange_BLOCKTYPE_DEPLOYMENT, 1, 6}, // 0x08040000 deployment
};
// 16kB block
const BlockRange BlockRange4[] = {
{BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 3} // 0x08100000 deployment
};
// 64kB block
const BlockRange BlockRange5[] = {
{BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0} // 0x08110000 deployment
};
// 128kB block
const BlockRange BlockRange6[] = {
{BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 6} // 0x08120000 deployment
};
const BlockRegionInfo BlockRegions[] = {
{
(0), // no attributes for this region
0x08000000, // start address for block region
4, // total number of blocks in this region
0x4000, // total number of bytes per block
ARRAYSIZE_CONST_EXPR(BlockRange1),
BlockRange1,
},
{
(0), // no attributes for this region
0x08010000, // start address for block region
1, // total number of blocks in this region
0x10000, // total number of bytes per block
ARRAYSIZE_CONST_EXPR(BlockRange2),
BlockRange2,
},
{
(0), // no attributes for this region
0x08020000, // start address for block region
7, // total number of blocks in this region
0x20000, // total number of bytes per block
ARRAYSIZE_CONST_EXPR(BlockRange3),
BlockRange3,
},
{
(0), // no attributes for this region
0x08100000, // start address for block region
4, // total number of blocks in this region
0x4000, // total number of bytes per block
ARRAYSIZE_CONST_EXPR(BlockRange4),
BlockRange4,
},
{
(0), // no attributes for this region
0x08110000, // start address for block region
1, // total number of blocks in this region
0x10000, // total number of bytes per block
ARRAYSIZE_CONST_EXPR(BlockRange5),
BlockRange5,
},
{
(0), // no attributes for this region
0x08120000, // start address for block region
7, // total number of blocks in this region
0x20000, // total number of bytes per block
ARRAYSIZE_CONST_EXPR(BlockRange6),
BlockRange6,
},
};
const DeviceBlockInfo Device_BlockInfo = {
(MediaAttribute_SupportsXIP), // STM32 flash memory is XIP
2, // UINT32 BytesPerSector
ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions;
(BlockRegionInfo *)BlockRegions, // const BlockRegionInfo* pRegions;
};
MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = {
{
// BLOCK_CONFIG
{
0, // GPIO_PIN Pin;
false, // BOOL ActiveState;
},
(DeviceBlockInfo *)&Device_BlockInfo, // BlockDeviceinfo
},
{
// CPU_MEMORY_CONFIG
0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect;
true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly;
0, // UINT32 CPU_MEMORY_CONFIG::WaitStates;
0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts;
16, // UINT32 CPU_MEMORY_CONFIG::BitWidth;
0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress;
0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes;
0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable
0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead
0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable
},
0, // UINT32 ChipProtection;
0, // UINT32 ManufacturerCode;
0, // UINT32 DeviceCode;
};
BlockStorageDevice Device_BlockStorage;

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//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.
// See LICENSE file in the project root for full license information.
//
#include "hal.h"
/* Virtual serial port over USB.*/
SerialUSBDriver SDU1;
/*
* Endpoints to be used for USBD2.
*/
#define USBD2_DATA_REQUEST_EP 1
#define USBD2_DATA_AVAILABLE_EP 1
#define USBD2_INTERRUPT_REQUEST_EP 2
// address for device unique ID
// valid for STM32F4 series
#define DEVICE_ID1 (0x1FFF7A10)
#define DEVICE_ID2 (0x1FFF7A14)
#define DEVICE_ID3 (0x1FFF7A18)
// // size of string serial is 36 = 2 + 5x2 + 26 from silicon unique ID precedeed of string "NANO_" and descriptor codes
// #define USB_SIZ_STRING_SERIAL 36
////////////////////////////////////////////////
// vendor
#define USB_STRING_VENDOR L"Mikrobus.Net"
////////////////////////////////////////////////
// structure for USB Vendor with Unicode string
typedef struct usb_string_vendor
{
uint8_t bLength;
uint8_t bDescriptorType;
wchar_t bPropertyData[sizeof(USB_STRING_VENDOR)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec)
}usb_string_vendor;
/////////////////////////////////////////////////////////////////////////
// device description
#define USB_STRING_DEVICE_DESCRIPTION L"Quail Virtual COM Port"
/////////////////////////////////////////////////////////////////////////
// structure for USB device descriptor with Unicode string
typedef struct usb_string_device_description
{
uint8_t bLength;
uint8_t bDescriptorType;
wchar_t bPropertyData[sizeof(USB_STRING_DEVICE_DESCRIPTION)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec)
}usb_string_device_description;
/////////////////////////////////////////////////////////////////////////
// device serial number
// this will produce a string with NANO_ prefix followed
// by the hexadecimal representation of the silicon unique ID of the CPU
#define USB_STRING_SERIAL_NUMBER L"NANO_xxxxxxxxxxx"
/////////////////////////////////////////////////////////////////////////
#define INDEX_OF_WCHAR_FOR_UNIQUE_ID 5
// structure for USB serial number descriptor with Unicode string
typedef struct usb_string_serial_number
{
uint8_t bLength;
uint8_t bDescriptorType;
wchar_t bPropertyData[sizeof(USB_STRING_SERIAL_NUMBER)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec)
}usb_string_serial_number;
/*
* USB Device Descriptor.
*/
static const uint8_t vcom_device_descriptor_data[] = {
USB_DESC_DEVICE (0x0200, /* bcdUSB (2.0). */
0x02, /* bDeviceClass (CDC). */
0x00, /* bDeviceSubClass. */
0x00, /* bDeviceProtocol. */
0x40, /* bMaxPacketSize. */
0x0483, /* idVendor (ST). */
0x5740, /* idProduct. */
0x0200, /* bcdDevice. */
1, /* iManufacturer. */
2, /* iProduct. */
3, /* iSerialNumber. */
1) /* bNumConfigurations. */
};
/*
* Device Descriptor wrapper.
*/
static const USBDescriptor vcom_device_descriptor = {
sizeof vcom_device_descriptor_data,
vcom_device_descriptor_data
};
/* Configuration Descriptor tree for a CDC.*/
static const uint8_t vcom_configuration_descriptor_data[] = {
/* Configuration Descriptor.*/
USB_DESC_CONFIGURATION(0x0043, /* wTotalLength. */
0x02, /* bNumInterfaces. */
0x01, /* bConfigurationValue. */
0, /* iConfiguration. */
0xC0, /* bmAttributes (self powered). */
50), /* bMaxPower (100mA). */
/* Interface Descriptor.*/
USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */
0x00, /* bAlternateSetting. */
0x01, /* bNumEndpoints. */
0x02, /* bInterfaceClass (Communications
Interface Class, CDC section
4.2). */
0x02, /* bInterfaceSubClass (Abstract
Control Model, CDC section 4.3). */
0x01, /* bInterfaceProtocol (AT commands,
CDC section 4.4). */
0), /* iInterface. */
/* Header Functional Descriptor (CDC section 5.2.3).*/
USB_DESC_BYTE (5), /* bLength. */
USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header
Functional Descriptor. */
USB_DESC_BCD (0x0110), /* bcdCDC. */
/* Call Management Functional Descriptor. */
USB_DESC_BYTE (5), /* bFunctionLength. */
USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management
Functional Descriptor). */
USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */
USB_DESC_BYTE (0x01), /* bDataInterface. */
/* ACM Functional Descriptor.*/
USB_DESC_BYTE (4), /* bFunctionLength. */
USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract
Control Management Descriptor). */
USB_DESC_BYTE (0x02), /* bmCapabilities. */
/* Union Functional Descriptor.*/
USB_DESC_BYTE (5), /* bFunctionLength. */
USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union
Functional Descriptor). */
USB_DESC_BYTE (0x00), /* bMasterInterface (Communication
Class Interface). */
USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class
Interface). */
/* Endpoint 2 Descriptor.*/
USB_DESC_ENDPOINT (USBD2_INTERRUPT_REQUEST_EP|0x80,
0x03, /* bmAttributes (Interrupt). */
0x0008, /* wMaxPacketSize. */
0xFF), /* bInterval. */
/* Interface Descriptor.*/
USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */
0x00, /* bAlternateSetting. */
0x02, /* bNumEndpoints. */
0x0A, /* bInterfaceClass (Data Class
Interface, CDC section 4.5). */
0x00, /* bInterfaceSubClass (CDC section
4.6). */
0x00, /* bInterfaceProtocol (CDC section
4.7). */
0x00), /* iInterface. */
/* Endpoint 3 Descriptor.*/
USB_DESC_ENDPOINT (USBD2_DATA_AVAILABLE_EP, /* bEndpointAddress.*/
0x02, /* bmAttributes (Bulk). */
0x0040, /* wMaxPacketSize. */
0x00), /* bInterval. */
/* Endpoint 1 Descriptor.*/
USB_DESC_ENDPOINT (USBD2_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/
0x02, /* bmAttributes (Bulk). */
0x0040, /* wMaxPacketSize. */
0x00) /* bInterval. */
};
/*
* Configuration Descriptor wrapper.
*/
static const USBDescriptor vcom_configuration_descriptor = {
sizeof vcom_configuration_descriptor_data,
vcom_configuration_descriptor_data
};
/*
* U.S. English language identifier.
*/
static const uint8_t vcom_string0[] = {
USB_DESC_BYTE(4), /* bLength. */
USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */
};
// Vendor string
static const usb_string_vendor usb_vendor = {
sizeof(usb_vendor),
USB_DESC_BYTE(USB_DESCRIPTOR_STRING),
USB_STRING_VENDOR
};
// Device Description string
static const usb_string_device_description usb_device_description = {
sizeof(usb_device_description),
USB_DESC_BYTE(USB_DESCRIPTOR_STRING),
USB_STRING_DEVICE_DESCRIPTION
};
// Serial Number string.
static usb_string_serial_number usb_serial_number = {
sizeof(usb_serial_number),
USB_DESC_BYTE(USB_DESCRIPTOR_STRING),
USB_STRING_SERIAL_NUMBER
};
/*
* Strings wrappers array.
*/
static const USBDescriptor vcom_strings[] = {
{sizeof vcom_string0, vcom_string0},
{sizeof usb_vendor, (uint8_t*)(&usb_vendor)},
{sizeof usb_device_description, (uint8_t*)(&usb_device_description)},
{sizeof usb_serial_number, (uint8_t*)(&usb_serial_number)},
};
// Convert Hex 32Bits value into char
// value: value to convert
// pbuf: pointer to the buffer
// len: buffer length
void IntToUnicode(uint32_t value , uint8_t *pbuf, uint8_t len)
{
uint8_t idx = 0;
for( idx = 0; idx < len; idx ++)
{
if( ((value >> 28)) < 0xA )
{
pbuf[ 2* idx] = (value >> 28) + '0';
}
else
{
pbuf[2* idx] = (value >> 28) + 'A' - 10;
}
value = value << 4;
pbuf[ 2* idx + 1] = 0;
}
}
// Create the serial number string descriptor
void Get_SerialNum(uint8_t* pbuf)
{
uint32_t deviceserial0, deviceserial1, deviceserial2;
deviceserial0 = *(uint32_t*)DEVICE_ID1;
deviceserial1 = *(uint32_t*)DEVICE_ID2;
deviceserial2 = *(uint32_t*)DEVICE_ID3;
deviceserial0 += deviceserial2;
if (deviceserial0 != 0)
{
IntToUnicode(deviceserial0, pbuf, 8);
pbuf += 16;
IntToUnicode(deviceserial1, pbuf, 4);
}
}
/*
* Handles the GET_DESCRIPTOR callback. All required descriptors must be
* handled here.
*/
static const USBDescriptor *get_descriptor(USBDriver *usbp,
uint8_t dtype,
uint8_t dindex,
uint16_t lang) {
(void)usbp;
(void)lang;
switch (dtype) {
case USB_DESCRIPTOR_DEVICE:
return &vcom_device_descriptor;
case USB_DESCRIPTOR_CONFIGURATION:
return &vcom_configuration_descriptor;
case USB_DESCRIPTOR_STRING:
if (dindex < 4)
{
if(dindex == 3)
{
// request is for serial number
// get it from the silicon unique ID
Get_SerialNum((uint8_t*)&usb_serial_number.bPropertyData[INDEX_OF_WCHAR_FOR_UNIQUE_ID]);
}
return &vcom_strings[dindex];
}
}
return NULL;
}
/**
* @brief IN EP1 state.
*/
static USBInEndpointState ep1instate;
/**
* @brief OUT EP1 state.
*/
static USBOutEndpointState ep1outstate;
/**
* @brief EP1 initialization structure (both IN and OUT).
*/
static const USBEndpointConfig ep1config = {
USB_EP_MODE_TYPE_BULK,
NULL,
sduDataTransmitted,
sduDataReceived,
0x0040,
0x0040,
&ep1instate,
&ep1outstate,
2,
NULL
};
/**
* @brief IN EP2 state.
*/
static USBInEndpointState ep2instate;
/**
* @brief EP2 initialization structure (IN only).
*/
static const USBEndpointConfig ep2config = {
USB_EP_MODE_TYPE_INTR,
NULL,
sduInterruptTransmitted,
NULL,
0x0010,
0x0000,
&ep2instate,
NULL,
1,
NULL
};
/*
* Handles the USB driver global events.
*/
static void usb_event(USBDriver *usbp, usbevent_t event) {
extern SerialUSBDriver SDU1;
switch (event) {
case USB_EVENT_ADDRESS:
return;
case USB_EVENT_CONFIGURED:
chSysLockFromISR();
if (usbp->state == USB_ACTIVE) {
/* Enables the endpoints specified into the configuration.
Note, this callback is invoked from an ISR so I-Class functions
must be used.*/
usbInitEndpointI(usbp, USBD2_DATA_REQUEST_EP, &ep1config);
usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config);
/* Resetting the state of the CDC subsystem.*/
sduConfigureHookI(&SDU1);
}
else if (usbp->state == USB_SELECTED) {
usbDisableEndpointsI(usbp);
}
chSysUnlockFromISR();
return;
case USB_EVENT_RESET:
/* Falls into.*/
case USB_EVENT_UNCONFIGURED:
/* Falls into.*/
case USB_EVENT_SUSPEND:
chSysLockFromISR();
/* Disconnection event on suspend.*/
sduSuspendHookI(&SDU1);
chSysUnlockFromISR();
return;
case USB_EVENT_WAKEUP:
chSysLockFromISR();
/* Disconnection event on suspend.*/
sduWakeupHookI(&SDU1);
chSysUnlockFromISR();
return;
case USB_EVENT_STALLED:
return;
}
return;
}
/*
* Handling messages not implemented in the default handler nor in the
* SerialUSB handler.
*/
static bool requests_hook(USBDriver *usbp) {
if (((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE) &&
(usbp->setup[1] == USB_REQ_SET_INTERFACE)) {
usbSetupTransfer(usbp, NULL, 0, NULL);
return true;
}
return sduRequestsHook(usbp);
}
/*
* Handles the USB driver global events.
*/
static void sof_handler(USBDriver *usbp) {
(void)usbp;
osalSysLockFromISR();
sduSOFHookI(&SDU1);
osalSysUnlockFromISR();
}
/*
* USB driver configuration.
*/
const USBConfig usbcfg = {
usb_event,
get_descriptor,
requests_hook,
sof_handler
};
/*
* Serial over USB driver configuration.
*/
const SerialUSBConfig serusbcfg = {
&USBD1,
USBD2_DATA_REQUEST_EP,
USBD2_DATA_AVAILABLE_EP,
USBD2_INTERRUPT_REQUEST_EP
};

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//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.
// See LICENSE file in the project root for full license information.
//
#ifndef USBCFG_H
#define USBCFG_H
extern const USBConfig usbcfg;
extern SerialUSBConfig serusbcfg;
extern SerialUSBDriver SDU1;
#endif /* USBCFG_H */
/** @} */

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/* CHIBIOS FIX */
#include "ch.h"
/*---------------------------------------------------------------------------/
/ FatFs Functional Configurations
/---------------------------------------------------------------------------*/
#define FFCONF_DEF 86606 /* Revision ID */
/*---------------------------------------------------------------------------/
/ Function Configurations
/---------------------------------------------------------------------------*/
#define FF_FS_READONLY 0
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
/ and optional writing functions as well. */
#define FF_FS_MINIMIZE 0
/* This option defines minimization level to remove some basic API functions.
/
/ 0: Basic functions are fully enabled.
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
/ are removed.
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
/ 3: f_lseek() function is removed in addition to 2. */
#define FF_USE_STRFUNC 1
/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
/
/ 0: Disable string functions.
/ 1: Enable without LF-CRLF conversion.
/ 2: Enable with LF-CRLF conversion. */
#define FF_USE_FIND 1
/* This option switches filtered directory read functions, f_findfirst() and
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
#define FF_USE_MKFS 0
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
#define FF_USE_FASTSEEK 0
/* This option switches fast seek function. (0:Disable or 1:Enable) */
#define FF_USE_EXPAND 0
/* This option switches f_expand function. (0:Disable or 1:Enable) */
#define FF_USE_CHMOD 0
/* This option switches attribute manipulation functions, f_chmod() and f_utime().
/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
#define FF_USE_LABEL 1
/* This option switches volume label functions, f_getlabel() and f_setlabel().
/ (0:Disable or 1:Enable) */
#define FF_USE_FORWARD 0
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
/*---------------------------------------------------------------------------/
/ Locale and Namespace Configurations
/---------------------------------------------------------------------------*/
#define FF_CODE_PAGE 850
/* This option specifies the OEM code page to be used on the target system.
/ Incorrect code page setting can cause a file open failure.
/
/ 437 - U.S.
/ 720 - Arabic
/ 737 - Greek
/ 771 - KBL
/ 775 - Baltic
/ 850 - Latin 1
/ 852 - Latin 2
/ 855 - Cyrillic
/ 857 - Turkish
/ 860 - Portuguese
/ 861 - Icelandic
/ 862 - Hebrew
/ 863 - Canadian French
/ 864 - Arabic
/ 865 - Nordic
/ 866 - Russian
/ 869 - Greek 2
/ 932 - Japanese (DBCS)
/ 936 - Simplified Chinese (DBCS)
/ 949 - Korean (DBCS)
/ 950 - Traditional Chinese (DBCS)
/ 0 - Include all code pages above and configured by f_setcp()
*/
#define FF_USE_LFN 3
#define FF_MAX_LFN 255
/* The FF_USE_LFN switches the support for LFN (long file name).
/
/ 0: Disable LFN. FF_MAX_LFN has no effect.
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
/ 2: Enable LFN with dynamic working buffer on the STACK.
/ 3: Enable LFN with dynamic working buffer on the HEAP.
/
/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
/ be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN
/ specification.
/ When use stack for the working buffer, take care on stack overflow. When use heap
/ memory for the working buffer, memory management functions, ff_memalloc() and
/ ff_memfree() exemplified in ffsystem.c, need to be added to the project. */
#define FF_LFN_UNICODE 0
/* This option switches the character encoding on the API when LFN is enabled.
/
/ 0: ANSI/OEM in current CP (TCHAR = char)
/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
/ 2: Unicode in UTF-8 (TCHAR = char)
/ 3: Unicode in UTF-32 (TCHAR = DWORD)
/
/ Also behavior of string I/O functions will be affected by this option.
/ When LFN is not enabled, this option has no effect. */
#define FF_LFN_BUF 255
#define FF_SFN_BUF 12
/* This set of options defines size of file name members in the FILINFO structure
/ which is used to read out directory items. These values should be suffcient for
/ the file names to read. The maximum possible length of the read file name depends
/ on character encoding. When LFN is not enabled, these options have no effect. */
#define FF_STRF_ENCODE 3
/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
/ f_putc(), f_puts and f_printf() convert the character encoding in it.
/ This option selects assumption of character encoding ON THE FILE to be
/ read/written via those functions.
/
/ 0: ANSI/OEM in current CP
/ 1: Unicode in UTF-16LE
/ 2: Unicode in UTF-16BE
/ 3: Unicode in UTF-8
*/
#define FF_FS_RPATH 2
/* This option configures support for relative path.
/
/ 0: Disable relative path and remove related functions.
/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
/ 2: f_getcwd() function is available in addition to 1.
*/
/*---------------------------------------------------------------------------/
/ Drive/Volume Configurations
/---------------------------------------------------------------------------*/
#define FF_VOLUMES 3
/* Number of volumes (logical drives) to be used. (1-10) */
#define FF_STR_VOLUME_ID 1
#define FF_VOLUME_STRS "D","E","F"
/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
/ not defined, a user defined volume string table needs to be defined as:
/
/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
*/
#define FF_MULTI_PARTITION 0
/* This option switches support for multiple volumes on the physical drive.
/ By default (0), each logical drive number is bound to the same physical drive
/ number and only an FAT volume found on the physical drive will be mounted.
/ When this function is enabled (1), each logical drive number can be bound to
/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
/ funciton will be available. */
#define FF_MIN_SS 512
#define FF_MAX_SS 512
/* This set of options configures the range of sector size to be supported. (512,
/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
/ harddisk. But a larger value may be required for on-board flash memory and some
/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
/ for variable sector size mode and disk_ioctl() function needs to implement
/ GET_SECTOR_SIZE command. */
#define FF_LBA64 0
/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable)
/ To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */
#define FF_MIN_GPT 0x100000000
/* Minimum number of sectors to switch GPT format to create partition in f_mkfs and
/ f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */
#define FF_USE_TRIM 0
/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
/ To enable Trim function, also CTRL_TRIM command should be implemented to the
/ disk_ioctl() function. */
/*---------------------------------------------------------------------------/
/ System Configurations
/---------------------------------------------------------------------------*/
#define FF_FS_TINY 0
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
/ Instead of private sector buffer eliminated from the file object, common sector
/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
#define FF_FS_EXFAT 0
/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
#define FF_FS_NORTC 1
#define FF_NORTC_MON 1
#define FF_NORTC_MDAY 1
#define FF_NORTC_YEAR 2020
/* The option FF_FS_NORTC switches timestamp function. If the system does not have
/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
/ added to the project to read current time form real-time clock. FF_NORTC_MON,
/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
/ These options have no effect in read-only configuration (FF_FS_READONLY = 1). */
#define FF_FS_NOFSINFO 0
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
/ option, and f_getfree() function at first time after volume mount will force
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
/
/ bit0=0: Use free cluster count in the FSINFO if available.
/ bit0=1: Do not trust free cluster count in the FSINFO.
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
*/
#define FF_FS_LOCK 0
/* The option FF_FS_LOCK switches file lock function to control duplicated file open
/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
/ is 1.
/
/ 0: Disable file lock function. To avoid volume corruption, application program
/ should avoid illegal open, remove and rename to the open objects.
/ >0: Enable file lock function. The value defines how many files/sub-directories
/ can be opened simultaneously under file lock control. Note that the file
/ lock control is independent of re-entrancy. */
#define FF_FS_REENTRANT 1
#define FF_FS_TIMEOUT TIME_MS2I(1000)
#define FF_SYNC_t semaphore_t*
/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
/ module itself. Note that regardless of this option, file access to different
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
/ and f_fdisk() function, are always not re-entrant. Only file/directory access
/ to the same volume is under control of this function.
/
/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
/ function, must be added to the project. Samples are available in
/ option/syscall.c.
/
/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
/ included somewhere in the scope of ff.h. */
/*--- End of configuration options ---*/

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{
"version": "0.2.0",
"configurations": [
{
"name": "NETDUINO3_WIFI nanoBooter",
"type": "cppdbg",
"request": "launch",
"miDebuggerPath": "<absolute-path-to-the-toolchain-folder-mind-the-forward-slashes>/bin/arm-none-eabi-gdb.exe",
"targetArchitecture": "ARM",
"program": "${workspaceRoot}/build/nanoBooter.elf",
"setupCommands": [
{
"text": "target extended-remote localhost:3333"
},
{
"text": "monitor reset_config none separate"
},
{
"text": "monitor reset halt"
},
{
"text": "monitor flash write_image erase \"<path-to-the-repo-root-mind-the-forward-slash>/build/nanoBooter.hex\" "
},
{
"text": "file <path-to-the-repo-root-mind-the-forward-slash>/build/nanoBooter.elf"
},
{
"text": "monitor reset halt"
},
{
"text": "set output-radix 16",
"description": "set the default numeric base to 16",
"ignoreFailures": false
}
],
"customLaunchSetupCommands": [
{
"text": "monitor reset_config none separate"
},
{
"text": "monitor reset halt"
}
],
"logging": {
"moduleLoad": false,
"trace": false,
"engineLogging": false,
"programOutput": true,
"exceptions": true
},
"launchCompleteCommand": "exec-continue",
"debugServerPath": "<absolute-path-to-openocd-mind-the-forward-slashes>/bin/openocd.exe",
"debugServerArgs": "-s \"<absolute-path-to-openocd-mind-the-forward-slashes>/scripts/\" -f board/stm32f4discovery.cfg",
"serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware",
"filterStderr": true,
"externalConsole": true,
"cwd": "${cwd}"
},
{
"name": "NETDUINO3_WIFI nanoCLR",
"type": "cppdbg",
"request": "launch",
"miDebuggerPath": "<absolute-path-to-the-toolchain-folder-mind-the-forward-slashes>/bin/arm-none-eabi-gdb.exe",
"targetArchitecture": "ARM",
"program": "${workspaceRoot}/build/nanoCLR.elf",
"setupCommands": [
{
"text": "target extended-remote localhost:3333"
},
{
"text": "monitor reset_config none separate"
},
{
"text": "monitor reset halt"
},
{
"text": "monitor flash write_image erase \"<path-to-the-repo-root-mind-the-forward-slash>/build/nanoCLR.hex\" "
},
{
"text": "file <path-to-the-repo-root-mind-the-forward-slash>/build/nanoCLR.elf"
},
{
"text": "monitor reset halt"
},
{
"text": "set output-radix 16",
"description": "set the default numeric base to 16",
"ignoreFailures": false
}
],
"customLaunchSetupCommands": [
{
"text": "monitor reset_config none separate"
},
{
"text": "monitor reset halt"
}
],
"logging": {
"moduleLoad": false,
"trace": false,
"engineLogging": false,
"programOutput": true,
"exceptions": true
},
"launchCompleteCommand": "exec-continue",
"debugServerPath": "<absolute-path-to-openocd-mind-the-forward-slashes>/bin/openocd.exe",
"debugServerArgs": "-s \"<absolute-path-to-openocd-mind-the-forward-slashes>/scripts/\" -f board/stm32429i_eval_stlink.cfg",
"serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware",
"filterStderr": true,
"externalConsole": true,
"cwd": "${cwd}"
}
]
}

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#
# Copyright (c) .NET Foundation and Contributors
# See LICENSE file in the project root for full license information.
#
# # append nanoBooter source files
list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c")
# make var global
set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global")

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//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.
// See LICENSE file in the project root for full license information.
//
/**
* @file rt/templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef CHCONF_H
#define CHCONF_H
#define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_6_1_
/*===========================================================================*/
/**
* @name System timers settings
* @{
*/
/*===========================================================================*/
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32
#endif
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_CFG_ST_FREQUENCY)
#define CH_CFG_ST_FREQUENCY 10000 // this is 1 millisecond
#endif
/**
* @brief Time intervals data size.
* @note Allowed values are 16, 32 or 64 bits.
*/
#if !defined(CH_CFG_INTERVALS_SIZE)
#define CH_CFG_INTERVALS_SIZE 32
#endif
/**
* @brief Time types data size.
* @note Allowed values are 16 or 32 bits.
*/
#if !defined(CH_CFG_TIME_TYPES_SIZE)
#define CH_CFG_TIME_TYPES_SIZE 32
#endif
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#if !defined(CH_CFG_ST_TIMEDELTA)
#define CH_CFG_ST_TIMEDELTA 2
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/
#if !defined(CH_CFG_TIME_QUANTUM)
#define CH_CFG_TIME_QUANTUM 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread. The application @p main()
* function becomes the idle thread and must implement an
* infinite loop.
*/
#if !defined(CH_CFG_NO_IDLE_THREAD)
#define CH_CFG_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_OPTIMIZE_SPEED)
#define CH_CFG_OPTIMIZE_SPEED FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Time Measurement APIs.
* @details If enabled then the time measurement APIs are included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_TM)
#define CH_CFG_USE_TM FALSE
#endif
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_REGISTRY)
#define CH_CFG_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_WAITEXIT)
#define CH_CFG_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_SEMAPHORES)
#define CH_CFG_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MUTEXES)
#define CH_CFG_USE_MUTEXES FALSE
#endif
/**
* @brief Enables recursive behavior on mutexes.
* @note Recursive mutexes are heavier and have an increased
* memory footprint.
*
* @note The default is @p FALSE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#if !defined(CH_CFG_USE_CONDVARS)
#define CH_CFG_USE_CONDVARS FALSE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_CONDVARS.
*/
#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_EVENTS)
#define CH_CFG_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_EVENTS.
*/
#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MESSAGES)
#define CH_CFG_USE_MESSAGES FALSE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/
#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
#if !defined(CH_CFG_USE_DYNAMIC)
#define CH_CFG_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name OSLIB options
* @{
*/
/*===========================================================================*/
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_MAILBOXES)
#define CH_CFG_USE_MAILBOXES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMCORE)
#define CH_CFG_USE_MEMCORE TRUE
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#if !defined(CH_CFG_MEMCORE_SIZE)
#define CH_CFG_MEMCORE_SIZE 0
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
* @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_CFG_USE_HEAP)
#define CH_CFG_USE_HEAP TRUE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMPOOLS)
#define CH_CFG_USE_MEMPOOLS TRUE
#endif
/**
* @brief Objects FIFOs APIs.
* @details If enabled then the objects FIFOs APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_FIFOS)
#define CH_CFG_USE_OBJ_FIFOS TRUE
#endif
/**
* @brief Pipes APIs.
* @details If enabled then the pipes APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES TRUE
#endif
/**
* @brief Objects Caches APIs.
* @details If enabled then the objects caches APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_CACHES)
#define CH_CFG_USE_OBJ_CACHES FALSE
#endif
/**
* @brief Delegate threads APIs.
* @details If enabled then the delegate threads APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_DELEGATES)
#define CH_CFG_USE_DELEGATES FALSE
#endif
/**
* @brief Jobs Queues APIs.
* @details If enabled then the jobs queues APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_JOBS)
#define CH_CFG_USE_JOBS FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Objects factory options
* @{
*/
/*===========================================================================*/
/**
* @brief Objects Factory APIs.
* @details If enabled then the objects factory APIs are included in the
* kernel.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_CFG_USE_FACTORY)
#define CH_CFG_USE_FACTORY FALSE
#endif
/**
* @brief Maximum length for object names.
* @details If the specified length is zero then the name is stored by
* pointer but this could have unintended side effects.
*/
#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
#endif
/**
* @brief Enables the registry of generic objects.
*/
#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
#endif
/**
* @brief Enables factory for generic buffers.
*/
#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
#endif
/**
* @brief Enables factory for semaphores.
*/
#if !defined(CH_CFG_FACTORY_SEMAPHORES)
#define CH_CFG_FACTORY_SEMAPHORES TRUE
#endif
/**
* @brief Enables factory for mailboxes.
*/
#if !defined(CH_CFG_FACTORY_MAILBOXES)
#define CH_CFG_FACTORY_MAILBOXES TRUE
#endif
/**
* @brief Enables factory for objects FIFOs.
*/
#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
#endif
/**
* @brief Enables factory for Pipes.
*/
#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)
#define CH_CFG_FACTORY_PIPES TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_STATISTICS)
#define CH_DBG_STATISTICS FALSE
#endif
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the trace buffer is activated.
*
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
*/
#if !defined(CH_DBG_TRACE_MASK)
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
#endif
/**
* @brief Trace buffer entries.
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
* different from @p CH_DBG_TRACE_MASK_DISABLED.
*/
#if !defined(CH_DBG_TRACE_BUFFER_SIZE)
#define CH_DBG_TRACE_BUFFER_SIZE 128
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p FALSE.
* @note This debug option is not currently compatible with the
* tickless mode.
*/
#if !defined(CH_DBG_THREADS_PROFILING)
#define CH_DBG_THREADS_PROFILING FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief System structure extension.
* @details User fields added to the end of the @p ch_system_t structure.
*/
#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add threads custom fields here.*/
/**
* @brief System initialization hook.
* @details User initialization code added to the @p chSysInit() function
* just before interrupts are enabled globally.
*/
#define CH_CFG_SYSTEM_INIT_HOOK() \
{ \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p _thread_init() function.
*
* @note It is invoked from within @p _thread_init() and implicitly from all
* the threads creation APIs.
*/
#define CH_CFG_THREAD_INIT_HOOK(tp) \
{ \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) \
{ \
/* Add threads finalization code here.*/ \
}
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \
{ \
/* Context switch code here.*/ \
}
/**
* @brief ISR enter hook.
*/
#define CH_CFG_IRQ_PROLOGUE_HOOK() \
{ \
/* IRQ prologue code here.*/ \
}
/**
* @brief ISR exit hook.
*/
#define CH_CFG_IRQ_EPILOGUE_HOOK() \
{ \
/* IRQ epilogue code here.*/ \
}
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() \
{ \
/* Idle-enter code here.*/ \
}
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() \
{ \
/* Idle-leave code here.*/ \
}
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#define CH_CFG_IDLE_LOOP_HOOK() \
{ \
/* Idle loop code here.*/ \
}
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#define CH_CFG_SYSTEM_TICK_HOOK() \
{ \
/* System tick event code here.*/ \
}
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#define CH_CFG_SYSTEM_HALT_HOOK(reason) \
{ \
/* System halt code here.*/ \
}
/**
* @brief Trace hook.
* @details This hook is invoked each time a new record is written in the
* trace buffer.
*/
#define CH_CFG_TRACE_HOOK(tep) \
{ \
/* Trace code here.*/ \
}
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* CHCONF_H */
/** @} */

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//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.
// See LICENSE file in the project root for full license information.
//
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the cryptographic subsystem.
*/
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the EFlash subsystem.
*/
#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
#define HAL_USE_EFL FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB TRUE
#endif
/**
* @brief Enables the SIO subsystem.
*/
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the TRNG subsystem.
*/
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB TRUE
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS FALSE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS FALSE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the SW fall-back of the cryptographic driver.
* @details When enabled, this option, activates a fall-back software
* implementation for algorithms not supported by the underlying
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the zero-copy API.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 921600
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 64
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 1
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
// header for nanoFramework overlay
#include "halconf_nf.h"
#endif /* HALCONF_H */
/** @} */

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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#ifndef _HALCONF_NF_H_
#define _HALCONF_NF_H_
// enables STM32 Flash driver
#if !defined(HAL_NF_USE_STM32_FLASH)
#define HAL_NF_USE_STM32_FLASH TRUE
#endif
#endif // _HALCONF_NF_H_

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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#include <ch.h>
#include <hal.h>
#include <hal_nf_community.h>
#include <cmsis_os.h>
#include <usbcfg.h>
#include <targetHAL.h>
#include <WireProtocol_ReceiverThread.h>
#include <nanoPAL_BlockStorage.h>
#include <LaunchCLR.h>
// need to declare the Receiver thread here
osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread");
// Application entry point.
int main(void)
{
// HAL initialization, this also initializes the configured device drivers
// and performs the board-specific initializations.
halInit();
// init boot clipboard
InitBootClipboard();
// check if there is a request to remain on nanoBooter
if (!IsToRemainInBooter())
{
// check for valid CLR image at address contiguous to nanoBooter
// this target DOES NOT have configuration block, so we need to use the __nanoImage_end__ address here
if (CheckValidCLRImage((uint32_t)&__nanoImage_end__))
{
// there seems to be a valid CLR image
// launch nanoCLR
LaunchCLR((uint32_t)&__nanoImage_end__);
}
}
// The kernel is initialized but not started yet, this means that
// main() is executing with absolute priority but interrupts are already enabled.
osKernelInitialize();
#if (HAL_NF_USE_STM32_CRC == TRUE)
// startup crc
crcStart(NULL);
#endif
// Initializes a serial-over-USB CDC driver.
sduObjectInit(&SDU1);
sduStart(&SDU1, &serusbcfg);
// Activates the USB driver and then the USB bus pull-up on D+.
// Note, a delay is inserted in order to not have to disconnect the cable after a reset.
usbDisconnectBus(serusbcfg.usbp);
chThdSleepMilliseconds(100);
usbStart(serusbcfg.usbp, &usbcfg);
usbConnectBus(serusbcfg.usbp);
// create the receiver thread
osThreadCreate(osThread(ReceiverThread), NULL);
// start kernel, after this main() will behave like a thread with priority osPriorityNormal
osKernelStart();
// initialize block storage list and devices
// in CLR this is called in nanoHAL_Initialize()
// for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command
BlockStorageList_Initialize();
BlockStorage_AddDevices();
// report successfull nanoBooter execution
ReportSuccessfullNanoBooter();
// Normal main() thread
while (true)
{
palSetPad(GPIOE, GPIOE_LED1);
osDelay(500);
palClearPad(GPIOE, GPIOE_LED1);
osDelay(500);
}
}

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/*
//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.
// See LICENSE file in the project root for full license information.
//
*/
/*
* STM32F427Vx memory setup.
* Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
*/
MEMORY
{
flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08007FFF)*/
config : org = 0x00000000, len = 0 /* space reserved for configuration block */
deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */
ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */
ram0 : org = 0x20000030, len = 192k-48 /* SRAM1 + SRAM2 + SRAM3 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
ram3 : org = 0x20020000, len = 64k /* SRAM3 */
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0
bootclpbrd : org = 0x20000000, len = 48 /* boot clipboard area */
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash);
REGION_ALIAS("VECTORS_FLASH_LMA", flash);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash);
REGION_ALIAS("XTORS_FLASH_LMA", flash);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash);
REGION_ALIAS("TEXT_FLASH_LMA", flash);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash);
REGION_ALIAS("RODATA_FLASH_LMA", flash);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram4);
/* RAM region to be used for the boot clipboard.*/
REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd);
/* Stacks rules inclusion.*/
INCLUDE rules_stacks.ld
/* Code rules inclusion.*/
INCLUDE rules_code.ld
/* Data rules inclusion.*/
INCLUDE rules_data.ld
/* Data rules inclusion.*/
INCLUDE rules_memory.ld

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/*
//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.
// See LICENSE file in the project root for full license information.
//
*/
/*
* STM32F427Vx memory setup.
* Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
*/
MEMORY
{
flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08003FFF)*/
config : org = 0x00000000, len = 0 /* space reserved for configuration block */
deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */
ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */
ram0 : org = 0x20000030, len = 192k-48 /* SRAM1 + SRAM2 + SRAM3 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
ram3 : org = 0x20020000, len = 64k /* SRAM3 */
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0
bootclpbrd : org = 0x20000000, len = 48 /* boot clipboard area */
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash);
REGION_ALIAS("VECTORS_FLASH_LMA", flash);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash);
REGION_ALIAS("XTORS_FLASH_LMA", flash);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash);
REGION_ALIAS("TEXT_FLASH_LMA", flash);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash);
REGION_ALIAS("RODATA_FLASH_LMA", flash);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram4);
/* RAM region to be used for the boot clipboard.*/
REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd);
/* Stacks rules inclusion.*/
INCLUDE rules_stacks.ld
/* Code rules inclusion.*/
INCLUDE rules_code.ld
/* Data rules inclusion.*/
INCLUDE rules_data.ld
/* Data rules inclusion.*/
INCLUDE rules_memory.ld

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//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.
// See LICENSE file in the project root for full license information.
//
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 6
#define STM32_PLLN_VALUE 168
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSE
#define STM32_RTCPRE_VALUE 2
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 2
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
/*
* SDC driver system settings.
*/
#define STM32_SDC_SDIO_DMA_PRIORITY 3
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
#define STM32_SDC_WRITE_TIMEOUT_MS 250
#define STM32_SDC_READ_TIMEOUT_MS 25
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 TRUE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
// header for nanoFramework overlay drivers
#include "mcuconf_nf.h"
#endif /* MCUCONF_H */

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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#ifndef _MCUCONF_NF_H_
#define _MCUCONF_NF_H_
#endif // _MCUCONF_NF_H_

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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
//////////////////////////////////////////////////////////////////////////////
// This file was automatically generated by a tool. //
// Any changes you make here will be overwritten when it's generated again. //
//////////////////////////////////////////////////////////////////////////////
#ifndef _TARGET_BOARD_NANOBOOTER_H_
#define _TARGET_BOARD_NANOBOOTER_H_
#include <target_common.h>
#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_BOARD@"
#endif /* _TARGET_BOARD_NANOBOOTER_H_ */

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#
# Copyright (c) .NET Foundation and Contributors
# See LICENSE file in the project root for full license information.
#
# append nanoCLR source files
list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c")
list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp")
# make var global
set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global")

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//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.
// See LICENSE file in the project root for full license information.
//
/**
* @file rt/templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef CHCONF_H
#define CHCONF_H
#define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_6_1_
/*===========================================================================*/
/**
* @name System timers settings
* @{
*/
/*===========================================================================*/
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32
#endif
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_CFG_ST_FREQUENCY)
#define CH_CFG_ST_FREQUENCY 10000 // this is 1 millisecond
#endif
/**
* @brief Time intervals data size.
* @note Allowed values are 16, 32 or 64 bits.
*/
#if !defined(CH_CFG_INTERVALS_SIZE)
#define CH_CFG_INTERVALS_SIZE 32
#endif
/**
* @brief Time types data size.
* @note Allowed values are 16 or 32 bits.
*/
#if !defined(CH_CFG_TIME_TYPES_SIZE)
#define CH_CFG_TIME_TYPES_SIZE 32
#endif
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#if !defined(CH_CFG_ST_TIMEDELTA)
#define CH_CFG_ST_TIMEDELTA 2
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/
#if !defined(CH_CFG_TIME_QUANTUM)
#define CH_CFG_TIME_QUANTUM 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread. The application @p main()
* function becomes the idle thread and must implement an
* infinite loop.
*/
#if !defined(CH_CFG_NO_IDLE_THREAD)
#define CH_CFG_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_OPTIMIZE_SPEED)
#define CH_CFG_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Time Measurement APIs.
* @details If enabled then the time measurement APIs are included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_TM)
#define CH_CFG_USE_TM FALSE
#endif
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_REGISTRY)
#define CH_CFG_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_WAITEXIT)
#define CH_CFG_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_SEMAPHORES)
#define CH_CFG_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MUTEXES)
#define CH_CFG_USE_MUTEXES TRUE
#endif
/**
* @brief Enables recursive behavior on mutexes.
* @note Recursive mutexes are heavier and have an increased
* memory footprint.
*
* @note The default is @p FALSE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#if !defined(CH_CFG_USE_CONDVARS)
#define CH_CFG_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_CONDVARS.
*/
#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_EVENTS)
#define CH_CFG_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_EVENTS.
*/
#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MESSAGES)
#define CH_CFG_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/
#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
#if !defined(CH_CFG_USE_DYNAMIC)
#define CH_CFG_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name OSLIB options
* @{
*/
/*===========================================================================*/
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_MAILBOXES)
#define CH_CFG_USE_MAILBOXES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMCORE)
#define CH_CFG_USE_MEMCORE TRUE
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#if !defined(CH_CFG_MEMCORE_SIZE)
#define CH_CFG_MEMCORE_SIZE 0
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
* @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_CFG_USE_HEAP)
#define CH_CFG_USE_HEAP TRUE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMPOOLS)
#define CH_CFG_USE_MEMPOOLS TRUE
#endif
/**
* @brief Objects FIFOs APIs.
* @details If enabled then the objects FIFOs APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_FIFOS)
#define CH_CFG_USE_OBJ_FIFOS TRUE
#endif
/**
* @brief Pipes APIs.
* @details If enabled then the pipes APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES TRUE
#endif
/**
* @brief Objects Caches APIs.
* @details If enabled then the objects caches APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_CACHES)
#define CH_CFG_USE_OBJ_CACHES FALSE
#endif
/**
* @brief Delegate threads APIs.
* @details If enabled then the delegate threads APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_DELEGATES)
#define CH_CFG_USE_DELEGATES FALSE
#endif
/**
* @brief Jobs Queues APIs.
* @details If enabled then the jobs queues APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_JOBS)
#define CH_CFG_USE_JOBS FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Objects factory options
* @{
*/
/*===========================================================================*/
/**
* @brief Objects Factory APIs.
* @details If enabled then the objects factory APIs are included in the
* kernel.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_CFG_USE_FACTORY)
#define CH_CFG_USE_FACTORY FALSE
#endif
/**
* @brief Maximum length for object names.
* @details If the specified length is zero then the name is stored by
* pointer but this could have unintended side effects.
*/
#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
#endif
/**
* @brief Enables the registry of generic objects.
*/
#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
#endif
/**
* @brief Enables factory for generic buffers.
*/
#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
#endif
/**
* @brief Enables factory for semaphores.
*/
#if !defined(CH_CFG_FACTORY_SEMAPHORES)
#define CH_CFG_FACTORY_SEMAPHORES TRUE
#endif
/**
* @brief Enables factory for mailboxes.
*/
#if !defined(CH_CFG_FACTORY_MAILBOXES)
#define CH_CFG_FACTORY_MAILBOXES TRUE
#endif
/**
* @brief Enables factory for objects FIFOs.
*/
#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
#endif
/**
* @brief Enables factory for Pipes.
*/
#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)
#define CH_CFG_FACTORY_PIPES TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_STATISTICS)
#define CH_DBG_STATISTICS FALSE
#endif
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the trace buffer is activated.
*
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
*/
#if !defined(CH_DBG_TRACE_MASK)
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
#endif
/**
* @brief Trace buffer entries.
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
* different from @p CH_DBG_TRACE_MASK_DISABLED.
*/
#if !defined(CH_DBG_TRACE_BUFFER_SIZE)
#define CH_DBG_TRACE_BUFFER_SIZE 128
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p FALSE.
* @note This debug option is not currently compatible with the
* tickless mode.
*/
#if !defined(CH_DBG_THREADS_PROFILING)
#define CH_DBG_THREADS_PROFILING FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief System structure extension.
* @details User fields added to the end of the @p ch_system_t structure.
*/
#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add threads custom fields here.*/
/**
* @brief System initialization hook.
* @details User initialization code added to the @p chSysInit() function
* just before interrupts are enabled globally.
*/
#define CH_CFG_SYSTEM_INIT_HOOK() \
{ \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p _thread_init() function.
*
* @note It is invoked from within @p _thread_init() and implicitly from all
* the threads creation APIs.
*/
#define CH_CFG_THREAD_INIT_HOOK(tp) \
{ \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) \
{ \
/* Add threads finalization code here.*/ \
}
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \
{ \
/* Context switch code here.*/ \
}
/**
* @brief ISR enter hook.
*/
#define CH_CFG_IRQ_PROLOGUE_HOOK() \
{ \
/* IRQ prologue code here.*/ \
}
/**
* @brief ISR exit hook.
*/
#define CH_CFG_IRQ_EPILOGUE_HOOK() \
{ \
/* IRQ epilogue code here.*/ \
}
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() \
{ \
/* Idle-enter code here.*/ \
}
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() \
{ \
/* Idle-leave code here.*/ \
}
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#define CH_CFG_IDLE_LOOP_HOOK() \
{ \
/* Idle loop code here.*/ \
}
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#define CH_CFG_SYSTEM_TICK_HOOK() \
{ \
/* System tick event code here.*/ \
}
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#define CH_CFG_SYSTEM_HALT_HOOK(reason) \
{ \
/* System halt code here.*/ \
}
/**
* @brief Trace hook.
* @details This hook is invoked each time a new record is written in the
* trace buffer.
*/
#define CH_CFG_TRACE_HOOK(tep) \
{ \
/* Trace code here.*/ \
}
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* CHCONF_H */
/** @} */

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//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.
// See LICENSE file in the project root for full license information.
//
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
#include <target_platform.h>
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
// this option is set at target_platform.h (from config file)
// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
// #define HAL_USE_ADC TRUE
// #endif
/**
* @brief Enables the CAN subsystem.
*/
// this option is set at target_platform.h (from config file)
// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
// #define HAL_USE_CAN FALSE
// #endif
/**
* @brief Enables the cryptographic subsystem.
*/
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
// /**
// * @brief Enables the DAC subsystem.
// */
// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
// #define HAL_USE_DAC FALSE
// #endif
/**
* @brief Enables the EFlash subsystem.
*/
#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
#define HAL_USE_EFL FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
// this option is set at target_platform.h (from config file)
//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
//#define HAL_USE_I2C TRUE
//#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
// this option is set at target_platform.h (from config file)
// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
// #define HAL_USE_MAC TRUE
// #endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
// this option is set at target_platform.h (from config file)
// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
// #define HAL_USE_PWM TRUE
// #endif
/**
* @brief Enables the RTC subsystem.
*/
// this option is set at target_platform.h (from config file)
// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
// #define HAL_USE_RTC TRUE
// #endif
/**
* @brief Enables the SDC subsystem.
*/
// this option is set at target_platform.h (from config file)
// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
// #define HAL_USE_SDC FALSE
// #endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB TRUE
#endif
/**
* @brief Enables the SIO subsystem.
*/
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
// this option is set at target_platform.h (from config file)
// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
// #define HAL_USE_SPI TRUE
// #endif
/**
* @brief Enables the TRNG subsystem.
*/
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
// this option is set at target_platform.h (from config file)
// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
// #define HAL_USE_UART FALSE
// #endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB TRUE
#endif
/**
* @brief Enables the WDG subsystem.
*/
// this option is set at target_platform.h (from config file)
// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
// #define HAL_USE_WDG FALSE
// #endif
/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS TRUE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS TRUE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the SW fall-back of the cryptographic driver.
* @details When enabled, this option, activates a fall-back software
* implementation for algorithms not supported by the underlying
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the zero-copy API.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 921600
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 64
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 1
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
// header for nanoFramework overlay
#include "halconf_nf.h"
#endif /* HALCONF_H */
/** @} */

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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#ifndef _HALCONF_NF_H_
#define _HALCONF_NF_H_
// enables STM32 Flash driver
#if !defined(HAL_NF_USE_STM32_FLASH)
#define HAL_NF_USE_STM32_FLASH TRUE
#endif
#endif // _HALCONF_NF_H_

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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
// Using Devantech LCD03 display in I2C mode @ address 0xC8
#include <ch.h>
#include <hal.h>
#include <hal_nf_community.h>
#include <cmsis_os.h>
#include "usbcfg.h"
#include <swo.h>
#include <CLR_Startup_Thread.h>
#include <WireProtocol_ReceiverThread.h>
#include <nanoCLR_Application.h>
#include <nanoPAL_BlockStorage.h>
#include <nanoHAL_v2.h>
#include <targetPAL.h>
// need to declare the Receiver thread here
osThreadDef(ReceiverThread, osPriorityHigh, 4096, "ReceiverThread");
// declare CLRStartup thread here
osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread");
#if HAL_USE_SDC
// declare SD Card working thread here
osThreadDef(SdCardWorkingThread, osPriorityNormal, 1024, "SDCWT");
#endif
// Application entry point.
int main(void)
{
// find out wakeup reason
if ((RTC->ISR & RTC_ISR_ALRAF) == RTC_ISR_ALRAF)
{
// standby, match WakeupReason_FromStandby enum
WakeupReasonStore = 1;
}
else if ((PWR->CSR & PWR_CSR_WUF) == PWR_CSR_WUF)
{
// wake from pin, match WakeupReason_FromPin enum
WakeupReasonStore = 2;
}
else
{
// undetermined reason, match WakeupReason_Undetermined enum
WakeupReasonStore = 0;
}
// first things first: need to clear any possible wakeup flags
// if this is not done here the next standby -> wakeup sequence won't work
CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE);
CLEAR_BIT(RTC->ISR, RTC_ISR_ALRAF);
SET_BIT(PWR->CR, PWR_CR_CWUF);
// HAL initialization, this also initializes the configured device drivers
// and performs the board-specific initializations.
halInit();
// init boot clipboard
InitBootClipboard();
// init SWO as soon as possible to make it available to output ASAP
#if (SWO_OUTPUT == TRUE)
SwoInit();
#endif
// The kernel is initialized but not started yet, this means that
// main() is executing with absolute priority but interrupts are already enabled.
osKernelInitialize();
// start watchdog
///////////////////////////////////////////////////////////////////////////////////////////////////////
// for STM32F4 family if watchdog is enabled can't use standby mode because the IWDG can't be stoped //
///////////////////////////////////////////////////////////////////////////////////////////////////////
Watchdog_Init();
#if (HAL_NF_USE_STM32_CRC == TRUE)
// startup crc
crcStart(NULL);
#endif
// Initializes a serial-over-USB CDC driver.
sduObjectInit(&SDU1);
sduStart(&SDU1, &serusbcfg);
// Activates the USB driver and then the USB bus pull-up on D+.
// Note, a delay is inserted in order to not have to disconnect the cable after a reset
usbDisconnectBus(serusbcfg.usbp);
chThdSleepMilliseconds(100);
usbStart(serusbcfg.usbp, &usbcfg);
usbConnectBus(serusbcfg.usbp);
// create the receiver thread
osThreadCreate(osThread(ReceiverThread), NULL);
// CLR settings to launch CLR thread
CLR_SETTINGS clrSettings;
(void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS));
clrSettings.MaxContextSwitches = 50;
clrSettings.WaitForDebugger = false;
clrSettings.EnterDebuggerLoopAfterExit = true;
// create the CLR Startup thread
osThreadCreate(osThread(CLRStartupThread), &clrSettings);
#if HAL_USE_SDC
// creates the SD card working thread
osThreadCreate(osThread(SdCardWorkingThread), NULL);
#endif
// start kernel, after this main() will behave like a thread with priority osPriorityNormal
osKernelStart();
while (true)
{
osDelay(100);
}
}

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/*
//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.
// See LICENSE file in the project root for full license information.
//
*/
/*
* STM32F427Vx memory setup.
* Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
*/
MEMORY
{
flash : org = 0x08008000, len = 2M - 32k - 1408k /* flash size less the space reserved for nanoBooter and application deployment*/
config : org = 0x00000000, len = 0 /* space reserved for configuration block */
deployment : org = 0x080A0000, len = 1408k /* space reserved for application deployment */
ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */
ram0 : org = 0x20000030, len = 192k-48 /* SRAM1 + SRAM2 + SRAM3 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x2001C030, len = 16k /* SRAM2 */
ram3 : org = 0x20020000, len = 64k /* SRAM3 */
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0
bootclpbrd : org = 0x20000000, len = 48 /* boot clipboard area */
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash);
REGION_ALIAS("VECTORS_FLASH_LMA", flash);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash);
REGION_ALIAS("XTORS_FLASH_LMA", flash);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash);
REGION_ALIAS("TEXT_FLASH_LMA", flash);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash);
REGION_ALIAS("RODATA_FLASH_LMA", flash);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram4);
/* RAM region to be used for the nanoFramework CLR managed heap.*/
REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0);
/* RAM region to be used for the boot clipboard.*/
REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd);
INCLUDE rules.ld

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/*
//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.
// See LICENSE file in the project root for full license information.
//
*/
/*
* STM32F427Vx memory setup.
* Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
*/
MEMORY
{
flash : org = 0x08004000, len = 2M - 32k - 1792k /* flash size less the space reserved for nanoBooter and application deployment*/
config : org = 0x00000000, len = 0 /* space reserved for configuration block */
deployment : org = 0x08040000, len = 1792k /* space reserved for application deployment */
ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */
ram0 : org = 0x20000030, len = 192k-48 /* SRAM1 + SRAM2 + SRAM3 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x2001C030, len = 16k /* SRAM2 */
ram3 : org = 0x20020000, len = 64k /* SRAM3 */
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0
bootclpbrd : org = 0x20000000, len = 48 /* boot clipboard area */
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash);
REGION_ALIAS("VECTORS_FLASH_LMA", flash);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash);
REGION_ALIAS("XTORS_FLASH_LMA", flash);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash);
REGION_ALIAS("TEXT_FLASH_LMA", flash);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash);
REGION_ALIAS("RODATA_FLASH_LMA", flash);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram4);
/* RAM region to be used for the nanoFramework CLR managed heap.*/
REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0);
/* RAM region to be used for the boot clipboard.*/
REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd);
INCLUDE rules.ld

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//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.
// See LICENSE file in the project root for full license information.
//
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 6
#define STM32_PLLN_VALUE 168
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSE
#define STM32_RTCPRE_VALUE 2
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 2
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 TRUE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 TRUE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED TRUE
#define STM32_PWM_USE_TIM1 TRUE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 TRUE
#define STM32_PWM_USE_TIM4 TRUE
#define STM32_PWM_USE_TIM5 TRUE
#define STM32_PWM_USE_TIM8 TRUE
#define STM32_PWM_USE_TIM9 FALSE // Turned off as not yet supported in 20.3
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
/*
* SDC driver system settings.
*/
#define STM32_SDC_SDIO_DMA_PRIORITY 3
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
#define STM32_SDC_WRITE_TIMEOUT_MS 1000
#define STM32_SDC_READ_TIMEOUT_MS 1000
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 TRUE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 TRUE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 TRUE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 TRUE
#define STM32_UART_USE_USART2 TRUE
#define STM32_UART_USE_USART3 TRUE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 TRUE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG TRUE
// header for nanoFramework overlay drivers
#include "mcuconf_nf.h"
#endif /* MCUCONF_H */

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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#ifndef _MCUCONF_NF_H_
#define _MCUCONF_NF_H_
#endif // _MCUCONF_NF_H_

8
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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#include <nanoHAL.h>
bool g_fDoNotUninitializeDebuggerPort = false;

18
CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/target_board.h.in Normal file
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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
//////////////////////////////////////////////////////////////////////////////
// This file was automatically generated by a tool. //
// Any changes you make here will be overwritten when it's generated again. //
//////////////////////////////////////////////////////////////////////////////
#ifndef _TARGET_BOARD_NANOCLR_H_
#define _TARGET_BOARD_NANOCLR_H_
#include <target_common.h>
#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_BOARD@"
#endif /* _TARGET_BOARD_NANOCLR_H_ */

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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#include <nanoPAL_BlockStorage.h>
extern struct BlockStorageDevice Device_BlockStorage;
extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig;
extern IBlockStorageDevice STM32Flash_BlockStorageInterface;
void BlockStorage_AddDevices()
{
BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false);
}

12
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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#ifndef _TARGETPAL_BLOCKSTORAGE_H_
#define _TARGETPAL_BLOCKSTORAGE_H_ 1
// this device has 1 block storage devices
#define TARGET_BLOCKSTORAGE_COUNT 1
#endif //_TARGETPAL_BLOCKSTORAGE_H_

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//
// Copyright (c) .NET Foundation and Contributors
// Portions Copyright (c) Microsoft Corporation. All rights reserved.
// See LICENSE file in the project root for full license information.
//
#include <nanoHAL_v2.h>
#include "target_board.h"
#include "target_common.h"
#include <platform_target_capabilities.h>
HAL_SYSTEM_CONFIG HalSystemConfig = {
{true}, // HAL_DRIVER_CONFIG_HEADER Header;
1, // ConvertCOM_DebugHandle(1),
0, // ConvertCOM_DebugHandle(0),
921600,
0, // STDIO = COM2 or COM1
{RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size},
{FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}};
HAL_TARGET_CONFIGURATION g_TargetConfiguration;
// this target uses DFU for updates
inline GET_TARGET_CAPABILITIES(TargetCapabilities_DfuUpdate);
inline TARGET_HAS_PROPRIETARY_BOOTER(true);

41
CMSIS-OS/ChibiOS/MBN_QUAIL/target_common.h.in Normal file
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@ -0,0 +1,41 @@
//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
//////////////////////////////////////////////////////////////////////////////
// This file was automatically generated by a tool. //
// Any changes you make here will be overwritten when it's generated again. //
//////////////////////////////////////////////////////////////////////////////
#ifndef _TARGET_COMMON_H_
#define _TARGET_COMMON_H_
#include <target_os.h>
/////////////////////////////////////////////////////////////////////////////////////////
// The following addresses and sizes should be filled in according to the SoC data-sheet
// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR
// RAM base address
#define RAM1_MEMORY_StartAddress ((uint32_t)0x200000C0)
// RAM size
#define RAM1_MEMORY_Size ((uint32_t)0x00030000)
// FLASH base address
#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000)
// FLASH size
#define FLASH1_MEMORY_Size ((uint32_t)0x00200000)
/////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////
#define TARGETNAMESTRING "@TARGET_BOARD@"
#define PLATFORMNAMESTRING "STM32F4"
//////////////////////////////////////////////
/////////////////////////////////////
//#define EVENTS_HEART_BEAT palToggleLine(GPIOE_LED1)
/////////////////////////////////////
#endif /* _TARGET_COMMON_H_ */

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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#include "target_nf_devices_onewire_config.h"
#include <nf_devices_onewire_native_target.h>
///////////
// UART6 //
///////////
// pin configuration for UART6
// port for TX pin is: GPIOC
// TX pin: is GPIOC_6
// GPIO alternate pin function is 8 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in
// STM32F405xx/STM32F407xx datasheet)
UART_CONFIG_PINS(6, GPIOC, 10, 8)
// buffers
// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary
// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache)
#if defined(__GNUC__)
__attribute__((aligned(32)))
#endif
uint8_t Uart6_TxBuffer[UART6_TX_SIZE];
#if defined(__GNUC__)
__attribute__((aligned(32)))
#endif
uint8_t Uart6_RxBuffer[UART6_RX_SIZE];

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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
///////////
// UART6 //
///////////
// enable USART6
#define NF_ONEWIRE_STM32_UART_USE_USART6 TRUE
// buffers size
// tx buffer size: 32 bytes
#define UART6_TX_SIZE 32
// rx buffer size: 32 bytes
#define UART6_RX_SIZE 32

18
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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#include <sys_dev_i2c_native_target.h>
//////////
// I2C1 //
//////////
// pin configuration for I2C1
// port for SCL pin is: GPIOB
// port for SDA pin is: GPIOB
// SCL pin: is GPIOB_6
// SDA pin: is GPIOB_7
// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet)
I2C_CONFIG_PINS(1, GPIOB, GPIOB, 6, 7, 4)

8
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@ -0,0 +1,8 @@
//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
//////////////////////////////////////////////////////////////////////////////////////////
// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T HAVE SUPPORT FOR DAC PINS //
//////////////////////////////////////////////////////////////////////////////////////////

18
CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_i2c_config.cpp Normal file
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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#include <Windows.Devices.I2c/win_dev_i2c_native_target.h>
//////////
// I2C1 //
//////////
// pin configuration for I2C1
// port for SCL pin is: GPIOB
// port for SDA pin is: GPIOB
// SCL pin: is GPIOB_6
// SDA pin: is GPIOB_7
// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet)
I2C_CONFIG_PINS(1, GPIOB, GPIOB, 6, 7, 4)

131
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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#include "target_windows_devices_serialcommunication_config.h"
#include <Windows.Devices.SerialCommunication/win_dev_serial_native_target.h>
///////////
// UART1 //
///////////
// pin configuration for UART1
// port for TX pin is: GPIOA
// port for RX pin is: GPIOA
// TX pin: is GPIOA_9
// RX pin: is GPIOA_10
// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in
// STM32F427xx and STM32F429xx datasheet)
UART_CONFIG_PINS(1, GPIOA, GPIOA, 9, 10, 7)
// buffers
// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary
// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache)
#if defined(__GNUC__)
__attribute__((aligned(32)))
#endif
uint8_t Uart1_TxBuffer[UART1_TX_SIZE];
#if defined(__GNUC__)
__attribute__((aligned(32)))
#endif
uint8_t Uart1_RxBuffer[UART1_RX_SIZE];
// initialization for UART1
UART_INIT(1, UART1_TX_SIZE, UART1_RX_SIZE)
// un-initialization for UART1
UART_UNINIT(1)
///////////
// UART2 //
///////////
// pin configuration for UART2
// port for TX pin is: GPIOD
// port for RX pin is: GPIOD
// TX pin: is GPIOD_5
// RX pin: is GPIOD_6
// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in
// STM32F427xx and STM32F429xx datasheet)
UART_CONFIG_PINS(2, GPIOD, GPIOD, 5, 6, 7)
// buffers
// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary
// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache)
#if defined(__GNUC__)
__attribute__((aligned(32)))
#endif
uint8_t Uart2_TxBuffer[UART2_TX_SIZE];
#if defined(__GNUC__)
__attribute__((aligned(32)))
#endif
uint8_t Uart2_RxBuffer[UART2_RX_SIZE];
// initialization for UART2
UART_INIT(2, UART2_TX_SIZE, UART2_RX_SIZE)
// un-initialization for UART2
UART_UNINIT(2)
///////////
// UART3 //
///////////
// pin configuration for UART3
// port for TX pin is: GPIOD
// port for RX pin is: GPIOD
// TX pin: is GPIOD_8
// RX pin: is GPIOD_9
// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in
// STM32F427xx and STM32F429xx datasheet)
UART_CONFIG_PINS(3, GPIOD, GPIOD, 8, 9, 7)
// buffers
// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary
// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache)
#if defined(__GNUC__)
__attribute__((aligned(32)))
#endif
uint8_t Uart3_TxBuffer[UART3_TX_SIZE];
#if defined(__GNUC__)
__attribute__((aligned(32)))
#endif
uint8_t Uart3_RxBuffer[UART3_RX_SIZE];
// initialization for UART3
UART_INIT(3, UART3_TX_SIZE, UART3_RX_SIZE)
// un-initialization for UART3
UART_UNINIT(3)
// ///////////
// // UART6 //
// ///////////
// // pin configuration for UART6
// // port for TX pin is: GPIOC
// // port for RX pin is: GPIOC
// // TX pin: is GPIOC_6
// // RX pin: is GPIOC_7
// // GPIO alternate pin function is 8 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in
// STM32F427xx and STM32F429xx datasheet) UART_CONFIG_PINS(6, GPIOC, GPIOC, 6, 7, 8)
// // buffers
// // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary
// // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache)
// #if defined(__GNUC__)
// __attribute__((aligned (32)))
// #endif
// uint8_t Uart6_TxBuffer[UART6_TX_SIZE];
// #if defined(__GNUC__)
// __attribute__((aligned (32)))
// #endif
// uint8_t Uart6_RxBuffer[UART6_RX_SIZE];
// // initialization for UART6
// UART_INIT(6, UART6_TX_SIZE, UART6_RX_SIZE)
// // un-initialization for UART6
// UART_UNINIT(6)

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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
///////////
// UART1 //
///////////
// enable USART1
#define NF_SERIAL_COMM_STM32_UART_USE_USART1 TRUE
// buffers size
// tx buffer size: 256 bytes
#define UART1_TX_SIZE 256
// rx buffer size: 256 bytes
#define UART1_RX_SIZE 256
///////////
// UART2 //
///////////
// enable USART2
#define NF_SERIAL_COMM_STM32_UART_USE_USART2 TRUE
// buffers size
// tx buffer size: 256 bytes
#define UART2_TX_SIZE 256
// rx buffer size: 256 bytes
#define UART2_RX_SIZE 256
///////////
// UART3 //
///////////
// enable USART3
#define NF_SERIAL_COMM_STM32_UART_USE_USART3 TRUE
// buffers size
// tx buffer size: 256 bytes
#define UART3_TX_SIZE 256
// rx buffer size: 256 bytes
#define UART3_RX_SIZE 256
// ///////////
// // UART6 //
// ///////////
// // enable USART6
// #define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE
// // buffers size
// // tx buffer size: 256 bytes
// #define UART6_TX_SIZE 256
// // rx buffer size: 256 bytes
// #define UART6_RX_SIZE 256

30
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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
#include <Windows.Devices.Spi/win_dev_spi_native_target.h>
//////////
// SPI1 //
//////////
// pin configuration for SPI1
// port for SCK pin is: GPIOB_SPI1_CLK
// port for MISO pin is: GPIOB_SPI1_MISO
// port for MOSI pin is: GPIOB_SPI1_MOSI
// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet)
SPI_CONFIG_PINS(1, GPIOB, 3, GPIOB, 4, GPIOB, 5, 5)
//////////
// SPI3 //
//////////
// pin configuration for SPI3
// port for SCK pin is: GPIOC_SPI3_CLK
// port for MISO pin is: GPIOC_SPI3_MISO
// port for MOSI pin is: GPIOC_SPI3_MOSI
// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet)
SPI_CONFIG_PINS(3, GPIOC, 10, GPIOC, 11, GPIOC, 12, 5)

13
CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_storage_config.h Normal file
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//
// Copyright (c) .NET Foundation and Contributors
// See LICENSE file in the project root for full license information.
//
// maps the SD Card driver
#define SD_CARD_DRIVER SDCD1
// maps the SD Card detect GPIO definition (in Target_Windows_Storage.c) to board GPIO line (in board.h)
#define SDCARD_LINE_DETECT LINE_SD_DETECT
// includes SPIFFS in storage
#define USE_SPIFFS_FOR_STORAGE FALSE

54
README.md
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@ -12,38 +12,40 @@ The provided boards are **NOT** supported by the **nanoFramework** team and any
## Available community boards
| Target name | Firmware Images | MCU | Frequency | FLASH | RAM |
|:-:|:-:|:-:|:-:|:-:|:-:|
| [GHI FEZ CERB40-I](CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/GHI_FEZ_CERB40_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/GHI_FEZ_CERB40_NF/_latestVersion) | STM32F405RG | 168 MHz | 1024 KB | 192 KB |
| [IngenuityMicro Electron](CMSIS-OS/ChibiOS/I2M_ELECTRON_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/I2M_ELECTRON_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/I2M_ELECTRON_NF/_latestVersion) | STM32F411CE | 100 MHz | 512 KB | 128 KB |
| [IngenuityMicro Oxygen](CMSIS-OS/ChibiOS/I2M_OXYGEN_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/I2M_OXYGEN_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/I2M_OXYGEN_NF/_latestVersion) | STM32F411CE | 100 MHz | 512 KB | 128 KB |
| [ST Nucleo64 F401RE](CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO64_F401RE_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO64_F401RE_NF/_latestVersion) | STM32F401RE | 84 MHz | 512 KB | 96 KB |
| [ST Nucleo64 F411RE](CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO64_F411RE_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO64_F411RE_NF/_latestVersion) | STM32F411RE | 100 MHz | 512 KB | 128 KB |
| [ST_STM32F411_DISCOVERY](CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_STM32F411_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_STM32F411_DISCOVERY/_latestVersion) | STM32F411VE | 100MHz | 512kB | 128kB |
| [ST Nucleo144 F412ZG](CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F412ZG_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F412ZG_NF/_latestVersion) | STM32F412ZG | 100 MHz | 1024 KB | 256 KB |
| [ST Nucleo144 F746ZG](CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F746ZG/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F746ZG/_latestVersion) | STM32F746ZG | 216 MHz | 1024 KB | 320 KB |
| [ST STM32F4DISCO](CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_STM32F4_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_STM32F4_DISCOVERY/_latestVersion) | STM32F407VGT6 | 168 MHz | 1024 KB | 192 KB |
| [ST Nucleo144 F439ZI](CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F439ZI/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F439ZI/_latestVersion) | STM32F439ZI | 180 MHz | 2048 KB | 256 KB |
| [TI_CC1352P1_LAUNCHXL](TI-SimpleLink/TI_CC1352P1_LAUNCHXL) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/TI_CC1352P1_LAUNCHXL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/TI_CC1352P1_LAUNCHXL/_latestVersion) | TI CC1352 | 48MHz | 352kB | 80kB |
| Target name | Firmware Images | MCU | Frequency | FLASH | RAM |
|:-: |:-: |:-: |:-: |:-: |:-: |
| [MBN_QUAIL](CMSIS-OS/ChibiOS/MBN_QUAIL) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/MBN_QUAIL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/MBN_QUAIL/_latestVersion) | | | | |
| [GHI FEZ CERB40-I](CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/GHI_FEZ_CERB40_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/GHI_FEZ_CERB40_NF/_latestVersion) | STM32F405RG | 168 MHz | 1024 KB | 192 KB |
| [IngenuityMicro Electron](CMSIS-OS/ChibiOS/I2M_ELECTRON_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/I2M_ELECTRON_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/I2M_ELECTRON_NF/_latestVersion) | STM32F411CE | 100 MHz | 512 KB | 128 KB |
| [IngenuityMicro Oxygen](CMSIS-OS/ChibiOS/I2M_OXYGEN_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/I2M_OXYGEN_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/I2M_OXYGEN_NF/_latestVersion) | STM32F411CE | 100 MHz | 512 KB | 128 KB |
| [ST Nucleo64 F401RE](CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO64_F401RE_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO64_F401RE_NF/_latestVersion) | STM32F401RE | 84 MHz | 512 KB | 96 KB |
| [ST Nucleo64 F411RE](CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO64_F411RE_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO64_F411RE_NF/_latestVersion) | STM32F411RE | 100 MHz | 512 KB | 128 KB |
| [ST_STM32F411_DISCOVERY](CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_STM32F411_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_STM32F411_DISCOVERY/_latestVersion) | STM32F411VE | 100MHz | 512kB | 128kB |
| [ST Nucleo144 F412ZG](CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F412ZG_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F412ZG_NF/_latestVersion) | STM32F412ZG | 100 MHz | 1024 KB | 256 KB |
| [ST Nucleo144 F746ZG](CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F746ZG/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F746ZG/_latestVersion) | STM32F746ZG | 216 MHz | 1024 KB | 320 KB |
| [ST STM32F4DISCO](CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_STM32F4_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_STM32F4_DISCOVERY/_latestVersion) | STM32F407VGT6 | 168 MHz | 1024 KB | 192 KB |
| [ST Nucleo144 F439ZI](CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F439ZI/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F439ZI/_latestVersion) | STM32F439ZI | 180 MHz | 2048 KB | 256 KB |
| [TI_CC1352P1_LAUNCHXL](TI-SimpleLink/TI_CC1352P1_LAUNCHXL) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/TI_CC1352P1_LAUNCHXL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/TI_CC1352P1_LAUNCHXL/_latestVersion) | TI CC1352 | 48MHz | 352kB | 80kB |
The above firmware builds include support for the class libraries and features marked below.
<details>
<summary>Click to expand!</summary>
| Target | Gpio | Spi | I2c | Pwm | Adc | Serial | OneWire | CAN | Events | SWO | Networking | Large Heap |
|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|
| GHI FEZ CERB40-I | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |:heavy_check_mark: | | | :heavy_check_mark: | | | |
| IngenuityMicro Electron | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | | | | |
| IngenuityMicro Oxygen | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | | | |
| ST Nucleo64 F401RE | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | | |
| ST Nucleo64 F411RE | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | | |
| ST STM32F411 DISCOVERY | :heavy_check_mark: | | | | | | | | | | | |
| ST Nucleo144 F412ZG | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | | |
| ST Nucleo144 F746ZG | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | |
| ST STM32F4DISCO | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | |
| ST Nucleo144 F439ZI | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | |
| TI CC1352P1 LAUNCHXL | :heavy_check_mark: | | | | | | | | | | | |
| Target | Gpio | Spi | I2c | Pwm | Adc | Dac | Serial | OneWire | CAN | Events | SWO | Networking | Large Heap | UI |
|:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: | |
| MBN_QUAIL | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | | |
| GHI FEZ CERB40-I | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | :heavy_check_mark: | | | | |
| IngenuityMicro Electron | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | | | | | |
| IngenuityMicro Oxygen | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | :heavy_check_mark: | | | | |
| ST Nucleo64 F401RE | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | | | |
| ST Nucleo64 F411RE | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | | | |
| ST STM32F411 DISCOVERY | :heavy_check_mark: | | | | | | | | | | | | | |
| ST Nucleo144 F412ZG | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | | | |
| ST Nucleo144 F746ZG | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | |
| ST STM32F4DISCO | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | |
| ST Nucleo144 F439ZI | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | |
| TI CC1352P1 LAUNCHXL | :heavy_check_mark: | | | | | | | | | | | | | |
</details>
## Feedback and documentation

38
azure-pipelines.yml
Просмотреть файл

@ -117,6 +117,7 @@ jobs:
"**Build ALL**" | Write-Host
}
elseif(
($COMMIT_MESSAGE -like "***MBN_QUAIL***") -Or
($COMMIT_MESSAGE -like "***GHI_FEZ_CERB40_NF***") -Or
($COMMIT_MESSAGE -like "***I2M_ELECTRON_NF***") -Or
($COMMIT_MESSAGE -like "***I2M_OXYGEN_NF***") -Or
@ -178,6 +179,43 @@ jobs:
name: BuildOptions
displayName: Evaluate build options
##############################
- job: Build_MBN_QUAIL
condition: or( contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***MBN_QUAIL***'), contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ALL***'), eq(variables['BUILD_ALL'], 'true'), eq(dependencies.Check_Build_Options.outputs['BuildOptions.GO'], 'True') )
dependsOn:
- Get_Commit_Message
- Check_Build_Options
pool:
vmImage: 'VS2017-Win2016'
variables:
TargetBoard: MBN_QUAIL
BuildOptions: -DTARGET_SERIES=STM32F4xx -DRTOS=CHIBIOS -DSUPPORT_ANY_BASE_CONVERSION=ON -DNF_FEATURE_DEBUGGER=ON -DNF_FEATURE_RTC=ON -DNF_FEATURE_HAS_SDCARD=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_System.Device.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_System.Device.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_nanoFramework.Devices.OneWire=ON -DAPI_Windows.Storage=ON -DAPI_nanoFramework.ResourceManager=ON -DAPI_nanoFramework.System.Collections=ON -DAPI_nanoFramework.System.Text=ON
# creates a counter and assigns it to the revision variable
REVISION: $[counter('MBN_QUAIL_versioncounter', 0)]
GccArm_Version:
NeedsDFU: true
steps:
- checkout: self
fetchDepth: 1
- template: azure-pipelines-templates/set-build-version.yml
- template: azure-pipelines-templates/clone-nf-interpreter-repo.yml
- template: azure-pipelines-templates/build-preparations.yml@templatesBuild
- template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml@templatesBuild
- template: azure-pipelines-templates/download-install-ninja.yml@templatesBuild
- template: azure-pipelines-templates/download-hexdfu.yml@templatesBuild
- template: azure-pipelines-templates/build-chibios-stm32.yml@templatesBuild
parameters:
buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build
- template: azure-pipelines-templates/pack-publish-artifacts.yml@templatesBuild
parameters:
buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build
- template: azure-pipelines-templates/publish-bintray.yml@templatesBuild
##############################
- job: Build_GHI_FEZ_CERB40_NF
condition: or( contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***GHI_FEZ_CERB40_NF***'), contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ALL***'), eq(variables['BUILD_ALL'], 'true'), eq(dependencies.Check_Build_Options.outputs['BuildOptions.GO'], 'True') )